| Line Number |
../DebugInfoTest/example_mips_dbg.ll
|
Hit count |
Line Number |
../DebugInfoTest/example_mips.ll
|
Hit count |
| 1 |
//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===// |
--- |
1 |
//===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===// |
--- |
| 2 |
// |
--- |
2 |
// |
--- |
| 3 |
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
--- |
3 |
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
--- |
| 4 |
// See https://llvm.org/LICENSE.txt for license information. |
--- |
4 |
// See https://llvm.org/LICENSE.txt for license information. |
--- |
| 5 |
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
--- |
5 |
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
--- |
| 6 |
// |
--- |
6 |
// |
--- |
| 7 |
//===----------------------------------------------------------------------===// |
--- |
7 |
//===----------------------------------------------------------------------===// |
--- |
| 8 |
// |
--- |
8 |
// |
--- |
| 9 |
// This implements routines for translating from LLVM IR into SelectionDAG IR. |
--- |
9 |
// This implements routines for translating from LLVM IR into SelectionDAG IR. |
--- |
| 10 |
// |
--- |
10 |
// |
--- |
| 11 |
//===----------------------------------------------------------------------===// |
--- |
11 |
//===----------------------------------------------------------------------===// |
--- |
| 12 |
|
--- |
12 |
|
--- |
| 13 |
#include "SelectionDAGBuilder.h" |
--- |
13 |
#include "SelectionDAGBuilder.h" |
--- |
| 14 |
#include "SDNodeDbgValue.h" |
--- |
14 |
#include "SDNodeDbgValue.h" |
--- |
| 15 |
#include "llvm/ADT/APFloat.h" |
--- |
15 |
#include "llvm/ADT/APFloat.h" |
--- |
| 16 |
#include "llvm/ADT/APInt.h" |
--- |
16 |
#include "llvm/ADT/APInt.h" |
--- |
| 17 |
#include "llvm/ADT/BitVector.h" |
--- |
17 |
#include "llvm/ADT/BitVector.h" |
--- |
| 18 |
#include "llvm/ADT/STLExtras.h" |
--- |
18 |
#include "llvm/ADT/STLExtras.h" |
--- |
| 19 |
#include "llvm/ADT/SmallPtrSet.h" |
--- |
19 |
#include "llvm/ADT/SmallPtrSet.h" |
--- |
| 20 |
#include "llvm/ADT/SmallSet.h" |
--- |
20 |
#include "llvm/ADT/SmallSet.h" |
--- |
| 21 |
#include "llvm/ADT/StringRef.h" |
--- |
21 |
#include "llvm/ADT/StringRef.h" |
--- |
| 22 |
#include "llvm/ADT/Twine.h" |
--- |
22 |
#include "llvm/ADT/Twine.h" |
--- |
| 23 |
#include "llvm/Analysis/AliasAnalysis.h" |
--- |
23 |
#include "llvm/Analysis/AliasAnalysis.h" |
--- |
| 24 |
#include "llvm/Analysis/BranchProbabilityInfo.h" |
--- |
24 |
#include "llvm/Analysis/BranchProbabilityInfo.h" |
--- |
| 25 |
#include "llvm/Analysis/ConstantFolding.h" |
--- |
25 |
#include "llvm/Analysis/ConstantFolding.h" |
--- |
| 26 |
#include "llvm/Analysis/Loads.h" |
--- |
26 |
#include "llvm/Analysis/Loads.h" |
--- |
| 27 |
#include "llvm/Analysis/MemoryLocation.h" |
--- |
27 |
#include "llvm/Analysis/MemoryLocation.h" |
--- |
| 28 |
#include "llvm/Analysis/TargetLibraryInfo.h" |
--- |
28 |
#include "llvm/Analysis/TargetLibraryInfo.h" |
--- |
| 29 |
#include "llvm/Analysis/ValueTracking.h" |
--- |
29 |
#include "llvm/Analysis/ValueTracking.h" |
--- |
| 30 |
#include "llvm/Analysis/VectorUtils.h" |
--- |
30 |
#include "llvm/Analysis/VectorUtils.h" |
--- |
| 31 |
#include "llvm/CodeGen/Analysis.h" |
--- |
31 |
#include "llvm/CodeGen/Analysis.h" |
--- |
| 32 |
#include "llvm/CodeGen/AssignmentTrackingAnalysis.h" |
--- |
32 |
#include "llvm/CodeGen/AssignmentTrackingAnalysis.h" |
--- |
| 33 |
#include "llvm/CodeGen/CodeGenCommonISel.h" |
--- |
33 |
#include "llvm/CodeGen/CodeGenCommonISel.h" |
--- |
| 34 |
#include "llvm/CodeGen/FunctionLoweringInfo.h" |
--- |
34 |
#include "llvm/CodeGen/FunctionLoweringInfo.h" |
--- |
| 35 |
#include "llvm/CodeGen/GCMetadata.h" |
--- |
35 |
#include "llvm/CodeGen/GCMetadata.h" |
--- |
| 36 |
#include "llvm/CodeGen/ISDOpcodes.h" |
--- |
36 |
#include "llvm/CodeGen/ISDOpcodes.h" |
--- |
| 37 |
#include "llvm/CodeGen/MachineBasicBlock.h" |
--- |
37 |
#include "llvm/CodeGen/MachineBasicBlock.h" |
--- |
| 38 |
#include "llvm/CodeGen/MachineFrameInfo.h" |
--- |
38 |
#include "llvm/CodeGen/MachineFrameInfo.h" |
--- |
| 39 |
#include "llvm/CodeGen/MachineFunction.h" |
--- |
39 |
#include "llvm/CodeGen/MachineFunction.h" |
--- |
| 40 |
#include "llvm/CodeGen/MachineInstrBuilder.h" |
--- |
40 |
#include "llvm/CodeGen/MachineInstrBuilder.h" |
--- |
| 41 |
#include "llvm/CodeGen/MachineInstrBundleIterator.h" |
--- |
41 |
#include "llvm/CodeGen/MachineInstrBundleIterator.h" |
--- |
| 42 |
#include "llvm/CodeGen/MachineMemOperand.h" |
--- |
42 |
#include "llvm/CodeGen/MachineMemOperand.h" |
--- |
| 43 |
#include "llvm/CodeGen/MachineModuleInfo.h" |
--- |
43 |
#include "llvm/CodeGen/MachineModuleInfo.h" |
--- |
| 44 |
#include "llvm/CodeGen/MachineOperand.h" |
--- |
44 |
#include "llvm/CodeGen/MachineOperand.h" |
--- |
| 45 |
#include "llvm/CodeGen/MachineRegisterInfo.h" |
--- |
45 |
#include "llvm/CodeGen/MachineRegisterInfo.h" |
--- |
| 46 |
#include "llvm/CodeGen/RuntimeLibcalls.h" |
--- |
46 |
#include "llvm/CodeGen/RuntimeLibcalls.h" |
--- |
| 47 |
#include "llvm/CodeGen/SelectionDAG.h" |
--- |
47 |
#include "llvm/CodeGen/SelectionDAG.h" |
--- |
| 48 |
#include "llvm/CodeGen/SelectionDAGTargetInfo.h" |
--- |
48 |
#include "llvm/CodeGen/SelectionDAGTargetInfo.h" |
--- |
| 49 |
#include "llvm/CodeGen/StackMaps.h" |
--- |
49 |
#include "llvm/CodeGen/StackMaps.h" |
--- |
| 50 |
#include "llvm/CodeGen/SwiftErrorValueTracking.h" |
--- |
50 |
#include "llvm/CodeGen/SwiftErrorValueTracking.h" |
--- |
| 51 |
#include "llvm/CodeGen/TargetFrameLowering.h" |
--- |
51 |
#include "llvm/CodeGen/TargetFrameLowering.h" |
--- |
| 52 |
#include "llvm/CodeGen/TargetInstrInfo.h" |
--- |
52 |
#include "llvm/CodeGen/TargetInstrInfo.h" |
--- |
| 53 |
#include "llvm/CodeGen/TargetOpcodes.h" |
--- |
53 |
#include "llvm/CodeGen/TargetOpcodes.h" |
--- |
| 54 |
#include "llvm/CodeGen/TargetRegisterInfo.h" |
--- |
54 |
#include "llvm/CodeGen/TargetRegisterInfo.h" |
--- |
| 55 |
#include "llvm/CodeGen/TargetSubtargetInfo.h" |
--- |
55 |
#include "llvm/CodeGen/TargetSubtargetInfo.h" |
--- |
| 56 |
#include "llvm/CodeGen/WinEHFuncInfo.h" |
--- |
56 |
#include "llvm/CodeGen/WinEHFuncInfo.h" |
--- |
| 57 |
#include "llvm/IR/Argument.h" |
--- |
57 |
#include "llvm/IR/Argument.h" |
--- |
| 58 |
#include "llvm/IR/Attributes.h" |
--- |
58 |
#include "llvm/IR/Attributes.h" |
--- |
| 59 |
#include "llvm/IR/BasicBlock.h" |
--- |
59 |
#include "llvm/IR/BasicBlock.h" |
--- |
| 60 |
#include "llvm/IR/CFG.h" |
--- |
60 |
#include "llvm/IR/CFG.h" |
--- |
| 61 |
#include "llvm/IR/CallingConv.h" |
--- |
61 |
#include "llvm/IR/CallingConv.h" |
--- |
| 62 |
#include "llvm/IR/Constant.h" |
--- |
62 |
#include "llvm/IR/Constant.h" |
--- |
| 63 |
#include "llvm/IR/ConstantRange.h" |
--- |
63 |
#include "llvm/IR/ConstantRange.h" |
--- |
| 64 |
#include "llvm/IR/Constants.h" |
--- |
64 |
#include "llvm/IR/Constants.h" |
--- |
| 65 |
#include "llvm/IR/DataLayout.h" |
--- |
65 |
#include "llvm/IR/DataLayout.h" |
--- |
| 66 |
#include "llvm/IR/DebugInfo.h" |
--- |
66 |
#include "llvm/IR/DebugInfo.h" |
--- |
| 67 |
#include "llvm/IR/DebugInfoMetadata.h" |
--- |
67 |
#include "llvm/IR/DebugInfoMetadata.h" |
--- |
| 68 |
#include "llvm/IR/DerivedTypes.h" |
--- |
68 |
#include "llvm/IR/DerivedTypes.h" |
--- |
| 69 |
#include "llvm/IR/DiagnosticInfo.h" |
--- |
69 |
#include "llvm/IR/DiagnosticInfo.h" |
--- |
| 70 |
#include "llvm/IR/EHPersonalities.h" |
--- |
70 |
#include "llvm/IR/EHPersonalities.h" |
--- |
| 71 |
#include "llvm/IR/Function.h" |
--- |
71 |
#include "llvm/IR/Function.h" |
--- |
| 72 |
#include "llvm/IR/GetElementPtrTypeIterator.h" |
--- |
72 |
#include "llvm/IR/GetElementPtrTypeIterator.h" |
--- |
| 73 |
#include "llvm/IR/InlineAsm.h" |
--- |
73 |
#include "llvm/IR/InlineAsm.h" |
--- |
| 74 |
#include "llvm/IR/InstrTypes.h" |
--- |
74 |
#include "llvm/IR/InstrTypes.h" |
--- |
| 75 |
#include "llvm/IR/Instructions.h" |
--- |
75 |
#include "llvm/IR/Instructions.h" |
--- |
| 76 |
#include "llvm/IR/IntrinsicInst.h" |
--- |
76 |
#include "llvm/IR/IntrinsicInst.h" |
--- |
| 77 |
#include "llvm/IR/Intrinsics.h" |
--- |
77 |
#include "llvm/IR/Intrinsics.h" |
--- |
| 78 |
#include "llvm/IR/IntrinsicsAArch64.h" |
--- |
78 |
#include "llvm/IR/IntrinsicsAArch64.h" |
--- |
| 79 |
#include "llvm/IR/IntrinsicsWebAssembly.h" |
--- |
79 |
#include "llvm/IR/IntrinsicsWebAssembly.h" |
--- |
| 80 |
#include "llvm/IR/LLVMContext.h" |
--- |
80 |
#include "llvm/IR/LLVMContext.h" |
--- |
| 81 |
#include "llvm/IR/Metadata.h" |
--- |
81 |
#include "llvm/IR/Metadata.h" |
--- |
| 82 |
#include "llvm/IR/Module.h" |
--- |
82 |
#include "llvm/IR/Module.h" |
--- |
| 83 |
#include "llvm/IR/Operator.h" |
--- |
83 |
#include "llvm/IR/Operator.h" |
--- |
| 84 |
#include "llvm/IR/PatternMatch.h" |
--- |
84 |
#include "llvm/IR/PatternMatch.h" |
--- |
| 85 |
#include "llvm/IR/Statepoint.h" |
--- |
85 |
#include "llvm/IR/Statepoint.h" |
--- |
| 86 |
#include "llvm/IR/Type.h" |
--- |
86 |
#include "llvm/IR/Type.h" |
--- |
| 87 |
#include "llvm/IR/User.h" |
--- |
87 |
#include "llvm/IR/User.h" |
--- |
| 88 |
#include "llvm/IR/Value.h" |
--- |
88 |
#include "llvm/IR/Value.h" |
--- |
| 89 |
#include "llvm/MC/MCContext.h" |
--- |
89 |
#include "llvm/MC/MCContext.h" |
--- |
| 90 |
#include "llvm/Support/AtomicOrdering.h" |
--- |
90 |
#include "llvm/Support/AtomicOrdering.h" |
--- |
| 91 |
#include "llvm/Support/Casting.h" |
--- |
91 |
#include "llvm/Support/Casting.h" |
--- |
| 92 |
#include "llvm/Support/CommandLine.h" |
--- |
92 |
#include "llvm/Support/CommandLine.h" |
--- |
| 93 |
#include "llvm/Support/Compiler.h" |
--- |
93 |
#include "llvm/Support/Compiler.h" |
--- |
| 94 |
#include "llvm/Support/Debug.h" |
--- |
94 |
#include "llvm/Support/Debug.h" |
--- |
| 95 |
#include "llvm/Support/MathExtras.h" |
--- |
95 |
#include "llvm/Support/MathExtras.h" |
--- |
| 96 |
#include "llvm/Support/raw_ostream.h" |
--- |
96 |
#include "llvm/Support/raw_ostream.h" |
--- |
| 97 |
#include "llvm/Target/TargetIntrinsicInfo.h" |
--- |
97 |
#include "llvm/Target/TargetIntrinsicInfo.h" |
--- |
| 98 |
#include "llvm/Target/TargetMachine.h" |
--- |
98 |
#include "llvm/Target/TargetMachine.h" |
--- |
| 99 |
#include "llvm/Target/TargetOptions.h" |
--- |
99 |
#include "llvm/Target/TargetOptions.h" |
--- |
| 100 |
#include "llvm/TargetParser/Triple.h" |
--- |
100 |
#include "llvm/TargetParser/Triple.h" |
--- |
| 101 |
#include "llvm/Transforms/Utils/Local.h" |
--- |
101 |
#include "llvm/Transforms/Utils/Local.h" |
--- |
| 102 |
#include |
--- |
102 |
#include |
--- |
| 103 |
#include |
--- |
103 |
#include |
--- |
| 104 |
#include |
--- |
104 |
#include |
--- |
| 105 |
#include |
--- |
105 |
#include |
--- |
| 106 |
#include |
--- |
106 |
#include |
--- |
| 107 |
|
--- |
107 |
|
--- |
| 108 |
using namespace llvm; |
--- |
108 |
using namespace llvm; |
--- |
| 109 |
using namespace PatternMatch; |
--- |
109 |
using namespace PatternMatch; |
--- |
| 110 |
using namespace SwitchCG; |
--- |
110 |
using namespace SwitchCG; |
--- |
| 111 |
|
--- |
111 |
|
--- |
| 112 |
#define DEBUG_TYPE "isel" |
--- |
112 |
#define DEBUG_TYPE "isel" |
--- |
| 113 |
|
--- |
113 |
|
--- |
| 114 |
/// LimitFloatPrecision - Generate low-precision inline sequences for |
--- |
114 |
/// LimitFloatPrecision - Generate low-precision inline sequences for |
--- |
| 115 |
/// some float libcalls (6, 8 or 12 bits). |
--- |
115 |
/// some float libcalls (6, 8 or 12 bits). |
--- |
| 116 |
static unsigned LimitFloatPrecision; |
--- |
116 |
static unsigned LimitFloatPrecision; |
--- |
| 117 |
|
--- |
117 |
|
--- |
| 118 |
static cl::opt |
--- |
118 |
static cl::opt |
--- |
| 119 |
InsertAssertAlign("insert-assert-align", cl::init(true), |
--- |
119 |
InsertAssertAlign("insert-assert-align", cl::init(true), |
--- |
| 120 |
cl::desc("Insert the experimental `assertalign` node."), |
--- |
120 |
cl::desc("Insert the experimental `assertalign` node."), |
--- |
| 121 |
cl::ReallyHidden); |
--- |
121 |
cl::ReallyHidden); |
--- |
| 122 |
|
--- |
122 |
|
--- |
| 123 |
static cl::opt |
--- |
123 |
static cl::opt |
--- |
| 124 |
LimitFPPrecision("limit-float-precision", |
--- |
124 |
LimitFPPrecision("limit-float-precision", |
--- |
| 125 |
cl::desc("Generate low-precision inline sequences " |
--- |
125 |
cl::desc("Generate low-precision inline sequences " |
--- |
| 126 |
"for some float libcalls"), |
--- |
126 |
"for some float libcalls"), |
--- |
| 127 |
cl::location(LimitFloatPrecision), cl::Hidden, |
--- |
127 |
cl::location(LimitFloatPrecision), cl::Hidden, |
--- |
| 128 |
cl::init(0)); |
--- |
128 |
cl::init(0)); |
--- |
| 129 |
|
--- |
129 |
|
--- |
| 130 |
static cl::opt SwitchPeelThreshold( |
--- |
130 |
static cl::opt SwitchPeelThreshold( |
--- |
| 131 |
"switch-peel-threshold", cl::Hidden, cl::init(66), |
--- |
131 |
"switch-peel-threshold", cl::Hidden, cl::init(66), |
--- |
| 132 |
cl::desc("Set the case probability threshold for peeling the case from a " |
--- |
132 |
cl::desc("Set the case probability threshold for peeling the case from a " |
--- |
| 133 |
"switch statement. A value greater than 100 will void this " |
--- |
133 |
"switch statement. A value greater than 100 will void this " |
--- |
| 134 |
"optimization")); |
--- |
134 |
"optimization")); |
--- |
| 135 |
|
--- |
135 |
|
--- |
| 136 |
// Limit the width of DAG chains. This is important in general to prevent |
--- |
136 |
// Limit the width of DAG chains. This is important in general to prevent |
--- |
| 137 |
// DAG-based analysis from blowing up. For example, alias analysis and |
--- |
137 |
// DAG-based analysis from blowing up. For example, alias analysis and |
--- |
| 138 |
// load clustering may not complete in reasonable time. It is difficult to |
--- |
138 |
// load clustering may not complete in reasonable time. It is difficult to |
--- |
| 139 |
// recognize and avoid this situation within each individual analysis, and |
--- |
139 |
// recognize and avoid this situation within each individual analysis, and |
--- |
| 140 |
// future analyses are likely to have the same behavior. Limiting DAG width is |
--- |
140 |
// future analyses are likely to have the same behavior. Limiting DAG width is |
--- |
| 141 |
// the safe approach and will be especially important with global DAGs. |
--- |
141 |
// the safe approach and will be especially important with global DAGs. |
--- |
| 142 |
// |
--- |
142 |
// |
--- |
| 143 |
// MaxParallelChains default is arbitrarily high to avoid affecting |
--- |
143 |
// MaxParallelChains default is arbitrarily high to avoid affecting |
--- |
| 144 |
// optimization, but could be lowered to improve compile time. Any ld-ld-st-st |
--- |
144 |
// optimization, but could be lowered to improve compile time. Any ld-ld-st-st |
--- |
| 145 |
// sequence over this should have been converted to llvm.memcpy by the |
--- |
145 |
// sequence over this should have been converted to llvm.memcpy by the |
--- |
| 146 |
// frontend. It is easy to induce this behavior with .ll code such as: |
--- |
146 |
// frontend. It is easy to induce this behavior with .ll code such as: |
--- |
| 147 |
// %buffer = alloca [4096 x i8] |
--- |
147 |
// %buffer = alloca [4096 x i8] |
--- |
| 148 |
// %data = load [4096 x i8]* %argPtr |
--- |
148 |
// %data = load [4096 x i8]* %argPtr |
--- |
| 149 |
// store [4096 x i8] %data, [4096 x i8]* %buffer |
--- |
149 |
// store [4096 x i8] %data, [4096 x i8]* %buffer |
--- |
| 150 |
static const unsigned MaxParallelChains = 64; |
--- |
150 |
static const unsigned MaxParallelChains = 64; |
--- |
| 151 |
|
--- |
151 |
|
--- |
| 152 |
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, |
--- |
152 |
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, |
--- |
| 153 |
const SDValue *Parts, unsigned NumParts, |
--- |
153 |
const SDValue *Parts, unsigned NumParts, |
--- |
| 154 |
MVT PartVT, EVT ValueVT, const Value *V, |
--- |
154 |
MVT PartVT, EVT ValueVT, const Value *V, |
--- |
| 155 |
std::optional CC); |
--- |
155 |
std::optional CC); |
--- |
| 156 |
|
--- |
156 |
|
--- |
| 157 |
/// getCopyFromParts - Create a value that contains the specified legal parts |
--- |
157 |
/// getCopyFromParts - Create a value that contains the specified legal parts |
--- |
| 158 |
/// combined into the value they represent. If the parts combine to a type |
--- |
158 |
/// combined into the value they represent. If the parts combine to a type |
--- |
| 159 |
/// larger than ValueVT then AssertOp can be used to specify whether the extra |
--- |
159 |
/// larger than ValueVT then AssertOp can be used to specify whether the extra |
--- |
| 160 |
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT |
--- |
160 |
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT |
--- |
| 161 |
/// (ISD::AssertSext). |
--- |
161 |
/// (ISD::AssertSext). |
--- |
| 162 |
static SDValue |
--- |
162 |
static SDValue |
--- |
| 163 |
getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, |
2 |
163 |
getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, |
2 |
| 164 |
unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, |
--- |
164 |
unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, |
--- |
| 165 |
std::optional CC = std::nullopt, |
--- |
165 |
std::optional CC = std::nullopt, |
--- |
| 166 |
std::optional AssertOp = std::nullopt) { |
--- |
166 |
std::optional AssertOp = std::nullopt) { |
--- |
| 167 |
// Let the target assemble the parts if it wants to |
--- |
167 |
// Let the target assemble the parts if it wants to |
--- |
| 168 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
2 |
168 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
2 |
| 169 |
if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts, |
4 |
169 |
if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts, |
4 |
| 170 |
PartVT, ValueVT, CC)) |
2 |
170 |
PartVT, ValueVT, CC)) |
2 |
| 171 |
return Val; |
0 |
171 |
return Val; |
0 |
| 172 |
|
--- |
172 |
|
--- |
| 173 |
if (ValueVT.isVector()) |
2 |
173 |
if (ValueVT.isVector()) |
2 |
| 174 |
return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, |
0 |
174 |
return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, |
0 |
| 175 |
CC); |
0 |
175 |
CC); |
0 |
| 176 |
|
--- |
176 |
|
--- |
| 177 |
assert(NumParts > 0 && "No parts to assemble!"); |
2 |
177 |
assert(NumParts > 0 && "No parts to assemble!"); |
2 |
| 178 |
SDValue Val = Parts[0]; |
2 |
178 |
SDValue Val = Parts[0]; |
2 |
| 179 |
|
--- |
179 |
|
--- |
| 180 |
if (NumParts > 1) { |
2 |
180 |
if (NumParts > 1) { |
2 |
| 181 |
// Assemble the value from multiple parts. |
--- |
181 |
// Assemble the value from multiple parts. |
--- |
| 182 |
if (ValueVT.isInteger()) { |
0 |
182 |
if (ValueVT.isInteger()) { |
0 |
| 183 |
unsigned PartBits = PartVT.getSizeInBits(); |
0 |
183 |
unsigned PartBits = PartVT.getSizeInBits(); |
0 |
| 184 |
unsigned ValueBits = ValueVT.getSizeInBits(); |
0 |
184 |
unsigned ValueBits = ValueVT.getSizeInBits(); |
0 |
| 185 |
|
--- |
185 |
|
--- |
| 186 |
// Assemble the power of 2 part. |
--- |
186 |
// Assemble the power of 2 part. |
--- |
| 187 |
unsigned RoundParts = llvm::bit_floor(NumParts); |
0 |
187 |
unsigned RoundParts = llvm::bit_floor(NumParts); |
0 |
| 188 |
unsigned RoundBits = PartBits * RoundParts; |
0 |
188 |
unsigned RoundBits = PartBits * RoundParts; |
0 |
| 189 |
EVT RoundVT = RoundBits == ValueBits ? |
--- |
189 |
EVT RoundVT = RoundBits == ValueBits ? |
--- |
| 190 |
ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); |
0 |
190 |
ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); |
0 |
| 191 |
SDValue Lo, Hi; |
0 |
191 |
SDValue Lo, Hi; |
0 |
| 192 |
|
--- |
192 |
|
--- |
| 193 |
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); |
0 |
193 |
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); |
0 |
| 194 |
|
--- |
194 |
|
--- |
| 195 |
if (RoundParts > 2) { |
0 |
195 |
if (RoundParts > 2) { |
0 |
| 196 |
Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, |
0 |
196 |
Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, |
0 |
| 197 |
PartVT, HalfVT, V); |
--- |
197 |
PartVT, HalfVT, V); |
--- |
| 198 |
Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, |
0 |
198 |
Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, |
0 |
| 199 |
RoundParts / 2, PartVT, HalfVT, V); |
--- |
199 |
RoundParts / 2, PartVT, HalfVT, V); |
--- |
| 200 |
} else { |
--- |
200 |
} else { |
--- |
| 201 |
Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); |
0 |
201 |
Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); |
0 |
| 202 |
Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); |
0 |
202 |
Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); |
0 |
| 203 |
} |
--- |
203 |
} |
--- |
| 204 |
|
--- |
204 |
|
--- |
| 205 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
205 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 206 |
std::swap(Lo, Hi); |
0 |
206 |
std::swap(Lo, Hi); |
0 |
| 207 |
|
--- |
207 |
|
--- |
| 208 |
Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); |
0 |
208 |
Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); |
0 |
| 209 |
|
--- |
209 |
|
--- |
| 210 |
if (RoundParts < NumParts) { |
0 |
210 |
if (RoundParts < NumParts) { |
0 |
| 211 |
// Assemble the trailing non-power-of-2 part. |
--- |
211 |
// Assemble the trailing non-power-of-2 part. |
--- |
| 212 |
unsigned OddParts = NumParts - RoundParts; |
0 |
212 |
unsigned OddParts = NumParts - RoundParts; |
0 |
| 213 |
EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); |
0 |
213 |
EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); |
0 |
| 214 |
Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, |
0 |
214 |
Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, |
0 |
| 215 |
OddVT, V, CC); |
--- |
215 |
OddVT, V, CC); |
--- |
| 216 |
|
--- |
216 |
|
--- |
| 217 |
// Combine the round and odd parts. |
--- |
217 |
// Combine the round and odd parts. |
--- |
| 218 |
Lo = Val; |
0 |
218 |
Lo = Val; |
0 |
| 219 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
219 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 220 |
std::swap(Lo, Hi); |
0 |
220 |
std::swap(Lo, Hi); |
0 |
| 221 |
EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
221 |
EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
| 222 |
Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); |
0 |
222 |
Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); |
0 |
| 223 |
Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, |
0 |
223 |
Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, |
0 |
| 224 |
DAG.getConstant(Lo.getValueSizeInBits(), DL, |
0 |
224 |
DAG.getConstant(Lo.getValueSizeInBits(), DL, |
0 |
| 225 |
TLI.getShiftAmountTy( |
--- |
225 |
TLI.getShiftAmountTy( |
--- |
| 226 |
TotalVT, DAG.getDataLayout()))); |
--- |
226 |
TotalVT, DAG.getDataLayout()))); |
--- |
| 227 |
Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); |
0 |
227 |
Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); |
0 |
| 228 |
Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); |
0 |
228 |
Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); |
0 |
| 229 |
} |
--- |
229 |
} |
--- |
| 230 |
} else if (PartVT.isFloatingPoint()) { |
0 |
230 |
} else if (PartVT.isFloatingPoint()) { |
0 |
| 231 |
// FP split into multiple FP parts (for ppcf128) |
--- |
231 |
// FP split into multiple FP parts (for ppcf128) |
--- |
| 232 |
assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && |
0 |
232 |
assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && |
0 |
| 233 |
"Unexpected split"); |
--- |
233 |
"Unexpected split"); |
--- |
| 234 |
SDValue Lo, Hi; |
0 |
234 |
SDValue Lo, Hi; |
0 |
| 235 |
Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); |
0 |
235 |
Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); |
0 |
| 236 |
Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); |
0 |
236 |
Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); |
0 |
| 237 |
if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) |
0 |
237 |
if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) |
0 |
| 238 |
std::swap(Lo, Hi); |
0 |
238 |
std::swap(Lo, Hi); |
0 |
| 239 |
Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); |
0 |
239 |
Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); |
0 |
| 240 |
} else { |
--- |
240 |
} else { |
--- |
| 241 |
// FP split into integer parts (soft fp) |
--- |
241 |
// FP split into integer parts (soft fp) |
--- |
| 242 |
assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && |
0 |
242 |
assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && |
0 |
| 243 |
!PartVT.isVector() && "Unexpected split"); |
--- |
243 |
!PartVT.isVector() && "Unexpected split"); |
--- |
| 244 |
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); |
0 |
244 |
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); |
0 |
| 245 |
Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); |
0 |
245 |
Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); |
0 |
| 246 |
} |
--- |
246 |
} |
--- |
| 247 |
} |
--- |
247 |
} |
--- |
| 248 |
|
--- |
248 |
|
--- |
| 249 |
// There is now one part, held in Val. Correct it to match ValueVT. |
--- |
249 |
// There is now one part, held in Val. Correct it to match ValueVT. |
--- |
| 250 |
// PartEVT is the type of the register class that holds the value. |
--- |
250 |
// PartEVT is the type of the register class that holds the value. |
--- |
| 251 |
// ValueVT is the type of the inline asm operation. |
--- |
251 |
// ValueVT is the type of the inline asm operation. |
--- |
| 252 |
EVT PartEVT = Val.getValueType(); |
2 |
252 |
EVT PartEVT = Val.getValueType(); |
2 |
| 253 |
|
--- |
253 |
|
--- |
| 254 |
if (PartEVT == ValueVT) |
2 |
254 |
if (PartEVT == ValueVT) |
2 |
| 255 |
return Val; |
2 |
255 |
return Val; |
2 |
| 256 |
|
--- |
256 |
|
--- |
| 257 |
if (PartEVT.isInteger() && ValueVT.isFloatingPoint() && |
0 |
257 |
if (PartEVT.isInteger() && ValueVT.isFloatingPoint() && |
0 |
| 258 |
ValueVT.bitsLT(PartEVT)) { |
0 |
258 |
ValueVT.bitsLT(PartEVT)) { |
0 |
| 259 |
// For an FP value in an integer part, we need to truncate to the right |
--- |
259 |
// For an FP value in an integer part, we need to truncate to the right |
--- |
| 260 |
// width first. |
--- |
260 |
// width first. |
--- |
| 261 |
PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); |
0 |
261 |
PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); |
0 |
| 262 |
Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val); |
0 |
262 |
Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val); |
0 |
| 263 |
} |
--- |
263 |
} |
--- |
| 264 |
|
--- |
264 |
|
--- |
| 265 |
// Handle types that have the same size. |
--- |
265 |
// Handle types that have the same size. |
--- |
| 266 |
if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) |
0 |
266 |
if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) |
0 |
| 267 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
267 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 268 |
|
--- |
268 |
|
--- |
| 269 |
// Handle types with different sizes. |
--- |
269 |
// Handle types with different sizes. |
--- |
| 270 |
if (PartEVT.isInteger() && ValueVT.isInteger()) { |
0 |
270 |
if (PartEVT.isInteger() && ValueVT.isInteger()) { |
0 |
| 271 |
if (ValueVT.bitsLT(PartEVT)) { |
0 |
271 |
if (ValueVT.bitsLT(PartEVT)) { |
0 |
| 272 |
// For a truncate, see if we have any information to |
--- |
272 |
// For a truncate, see if we have any information to |
--- |
| 273 |
// indicate whether the truncated bits will always be |
--- |
273 |
// indicate whether the truncated bits will always be |
--- |
| 274 |
// zero or sign-extension. |
--- |
274 |
// zero or sign-extension. |
--- |
| 275 |
if (AssertOp) |
0 |
275 |
if (AssertOp) |
0 |
| 276 |
Val = DAG.getNode(*AssertOp, DL, PartEVT, Val, |
0 |
276 |
Val = DAG.getNode(*AssertOp, DL, PartEVT, Val, |
0 |
| 277 |
DAG.getValueType(ValueVT)); |
--- |
277 |
DAG.getValueType(ValueVT)); |
--- |
| 278 |
return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
278 |
return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
| 279 |
} |
--- |
279 |
} |
--- |
| 280 |
return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); |
0 |
280 |
return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); |
0 |
| 281 |
} |
--- |
281 |
} |
--- |
| 282 |
|
--- |
282 |
|
--- |
| 283 |
if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { |
0 |
283 |
if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { |
0 |
| 284 |
// FP_ROUND's are always exact here. |
--- |
284 |
// FP_ROUND's are always exact here. |
--- |
| 285 |
if (ValueVT.bitsLT(Val.getValueType())) |
0 |
285 |
if (ValueVT.bitsLT(Val.getValueType())) |
0 |
| 286 |
return DAG.getNode( |
0 |
286 |
return DAG.getNode( |
0 |
| 287 |
ISD::FP_ROUND, DL, ValueVT, Val, |
--- |
287 |
ISD::FP_ROUND, DL, ValueVT, Val, |
--- |
| 288 |
DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
288 |
DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 289 |
|
--- |
289 |
|
--- |
| 290 |
return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); |
0 |
290 |
return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); |
0 |
| 291 |
} |
--- |
291 |
} |
--- |
| 292 |
|
--- |
292 |
|
--- |
| 293 |
// Handle MMX to a narrower integer type by bitcasting MMX to integer and |
--- |
293 |
// Handle MMX to a narrower integer type by bitcasting MMX to integer and |
--- |
| 294 |
// then truncating. |
--- |
294 |
// then truncating. |
--- |
| 295 |
if (PartEVT == MVT::x86mmx && ValueVT.isInteger() && |
0 |
295 |
if (PartEVT == MVT::x86mmx && ValueVT.isInteger() && |
0 |
| 296 |
ValueVT.bitsLT(PartEVT)) { |
0 |
296 |
ValueVT.bitsLT(PartEVT)) { |
0 |
| 297 |
Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val); |
0 |
297 |
Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val); |
0 |
| 298 |
return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
298 |
return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
| 299 |
} |
--- |
299 |
} |
--- |
| 300 |
|
--- |
300 |
|
--- |
| 301 |
report_fatal_error("Unknown mismatch in getCopyFromParts!"); |
0 |
301 |
report_fatal_error("Unknown mismatch in getCopyFromParts!"); |
0 |
| 302 |
} |
--- |
302 |
} |
--- |
| 303 |
|
--- |
303 |
|
--- |
| 304 |
static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, |
0 |
304 |
static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, |
0 |
| 305 |
const Twine &ErrMsg) { |
--- |
305 |
const Twine &ErrMsg) { |
--- |
| 306 |
const Instruction *I = dyn_cast_or_null(V); |
0 |
306 |
const Instruction *I = dyn_cast_or_null(V); |
0 |
| 307 |
if (!V) |
0 |
307 |
if (!V) |
0 |
| 308 |
return Ctx.emitError(ErrMsg); |
0 |
308 |
return Ctx.emitError(ErrMsg); |
0 |
| 309 |
|
--- |
309 |
|
--- |
| 310 |
const char *AsmError = ", possible invalid constraint for vector type"; |
0 |
310 |
const char *AsmError = ", possible invalid constraint for vector type"; |
0 |
| 311 |
if (const CallInst *CI = dyn_cast(I)) |
0 |
311 |
if (const CallInst *CI = dyn_cast(I)) |
0 |
| 312 |
if (CI->isInlineAsm()) |
0 |
312 |
if (CI->isInlineAsm()) |
0 |
| 313 |
return Ctx.emitError(I, ErrMsg + AsmError); |
0 |
313 |
return Ctx.emitError(I, ErrMsg + AsmError); |
0 |
| 314 |
|
--- |
314 |
|
--- |
| 315 |
return Ctx.emitError(I, ErrMsg); |
0 |
315 |
return Ctx.emitError(I, ErrMsg); |
0 |
| 316 |
} |
--- |
316 |
} |
--- |
| 317 |
|
--- |
317 |
|
--- |
| 318 |
/// getCopyFromPartsVector - Create a value that contains the specified legal |
--- |
318 |
/// getCopyFromPartsVector - Create a value that contains the specified legal |
--- |
| 319 |
/// parts combined into the value they represent. If the parts combine to a |
--- |
319 |
/// parts combined into the value they represent. If the parts combine to a |
--- |
| 320 |
/// type larger than ValueVT then AssertOp can be used to specify whether the |
--- |
320 |
/// type larger than ValueVT then AssertOp can be used to specify whether the |
--- |
| 321 |
/// extra bits are known to be zero (ISD::AssertZext) or sign extended from |
--- |
321 |
/// extra bits are known to be zero (ISD::AssertZext) or sign extended from |
--- |
| 322 |
/// ValueVT (ISD::AssertSext). |
--- |
322 |
/// ValueVT (ISD::AssertSext). |
--- |
| 323 |
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, |
0 |
323 |
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, |
0 |
| 324 |
const SDValue *Parts, unsigned NumParts, |
--- |
324 |
const SDValue *Parts, unsigned NumParts, |
--- |
| 325 |
MVT PartVT, EVT ValueVT, const Value *V, |
--- |
325 |
MVT PartVT, EVT ValueVT, const Value *V, |
--- |
| 326 |
std::optional CallConv) { |
--- |
326 |
std::optional CallConv) { |
--- |
| 327 |
assert(ValueVT.isVector() && "Not a vector value"); |
0 |
327 |
assert(ValueVT.isVector() && "Not a vector value"); |
0 |
| 328 |
assert(NumParts > 0 && "No parts to assemble!"); |
0 |
328 |
assert(NumParts > 0 && "No parts to assemble!"); |
0 |
| 329 |
const bool IsABIRegCopy = CallConv.has_value(); |
0 |
329 |
const bool IsABIRegCopy = CallConv.has_value(); |
0 |
| 330 |
|
--- |
330 |
|
--- |
| 331 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
331 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 332 |
SDValue Val = Parts[0]; |
0 |
332 |
SDValue Val = Parts[0]; |
0 |
| 333 |
|
--- |
333 |
|
--- |
| 334 |
// Handle a multi-element vector. |
--- |
334 |
// Handle a multi-element vector. |
--- |
| 335 |
if (NumParts > 1) { |
0 |
335 |
if (NumParts > 1) { |
0 |
| 336 |
EVT IntermediateVT; |
0 |
336 |
EVT IntermediateVT; |
0 |
| 337 |
MVT RegisterVT; |
0 |
337 |
MVT RegisterVT; |
0 |
| 338 |
unsigned NumIntermediates; |
--- |
338 |
unsigned NumIntermediates; |
--- |
| 339 |
unsigned NumRegs; |
--- |
339 |
unsigned NumRegs; |
--- |
| 340 |
|
--- |
340 |
|
--- |
| 341 |
if (IsABIRegCopy) { |
0 |
341 |
if (IsABIRegCopy) { |
0 |
| 342 |
NumRegs = TLI.getVectorTypeBreakdownForCallingConv( |
0 |
342 |
NumRegs = TLI.getVectorTypeBreakdownForCallingConv( |
0 |
| 343 |
*DAG.getContext(), *CallConv, ValueVT, IntermediateVT, |
0 |
343 |
*DAG.getContext(), *CallConv, ValueVT, IntermediateVT, |
0 |
| 344 |
NumIntermediates, RegisterVT); |
--- |
344 |
NumIntermediates, RegisterVT); |
--- |
| 345 |
} else { |
--- |
345 |
} else { |
--- |
| 346 |
NumRegs = |
--- |
346 |
NumRegs = |
--- |
| 347 |
TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, |
0 |
347 |
TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, |
0 |
| 348 |
NumIntermediates, RegisterVT); |
--- |
348 |
NumIntermediates, RegisterVT); |
--- |
| 349 |
} |
--- |
349 |
} |
--- |
| 350 |
|
--- |
350 |
|
--- |
| 351 |
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); |
0 |
351 |
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); |
0 |
| 352 |
NumParts = NumRegs; // Silence a compiler warning. |
0 |
352 |
NumParts = NumRegs; // Silence a compiler warning. |
0 |
| 353 |
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); |
0 |
353 |
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); |
0 |
| 354 |
assert(RegisterVT.getSizeInBits() == |
0 |
354 |
assert(RegisterVT.getSizeInBits() == |
0 |
| 355 |
Parts[0].getSimpleValueType().getSizeInBits() && |
--- |
355 |
Parts[0].getSimpleValueType().getSizeInBits() && |
--- |
| 356 |
"Part type sizes don't match!"); |
--- |
356 |
"Part type sizes don't match!"); |
--- |
| 357 |
|
--- |
357 |
|
--- |
| 358 |
// Assemble the parts into intermediate operands. |
--- |
358 |
// Assemble the parts into intermediate operands. |
--- |
| 359 |
SmallVector Ops(NumIntermediates); |
0 |
359 |
SmallVector Ops(NumIntermediates); |
0 |
| 360 |
if (NumIntermediates == NumParts) { |
0 |
360 |
if (NumIntermediates == NumParts) { |
0 |
| 361 |
// If the register was not expanded, truncate or copy the value, |
--- |
361 |
// If the register was not expanded, truncate or copy the value, |
--- |
| 362 |
// as appropriate. |
--- |
362 |
// as appropriate. |
--- |
| 363 |
for (unsigned i = 0; i != NumParts; ++i) |
0 |
363 |
for (unsigned i = 0; i != NumParts; ++i) |
0 |
| 364 |
Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, |
0 |
364 |
Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, |
0 |
| 365 |
PartVT, IntermediateVT, V, CallConv); |
--- |
365 |
PartVT, IntermediateVT, V, CallConv); |
--- |
| 366 |
} else if (NumParts > 0) { |
0 |
366 |
} else if (NumParts > 0) { |
0 |
| 367 |
// If the intermediate type was expanded, build the intermediate |
--- |
367 |
// If the intermediate type was expanded, build the intermediate |
--- |
| 368 |
// operands from the parts. |
--- |
368 |
// operands from the parts. |
--- |
| 369 |
assert(NumParts % NumIntermediates == 0 && |
0 |
369 |
assert(NumParts % NumIntermediates == 0 && |
0 |
| 370 |
"Must expand into a divisible number of parts!"); |
--- |
370 |
"Must expand into a divisible number of parts!"); |
--- |
| 371 |
unsigned Factor = NumParts / NumIntermediates; |
0 |
371 |
unsigned Factor = NumParts / NumIntermediates; |
0 |
| 372 |
for (unsigned i = 0; i != NumIntermediates; ++i) |
0 |
372 |
for (unsigned i = 0; i != NumIntermediates; ++i) |
0 |
| 373 |
Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, |
0 |
373 |
Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, |
0 |
| 374 |
PartVT, IntermediateVT, V, CallConv); |
--- |
374 |
PartVT, IntermediateVT, V, CallConv); |
--- |
| 375 |
} |
--- |
375 |
} |
--- |
| 376 |
|
--- |
376 |
|
--- |
| 377 |
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the |
--- |
377 |
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the |
--- |
| 378 |
// intermediate operands. |
--- |
378 |
// intermediate operands. |
--- |
| 379 |
EVT BuiltVectorTy = |
--- |
379 |
EVT BuiltVectorTy = |
--- |
| 380 |
IntermediateVT.isVector() |
0 |
380 |
IntermediateVT.isVector() |
0 |
| 381 |
? EVT::getVectorVT( |
0 |
381 |
? EVT::getVectorVT( |
0 |
| 382 |
*DAG.getContext(), IntermediateVT.getScalarType(), |
0 |
382 |
*DAG.getContext(), IntermediateVT.getScalarType(), |
0 |
| 383 |
IntermediateVT.getVectorElementCount() * NumParts) |
0 |
383 |
IntermediateVT.getVectorElementCount() * NumParts) |
0 |
| 384 |
: EVT::getVectorVT(*DAG.getContext(), |
0 |
384 |
: EVT::getVectorVT(*DAG.getContext(), |
0 |
| 385 |
IntermediateVT.getScalarType(), |
--- |
385 |
IntermediateVT.getScalarType(), |
--- |
| 386 |
NumIntermediates); |
0 |
386 |
NumIntermediates); |
0 |
| 387 |
Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS |
0 |
387 |
Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS |
0 |
| 388 |
: ISD::BUILD_VECTOR, |
--- |
388 |
: ISD::BUILD_VECTOR, |
--- |
| 389 |
DL, BuiltVectorTy, Ops); |
--- |
389 |
DL, BuiltVectorTy, Ops); |
--- |
| 390 |
} |
0 |
390 |
} |
0 |
| 391 |
|
--- |
391 |
|
--- |
| 392 |
// There is now one part, held in Val. Correct it to match ValueVT. |
--- |
392 |
// There is now one part, held in Val. Correct it to match ValueVT. |
--- |
| 393 |
EVT PartEVT = Val.getValueType(); |
0 |
393 |
EVT PartEVT = Val.getValueType(); |
0 |
| 394 |
|
--- |
394 |
|
--- |
| 395 |
if (PartEVT == ValueVT) |
0 |
395 |
if (PartEVT == ValueVT) |
0 |
| 396 |
return Val; |
0 |
396 |
return Val; |
0 |
| 397 |
|
--- |
397 |
|
--- |
| 398 |
if (PartEVT.isVector()) { |
0 |
398 |
if (PartEVT.isVector()) { |
0 |
| 399 |
// Vector/Vector bitcast. |
--- |
399 |
// Vector/Vector bitcast. |
--- |
| 400 |
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) |
0 |
400 |
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) |
0 |
| 401 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
401 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 402 |
|
--- |
402 |
|
--- |
| 403 |
// If the parts vector has more elements than the value vector, then we |
--- |
403 |
// If the parts vector has more elements than the value vector, then we |
--- |
| 404 |
// have a vector widening case (e.g. <2 x float> -> <4 x float>). |
--- |
404 |
// have a vector widening case (e.g. <2 x float> -> <4 x float>). |
--- |
| 405 |
// Extract the elements we want. |
--- |
405 |
// Extract the elements we want. |
--- |
| 406 |
if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) { |
0 |
406 |
if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) { |
0 |
| 407 |
assert((PartEVT.getVectorElementCount().getKnownMinValue() > |
0 |
407 |
assert((PartEVT.getVectorElementCount().getKnownMinValue() > |
0 |
| 408 |
ValueVT.getVectorElementCount().getKnownMinValue()) && |
--- |
408 |
ValueVT.getVectorElementCount().getKnownMinValue()) && |
--- |
| 409 |
(PartEVT.getVectorElementCount().isScalable() == |
--- |
409 |
(PartEVT.getVectorElementCount().isScalable() == |
--- |
| 410 |
ValueVT.getVectorElementCount().isScalable()) && |
--- |
410 |
ValueVT.getVectorElementCount().isScalable()) && |
--- |
| 411 |
"Cannot narrow, it would be a lossy transformation"); |
--- |
411 |
"Cannot narrow, it would be a lossy transformation"); |
--- |
| 412 |
PartEVT = |
--- |
412 |
PartEVT = |
--- |
| 413 |
EVT::getVectorVT(*DAG.getContext(), PartEVT.getVectorElementType(), |
0 |
413 |
EVT::getVectorVT(*DAG.getContext(), PartEVT.getVectorElementType(), |
0 |
| 414 |
ValueVT.getVectorElementCount()); |
--- |
414 |
ValueVT.getVectorElementCount()); |
--- |
| 415 |
Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val, |
0 |
415 |
Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val, |
0 |
| 416 |
DAG.getVectorIdxConstant(0, DL)); |
--- |
416 |
DAG.getVectorIdxConstant(0, DL)); |
--- |
| 417 |
if (PartEVT == ValueVT) |
0 |
417 |
if (PartEVT == ValueVT) |
0 |
| 418 |
return Val; |
0 |
418 |
return Val; |
0 |
| 419 |
if (PartEVT.isInteger() && ValueVT.isFloatingPoint()) |
0 |
419 |
if (PartEVT.isInteger() && ValueVT.isFloatingPoint()) |
0 |
| 420 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
420 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 421 |
|
--- |
421 |
|
--- |
| 422 |
// Vector/Vector bitcast (e.g. <2 x bfloat> -> <2 x half>). |
--- |
422 |
// Vector/Vector bitcast (e.g. <2 x bfloat> -> <2 x half>). |
--- |
| 423 |
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) |
0 |
423 |
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) |
0 |
| 424 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
424 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 425 |
} |
--- |
425 |
} |
--- |
| 426 |
|
--- |
426 |
|
--- |
| 427 |
// Promoted vector extract |
--- |
427 |
// Promoted vector extract |
--- |
| 428 |
return DAG.getAnyExtOrTrunc(Val, DL, ValueVT); |
0 |
428 |
return DAG.getAnyExtOrTrunc(Val, DL, ValueVT); |
0 |
| 429 |
} |
--- |
429 |
} |
--- |
| 430 |
|
--- |
430 |
|
--- |
| 431 |
// Trivial bitcast if the types are the same size and the destination |
--- |
431 |
// Trivial bitcast if the types are the same size and the destination |
--- |
| 432 |
// vector type is legal. |
--- |
432 |
// vector type is legal. |
--- |
| 433 |
if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && |
0 |
433 |
if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && |
0 |
| 434 |
TLI.isTypeLegal(ValueVT)) |
0 |
434 |
TLI.isTypeLegal(ValueVT)) |
0 |
| 435 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
435 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 436 |
|
--- |
436 |
|
--- |
| 437 |
if (ValueVT.getVectorNumElements() != 1) { |
0 |
437 |
if (ValueVT.getVectorNumElements() != 1) { |
0 |
| 438 |
// Certain ABIs require that vectors are passed as integers. For vectors |
--- |
438 |
// Certain ABIs require that vectors are passed as integers. For vectors |
--- |
| 439 |
// are the same size, this is an obvious bitcast. |
--- |
439 |
// are the same size, this is an obvious bitcast. |
--- |
| 440 |
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) { |
0 |
440 |
if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) { |
0 |
| 441 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
441 |
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 442 |
} else if (ValueVT.bitsLT(PartEVT)) { |
0 |
442 |
} else if (ValueVT.bitsLT(PartEVT)) { |
0 |
| 443 |
const uint64_t ValueSize = ValueVT.getFixedSizeInBits(); |
0 |
443 |
const uint64_t ValueSize = ValueVT.getFixedSizeInBits(); |
0 |
| 444 |
EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); |
0 |
444 |
EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); |
0 |
| 445 |
// Drop the extra bits. |
--- |
445 |
// Drop the extra bits. |
--- |
| 446 |
Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val); |
0 |
446 |
Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val); |
0 |
| 447 |
return DAG.getBitcast(ValueVT, Val); |
0 |
447 |
return DAG.getBitcast(ValueVT, Val); |
0 |
| 448 |
} |
--- |
448 |
} |
--- |
| 449 |
|
--- |
449 |
|
--- |
| 450 |
diagnosePossiblyInvalidConstraint( |
0 |
450 |
diagnosePossiblyInvalidConstraint( |
0 |
| 451 |
*DAG.getContext(), V, "non-trivial scalar-to-vector conversion"); |
0 |
451 |
*DAG.getContext(), V, "non-trivial scalar-to-vector conversion"); |
0 |
| 452 |
return DAG.getUNDEF(ValueVT); |
0 |
452 |
return DAG.getUNDEF(ValueVT); |
0 |
| 453 |
} |
--- |
453 |
} |
--- |
| 454 |
|
--- |
454 |
|
--- |
| 455 |
// Handle cases such as i8 -> <1 x i1> |
--- |
455 |
// Handle cases such as i8 -> <1 x i1> |
--- |
| 456 |
EVT ValueSVT = ValueVT.getVectorElementType(); |
0 |
456 |
EVT ValueSVT = ValueVT.getVectorElementType(); |
0 |
| 457 |
if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) { |
0 |
457 |
if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) { |
0 |
| 458 |
unsigned ValueSize = ValueSVT.getSizeInBits(); |
0 |
458 |
unsigned ValueSize = ValueSVT.getSizeInBits(); |
0 |
| 459 |
if (ValueSize == PartEVT.getSizeInBits()) { |
0 |
459 |
if (ValueSize == PartEVT.getSizeInBits()) { |
0 |
| 460 |
Val = DAG.getNode(ISD::BITCAST, DL, ValueSVT, Val); |
0 |
460 |
Val = DAG.getNode(ISD::BITCAST, DL, ValueSVT, Val); |
0 |
| 461 |
} else if (ValueSVT.isFloatingPoint() && PartEVT.isInteger()) { |
0 |
461 |
} else if (ValueSVT.isFloatingPoint() && PartEVT.isInteger()) { |
0 |
| 462 |
// It's possible a scalar floating point type gets softened to integer and |
--- |
462 |
// It's possible a scalar floating point type gets softened to integer and |
--- |
| 463 |
// then promoted to a larger integer. If PartEVT is the larger integer |
--- |
463 |
// then promoted to a larger integer. If PartEVT is the larger integer |
--- |
| 464 |
// we need to truncate it and then bitcast to the FP type. |
--- |
464 |
// we need to truncate it and then bitcast to the FP type. |
--- |
| 465 |
assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types"); |
0 |
465 |
assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types"); |
0 |
| 466 |
EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); |
0 |
466 |
EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); |
0 |
| 467 |
Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val); |
0 |
467 |
Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val); |
0 |
| 468 |
Val = DAG.getBitcast(ValueSVT, Val); |
0 |
468 |
Val = DAG.getBitcast(ValueSVT, Val); |
0 |
| 469 |
} else { |
--- |
469 |
} else { |
--- |
| 470 |
Val = ValueVT.isFloatingPoint() |
0 |
470 |
Val = ValueVT.isFloatingPoint() |
0 |
| 471 |
? DAG.getFPExtendOrRound(Val, DL, ValueSVT) |
0 |
471 |
? DAG.getFPExtendOrRound(Val, DL, ValueSVT) |
0 |
| 472 |
: DAG.getAnyExtOrTrunc(Val, DL, ValueSVT); |
0 |
472 |
: DAG.getAnyExtOrTrunc(Val, DL, ValueSVT); |
0 |
| 473 |
} |
--- |
473 |
} |
--- |
| 474 |
} |
--- |
474 |
} |
--- |
| 475 |
|
--- |
475 |
|
--- |
| 476 |
return DAG.getBuildVector(ValueVT, DL, Val); |
0 |
476 |
return DAG.getBuildVector(ValueVT, DL, Val); |
0 |
| 477 |
} |
--- |
477 |
} |
--- |
| 478 |
|
--- |
478 |
|
--- |
| 479 |
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, |
--- |
479 |
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, |
--- |
| 480 |
SDValue Val, SDValue *Parts, unsigned NumParts, |
--- |
480 |
SDValue Val, SDValue *Parts, unsigned NumParts, |
--- |
| 481 |
MVT PartVT, const Value *V, |
--- |
481 |
MVT PartVT, const Value *V, |
--- |
| 482 |
std::optional CallConv); |
--- |
482 |
std::optional CallConv); |
--- |
| 483 |
|
--- |
483 |
|
--- |
| 484 |
/// getCopyToParts - Create a series of nodes that contain the specified value |
--- |
484 |
/// getCopyToParts - Create a series of nodes that contain the specified value |
--- |
| 485 |
/// split into legal parts. If the parts contain more bits than Val, then, for |
--- |
485 |
/// split into legal parts. If the parts contain more bits than Val, then, for |
--- |
| 486 |
/// integers, ExtendKind can be used to specify how to generate the extra bits. |
--- |
486 |
/// integers, ExtendKind can be used to specify how to generate the extra bits. |
--- |
| 487 |
static void |
--- |
487 |
static void |
--- |
| 488 |
getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, |
1 |
488 |
getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, |
1 |
| 489 |
unsigned NumParts, MVT PartVT, const Value *V, |
--- |
489 |
unsigned NumParts, MVT PartVT, const Value *V, |
--- |
| 490 |
std::optional CallConv = std::nullopt, |
--- |
490 |
std::optional CallConv = std::nullopt, |
--- |
| 491 |
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { |
--- |
491 |
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { |
--- |
| 492 |
// Let the target split the parts if it wants to |
--- |
492 |
// Let the target split the parts if it wants to |
--- |
| 493 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
1 |
493 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
1 |
| 494 |
if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT, |
1 |
494 |
if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT, |
1 |
| 495 |
CallConv)) |
--- |
495 |
CallConv)) |
--- |
| 496 |
return; |
1 |
496 |
return; |
1 |
| 497 |
EVT ValueVT = Val.getValueType(); |
1 |
497 |
EVT ValueVT = Val.getValueType(); |
1 |
| 498 |
|
--- |
498 |
|
--- |
| 499 |
// Handle the vector case separately. |
--- |
499 |
// Handle the vector case separately. |
--- |
| 500 |
if (ValueVT.isVector()) |
1 |
500 |
if (ValueVT.isVector()) |
1 |
| 501 |
return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V, |
0 |
501 |
return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V, |
0 |
| 502 |
CallConv); |
0 |
502 |
CallConv); |
0 |
| 503 |
|
--- |
503 |
|
--- |
| 504 |
unsigned OrigNumParts = NumParts; |
1 |
504 |
unsigned OrigNumParts = NumParts; |
1 |
| 505 |
assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && |
1 |
505 |
assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && |
1 |
| 506 |
"Copying to an illegal type!"); |
--- |
506 |
"Copying to an illegal type!"); |
--- |
| 507 |
|
--- |
507 |
|
--- |
| 508 |
if (NumParts == 0) |
1 |
508 |
if (NumParts == 0) |
1 |
| 509 |
return; |
0 |
509 |
return; |
0 |
| 510 |
|
--- |
510 |
|
--- |
| 511 |
assert(!ValueVT.isVector() && "Vector case handled elsewhere"); |
1 |
511 |
assert(!ValueVT.isVector() && "Vector case handled elsewhere"); |
1 |
| 512 |
EVT PartEVT = PartVT; |
1 |
512 |
EVT PartEVT = PartVT; |
1 |
| 513 |
if (PartEVT == ValueVT) { |
1 |
513 |
if (PartEVT == ValueVT) { |
1 |
| 514 |
assert(NumParts == 1 && "No-op copy with multiple parts!"); |
1 |
514 |
assert(NumParts == 1 && "No-op copy with multiple parts!"); |
1 |
| 515 |
Parts[0] = Val; |
1 |
515 |
Parts[0] = Val; |
1 |
| 516 |
return; |
1 |
516 |
return; |
1 |
| 517 |
} |
--- |
517 |
} |
--- |
| 518 |
|
--- |
518 |
|
--- |
| 519 |
unsigned PartBits = PartVT.getSizeInBits(); |
0 |
519 |
unsigned PartBits = PartVT.getSizeInBits(); |
0 |
| 520 |
if (NumParts * PartBits > ValueVT.getSizeInBits()) { |
0 |
520 |
if (NumParts * PartBits > ValueVT.getSizeInBits()) { |
0 |
| 521 |
// If the parts cover more bits than the value has, promote the value. |
--- |
521 |
// If the parts cover more bits than the value has, promote the value. |
--- |
| 522 |
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { |
0 |
522 |
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { |
0 |
| 523 |
assert(NumParts == 1 && "Do not know what to promote to!"); |
0 |
523 |
assert(NumParts == 1 && "Do not know what to promote to!"); |
0 |
| 524 |
Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); |
0 |
524 |
Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); |
0 |
| 525 |
} else { |
--- |
525 |
} else { |
--- |
| 526 |
if (ValueVT.isFloatingPoint()) { |
0 |
526 |
if (ValueVT.isFloatingPoint()) { |
0 |
| 527 |
// FP values need to be bitcast, then extended if they are being put |
--- |
527 |
// FP values need to be bitcast, then extended if they are being put |
--- |
| 528 |
// into a larger container. |
--- |
528 |
// into a larger container. |
--- |
| 529 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); |
0 |
529 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); |
0 |
| 530 |
Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
530 |
Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); |
0 |
| 531 |
} |
--- |
531 |
} |
--- |
| 532 |
assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && |
0 |
532 |
assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && |
0 |
| 533 |
ValueVT.isInteger() && |
--- |
533 |
ValueVT.isInteger() && |
--- |
| 534 |
"Unknown mismatch!"); |
--- |
534 |
"Unknown mismatch!"); |
--- |
| 535 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
535 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
| 536 |
Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); |
0 |
536 |
Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); |
0 |
| 537 |
if (PartVT == MVT::x86mmx) |
0 |
537 |
if (PartVT == MVT::x86mmx) |
0 |
| 538 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
538 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
| 539 |
} |
--- |
539 |
} |
--- |
| 540 |
} else if (PartBits == ValueVT.getSizeInBits()) { |
0 |
540 |
} else if (PartBits == ValueVT.getSizeInBits()) { |
0 |
| 541 |
// Different types of the same size. |
--- |
541 |
// Different types of the same size. |
--- |
| 542 |
assert(NumParts == 1 && PartEVT != ValueVT); |
0 |
542 |
assert(NumParts == 1 && PartEVT != ValueVT); |
0 |
| 543 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
543 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
| 544 |
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) { |
0 |
544 |
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) { |
0 |
| 545 |
// If the parts cover less bits than value has, truncate the value. |
--- |
545 |
// If the parts cover less bits than value has, truncate the value. |
--- |
| 546 |
assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && |
0 |
546 |
assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && |
0 |
| 547 |
ValueVT.isInteger() && |
--- |
547 |
ValueVT.isInteger() && |
--- |
| 548 |
"Unknown mismatch!"); |
--- |
548 |
"Unknown mismatch!"); |
--- |
| 549 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
549 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
| 550 |
Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
550 |
Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
| 551 |
if (PartVT == MVT::x86mmx) |
0 |
551 |
if (PartVT == MVT::x86mmx) |
0 |
| 552 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
552 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
| 553 |
} |
--- |
553 |
} |
--- |
| 554 |
|
--- |
554 |
|
--- |
| 555 |
// The value may have changed - recompute ValueVT. |
--- |
555 |
// The value may have changed - recompute ValueVT. |
--- |
| 556 |
ValueVT = Val.getValueType(); |
0 |
556 |
ValueVT = Val.getValueType(); |
0 |
| 557 |
assert(NumParts * PartBits == ValueVT.getSizeInBits() && |
0 |
557 |
assert(NumParts * PartBits == ValueVT.getSizeInBits() && |
0 |
| 558 |
"Failed to tile the value with PartVT!"); |
--- |
558 |
"Failed to tile the value with PartVT!"); |
--- |
| 559 |
|
--- |
559 |
|
--- |
| 560 |
if (NumParts == 1) { |
0 |
560 |
if (NumParts == 1) { |
0 |
| 561 |
if (PartEVT != ValueVT) { |
0 |
561 |
if (PartEVT != ValueVT) { |
0 |
| 562 |
diagnosePossiblyInvalidConstraint(*DAG.getContext(), V, |
0 |
562 |
diagnosePossiblyInvalidConstraint(*DAG.getContext(), V, |
0 |
| 563 |
"scalar-to-vector conversion failed"); |
--- |
563 |
"scalar-to-vector conversion failed"); |
--- |
| 564 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
564 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
| 565 |
} |
--- |
565 |
} |
--- |
| 566 |
|
--- |
566 |
|
--- |
| 567 |
Parts[0] = Val; |
0 |
567 |
Parts[0] = Val; |
0 |
| 568 |
return; |
0 |
568 |
return; |
0 |
| 569 |
} |
--- |
569 |
} |
--- |
| 570 |
|
--- |
570 |
|
--- |
| 571 |
// Expand the value into multiple parts. |
--- |
571 |
// Expand the value into multiple parts. |
--- |
| 572 |
if (NumParts & (NumParts - 1)) { |
0 |
572 |
if (NumParts & (NumParts - 1)) { |
0 |
| 573 |
// The number of parts is not a power of 2. Split off and copy the tail. |
--- |
573 |
// The number of parts is not a power of 2. Split off and copy the tail. |
--- |
| 574 |
assert(PartVT.isInteger() && ValueVT.isInteger() && |
0 |
574 |
assert(PartVT.isInteger() && ValueVT.isInteger() && |
0 |
| 575 |
"Do not know what to expand to!"); |
--- |
575 |
"Do not know what to expand to!"); |
--- |
| 576 |
unsigned RoundParts = llvm::bit_floor(NumParts); |
0 |
576 |
unsigned RoundParts = llvm::bit_floor(NumParts); |
0 |
| 577 |
unsigned RoundBits = RoundParts * PartBits; |
0 |
577 |
unsigned RoundBits = RoundParts * PartBits; |
0 |
| 578 |
unsigned OddParts = NumParts - RoundParts; |
0 |
578 |
unsigned OddParts = NumParts - RoundParts; |
0 |
| 579 |
SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, |
0 |
579 |
SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, |
0 |
| 580 |
DAG.getShiftAmountConstant(RoundBits, ValueVT, DL)); |
--- |
580 |
DAG.getShiftAmountConstant(RoundBits, ValueVT, DL)); |
--- |
| 581 |
|
--- |
581 |
|
--- |
| 582 |
getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V, |
0 |
582 |
getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V, |
0 |
| 583 |
CallConv); |
--- |
583 |
CallConv); |
--- |
| 584 |
|
--- |
584 |
|
--- |
| 585 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
585 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 586 |
// The odd parts were reversed by getCopyToParts - unreverse them. |
--- |
586 |
// The odd parts were reversed by getCopyToParts - unreverse them. |
--- |
| 587 |
std::reverse(Parts + RoundParts, Parts + NumParts); |
0 |
587 |
std::reverse(Parts + RoundParts, Parts + NumParts); |
0 |
| 588 |
|
--- |
588 |
|
--- |
| 589 |
NumParts = RoundParts; |
0 |
589 |
NumParts = RoundParts; |
0 |
| 590 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
590 |
ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); |
0 |
| 591 |
Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
591 |
Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); |
0 |
| 592 |
} |
--- |
592 |
} |
--- |
| 593 |
|
--- |
593 |
|
--- |
| 594 |
// The number of parts is a power of 2. Repeatedly bisect the value using |
--- |
594 |
// The number of parts is a power of 2. Repeatedly bisect the value using |
--- |
| 595 |
// EXTRACT_ELEMENT. |
--- |
595 |
// EXTRACT_ELEMENT. |
--- |
| 596 |
Parts[0] = DAG.getNode(ISD::BITCAST, DL, |
0 |
596 |
Parts[0] = DAG.getNode(ISD::BITCAST, DL, |
0 |
| 597 |
EVT::getIntegerVT(*DAG.getContext(), |
0 |
597 |
EVT::getIntegerVT(*DAG.getContext(), |
0 |
| 598 |
ValueVT.getSizeInBits()), |
0 |
598 |
ValueVT.getSizeInBits()), |
0 |
| 599 |
Val); |
--- |
599 |
Val); |
--- |
| 600 |
|
--- |
600 |
|
--- |
| 601 |
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { |
0 |
601 |
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { |
0 |
| 602 |
for (unsigned i = 0; i < NumParts; i += StepSize) { |
0 |
602 |
for (unsigned i = 0; i < NumParts; i += StepSize) { |
0 |
| 603 |
unsigned ThisBits = StepSize * PartBits / 2; |
0 |
603 |
unsigned ThisBits = StepSize * PartBits / 2; |
0 |
| 604 |
EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); |
0 |
604 |
EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); |
0 |
| 605 |
SDValue &Part0 = Parts[i]; |
0 |
605 |
SDValue &Part0 = Parts[i]; |
0 |
| 606 |
SDValue &Part1 = Parts[i+StepSize/2]; |
0 |
606 |
SDValue &Part1 = Parts[i+StepSize/2]; |
0 |
| 607 |
|
--- |
607 |
|
--- |
| 608 |
Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, |
0 |
608 |
Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, |
0 |
| 609 |
ThisVT, Part0, DAG.getIntPtrConstant(1, DL)); |
--- |
609 |
ThisVT, Part0, DAG.getIntPtrConstant(1, DL)); |
--- |
| 610 |
Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, |
0 |
610 |
Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, |
0 |
| 611 |
ThisVT, Part0, DAG.getIntPtrConstant(0, DL)); |
--- |
611 |
ThisVT, Part0, DAG.getIntPtrConstant(0, DL)); |
--- |
| 612 |
|
--- |
612 |
|
--- |
| 613 |
if (ThisBits == PartBits && ThisVT != PartVT) { |
0 |
613 |
if (ThisBits == PartBits && ThisVT != PartVT) { |
0 |
| 614 |
Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); |
0 |
614 |
Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); |
0 |
| 615 |
Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); |
0 |
615 |
Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); |
0 |
| 616 |
} |
--- |
616 |
} |
--- |
| 617 |
} |
--- |
617 |
} |
--- |
| 618 |
} |
--- |
618 |
} |
--- |
| 619 |
|
--- |
619 |
|
--- |
| 620 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
620 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 621 |
std::reverse(Parts, Parts + OrigNumParts); |
0 |
621 |
std::reverse(Parts, Parts + OrigNumParts); |
0 |
| 622 |
} |
--- |
622 |
} |
--- |
| 623 |
|
--- |
623 |
|
--- |
| 624 |
static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val, |
0 |
624 |
static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val, |
0 |
| 625 |
const SDLoc &DL, EVT PartVT) { |
--- |
625 |
const SDLoc &DL, EVT PartVT) { |
--- |
| 626 |
if (!PartVT.isVector()) |
0 |
626 |
if (!PartVT.isVector()) |
0 |
| 627 |
return SDValue(); |
0 |
627 |
return SDValue(); |
0 |
| 628 |
|
--- |
628 |
|
--- |
| 629 |
EVT ValueVT = Val.getValueType(); |
0 |
629 |
EVT ValueVT = Val.getValueType(); |
0 |
| 630 |
EVT PartEVT = PartVT.getVectorElementType(); |
0 |
630 |
EVT PartEVT = PartVT.getVectorElementType(); |
0 |
| 631 |
EVT ValueEVT = ValueVT.getVectorElementType(); |
0 |
631 |
EVT ValueEVT = ValueVT.getVectorElementType(); |
0 |
| 632 |
ElementCount PartNumElts = PartVT.getVectorElementCount(); |
0 |
632 |
ElementCount PartNumElts = PartVT.getVectorElementCount(); |
0 |
| 633 |
ElementCount ValueNumElts = ValueVT.getVectorElementCount(); |
0 |
633 |
ElementCount ValueNumElts = ValueVT.getVectorElementCount(); |
0 |
| 634 |
|
--- |
634 |
|
--- |
| 635 |
// We only support widening vectors with equivalent element types and |
--- |
635 |
// We only support widening vectors with equivalent element types and |
--- |
| 636 |
// fixed/scalable properties. If a target needs to widen a fixed-length type |
--- |
636 |
// fixed/scalable properties. If a target needs to widen a fixed-length type |
--- |
| 637 |
// to a scalable one, it should be possible to use INSERT_SUBVECTOR below. |
--- |
637 |
// to a scalable one, it should be possible to use INSERT_SUBVECTOR below. |
--- |
| 638 |
if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) || |
0 |
638 |
if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) || |
0 |
| 639 |
PartNumElts.isScalable() != ValueNumElts.isScalable()) |
0 |
639 |
PartNumElts.isScalable() != ValueNumElts.isScalable()) |
0 |
| 640 |
return SDValue(); |
0 |
640 |
return SDValue(); |
0 |
| 641 |
|
--- |
641 |
|
--- |
| 642 |
// Have a try for bf16 because some targets share its ABI with fp16. |
--- |
642 |
// Have a try for bf16 because some targets share its ABI with fp16. |
--- |
| 643 |
if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) { |
0 |
643 |
if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) { |
0 |
| 644 |
assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && |
0 |
644 |
assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && |
0 |
| 645 |
"Cannot widen to illegal type"); |
--- |
645 |
"Cannot widen to illegal type"); |
--- |
| 646 |
Val = DAG.getNode(ISD::BITCAST, DL, |
0 |
646 |
Val = DAG.getNode(ISD::BITCAST, DL, |
0 |
| 647 |
ValueVT.changeVectorElementType(MVT::f16), Val); |
0 |
647 |
ValueVT.changeVectorElementType(MVT::f16), Val); |
0 |
| 648 |
} else if (PartEVT != ValueEVT) { |
0 |
648 |
} else if (PartEVT != ValueEVT) { |
0 |
| 649 |
return SDValue(); |
0 |
649 |
return SDValue(); |
0 |
| 650 |
} |
--- |
650 |
} |
--- |
| 651 |
|
--- |
651 |
|
--- |
| 652 |
// Widening a scalable vector to another scalable vector is done by inserting |
--- |
652 |
// Widening a scalable vector to another scalable vector is done by inserting |
--- |
| 653 |
// the vector into a larger undef one. |
--- |
653 |
// the vector into a larger undef one. |
--- |
| 654 |
if (PartNumElts.isScalable()) |
0 |
654 |
if (PartNumElts.isScalable()) |
0 |
| 655 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), |
0 |
655 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), |
0 |
| 656 |
Val, DAG.getVectorIdxConstant(0, DL)); |
0 |
656 |
Val, DAG.getVectorIdxConstant(0, DL)); |
0 |
| 657 |
|
--- |
657 |
|
--- |
| 658 |
// Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in |
--- |
658 |
// Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in |
--- |
| 659 |
// undef elements. |
--- |
659 |
// undef elements. |
--- |
| 660 |
SmallVector Ops; |
0 |
660 |
SmallVector Ops; |
0 |
| 661 |
DAG.ExtractVectorElements(Val, Ops); |
0 |
661 |
DAG.ExtractVectorElements(Val, Ops); |
0 |
| 662 |
SDValue EltUndef = DAG.getUNDEF(PartEVT); |
0 |
662 |
SDValue EltUndef = DAG.getUNDEF(PartEVT); |
0 |
| 663 |
Ops.append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef); |
0 |
663 |
Ops.append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef); |
0 |
| 664 |
|
--- |
664 |
|
--- |
| 665 |
// FIXME: Use CONCAT for 2x -> 4x. |
--- |
665 |
// FIXME: Use CONCAT for 2x -> 4x. |
--- |
| 666 |
return DAG.getBuildVector(PartVT, DL, Ops); |
0 |
666 |
return DAG.getBuildVector(PartVT, DL, Ops); |
0 |
| 667 |
} |
0 |
667 |
} |
0 |
| 668 |
|
--- |
668 |
|
--- |
| 669 |
/// getCopyToPartsVector - Create a series of nodes that contain the specified |
--- |
669 |
/// getCopyToPartsVector - Create a series of nodes that contain the specified |
--- |
| 670 |
/// value split into legal parts. |
--- |
670 |
/// value split into legal parts. |
--- |
| 671 |
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL, |
0 |
671 |
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL, |
0 |
| 672 |
SDValue Val, SDValue *Parts, unsigned NumParts, |
--- |
672 |
SDValue Val, SDValue *Parts, unsigned NumParts, |
--- |
| 673 |
MVT PartVT, const Value *V, |
--- |
673 |
MVT PartVT, const Value *V, |
--- |
| 674 |
std::optional CallConv) { |
--- |
674 |
std::optional CallConv) { |
--- |
| 675 |
EVT ValueVT = Val.getValueType(); |
0 |
675 |
EVT ValueVT = Val.getValueType(); |
0 |
| 676 |
assert(ValueVT.isVector() && "Not a vector"); |
0 |
676 |
assert(ValueVT.isVector() && "Not a vector"); |
0 |
| 677 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
677 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 678 |
const bool IsABIRegCopy = CallConv.has_value(); |
0 |
678 |
const bool IsABIRegCopy = CallConv.has_value(); |
0 |
| 679 |
|
--- |
679 |
|
--- |
| 680 |
if (NumParts == 1) { |
0 |
680 |
if (NumParts == 1) { |
0 |
| 681 |
EVT PartEVT = PartVT; |
0 |
681 |
EVT PartEVT = PartVT; |
0 |
| 682 |
if (PartEVT == ValueVT) { |
0 |
682 |
if (PartEVT == ValueVT) { |
0 |
| 683 |
// Nothing to do. |
--- |
683 |
// Nothing to do. |
--- |
| 684 |
} else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { |
0 |
684 |
} else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { |
0 |
| 685 |
// Bitconvert vector->vector case. |
--- |
685 |
// Bitconvert vector->vector case. |
--- |
| 686 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
686 |
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); |
0 |
| 687 |
} else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) { |
0 |
687 |
} else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) { |
0 |
| 688 |
Val = Widened; |
0 |
688 |
Val = Widened; |
0 |
| 689 |
} else if (PartVT.isVector() && |
0 |
689 |
} else if (PartVT.isVector() && |
0 |
| 690 |
PartEVT.getVectorElementType().bitsGE( |
0 |
690 |
PartEVT.getVectorElementType().bitsGE( |
0 |
| 691 |
ValueVT.getVectorElementType()) && |
0 |
691 |
ValueVT.getVectorElementType()) && |
0 |
| 692 |
PartEVT.getVectorElementCount() == |
0 |
692 |
PartEVT.getVectorElementCount() == |
0 |
| 693 |
ValueVT.getVectorElementCount()) { |
0 |
693 |
ValueVT.getVectorElementCount()) { |
0 |
| 694 |
|
--- |
694 |
|
--- |
| 695 |
// Promoted vector extract |
--- |
695 |
// Promoted vector extract |
--- |
| 696 |
Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); |
0 |
696 |
Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); |
0 |
| 697 |
} else if (PartEVT.isVector() && |
0 |
697 |
} else if (PartEVT.isVector() && |
0 |
| 698 |
PartEVT.getVectorElementType() != |
0 |
698 |
PartEVT.getVectorElementType() != |
0 |
| 699 |
ValueVT.getVectorElementType() && |
0 |
699 |
ValueVT.getVectorElementType() && |
0 |
| 700 |
TLI.getTypeAction(*DAG.getContext(), ValueVT) == |
0 |
700 |
TLI.getTypeAction(*DAG.getContext(), ValueVT) == |
0 |
| 701 |
TargetLowering::TypeWidenVector) { |
--- |
701 |
TargetLowering::TypeWidenVector) { |
--- |
| 702 |
// Combination of widening and promotion. |
--- |
702 |
// Combination of widening and promotion. |
--- |
| 703 |
EVT WidenVT = |
--- |
703 |
EVT WidenVT = |
--- |
| 704 |
EVT::getVectorVT(*DAG.getContext(), ValueVT.getVectorElementType(), |
0 |
704 |
EVT::getVectorVT(*DAG.getContext(), ValueVT.getVectorElementType(), |
0 |
| 705 |
PartVT.getVectorElementCount()); |
--- |
705 |
PartVT.getVectorElementCount()); |
--- |
| 706 |
SDValue Widened = widenVectorToPartType(DAG, Val, DL, WidenVT); |
0 |
706 |
SDValue Widened = widenVectorToPartType(DAG, Val, DL, WidenVT); |
0 |
| 707 |
Val = DAG.getAnyExtOrTrunc(Widened, DL, PartVT); |
0 |
707 |
Val = DAG.getAnyExtOrTrunc(Widened, DL, PartVT); |
0 |
| 708 |
} else { |
--- |
708 |
} else { |
--- |
| 709 |
// Don't extract an integer from a float vector. This can happen if the |
--- |
709 |
// Don't extract an integer from a float vector. This can happen if the |
--- |
| 710 |
// FP type gets softened to integer and then promoted. The promotion |
--- |
710 |
// FP type gets softened to integer and then promoted. The promotion |
--- |
| 711 |
// prevents it from being picked up by the earlier bitcast case. |
--- |
711 |
// prevents it from being picked up by the earlier bitcast case. |
--- |
| 712 |
if (ValueVT.getVectorElementCount().isScalar() && |
0 |
712 |
if (ValueVT.getVectorElementCount().isScalar() && |
0 |
| 713 |
(!ValueVT.isFloatingPoint() || !PartVT.isInteger())) { |
0 |
713 |
(!ValueVT.isFloatingPoint() || !PartVT.isInteger())) { |
0 |
| 714 |
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val, |
0 |
714 |
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val, |
0 |
| 715 |
DAG.getVectorIdxConstant(0, DL)); |
--- |
715 |
DAG.getVectorIdxConstant(0, DL)); |
--- |
| 716 |
} else { |
--- |
716 |
} else { |
--- |
| 717 |
uint64_t ValueSize = ValueVT.getFixedSizeInBits(); |
0 |
717 |
uint64_t ValueSize = ValueVT.getFixedSizeInBits(); |
0 |
| 718 |
assert(PartVT.getFixedSizeInBits() > ValueSize && |
0 |
718 |
assert(PartVT.getFixedSizeInBits() > ValueSize && |
0 |
| 719 |
"lossy conversion of vector to scalar type"); |
--- |
719 |
"lossy conversion of vector to scalar type"); |
--- |
| 720 |
EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); |
0 |
720 |
EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); |
0 |
| 721 |
Val = DAG.getBitcast(IntermediateType, Val); |
0 |
721 |
Val = DAG.getBitcast(IntermediateType, Val); |
0 |
| 722 |
Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); |
0 |
722 |
Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); |
0 |
| 723 |
} |
--- |
723 |
} |
--- |
| 724 |
} |
--- |
724 |
} |
--- |
| 725 |
|
--- |
725 |
|
--- |
| 726 |
assert(Val.getValueType() == PartVT && "Unexpected vector part value type"); |
0 |
726 |
assert(Val.getValueType() == PartVT && "Unexpected vector part value type"); |
0 |
| 727 |
Parts[0] = Val; |
0 |
727 |
Parts[0] = Val; |
0 |
| 728 |
return; |
0 |
728 |
return; |
0 |
| 729 |
} |
--- |
729 |
} |
--- |
| 730 |
|
--- |
730 |
|
--- |
| 731 |
// Handle a multi-element vector. |
--- |
731 |
// Handle a multi-element vector. |
--- |
| 732 |
EVT IntermediateVT; |
0 |
732 |
EVT IntermediateVT; |
0 |
| 733 |
MVT RegisterVT; |
0 |
733 |
MVT RegisterVT; |
0 |
| 734 |
unsigned NumIntermediates; |
--- |
734 |
unsigned NumIntermediates; |
--- |
| 735 |
unsigned NumRegs; |
--- |
735 |
unsigned NumRegs; |
--- |
| 736 |
if (IsABIRegCopy) { |
0 |
736 |
if (IsABIRegCopy) { |
0 |
| 737 |
NumRegs = TLI.getVectorTypeBreakdownForCallingConv( |
0 |
737 |
NumRegs = TLI.getVectorTypeBreakdownForCallingConv( |
0 |
| 738 |
*DAG.getContext(), *CallConv, ValueVT, IntermediateVT, NumIntermediates, |
0 |
738 |
*DAG.getContext(), *CallConv, ValueVT, IntermediateVT, NumIntermediates, |
0 |
| 739 |
RegisterVT); |
--- |
739 |
RegisterVT); |
--- |
| 740 |
} else { |
--- |
740 |
} else { |
--- |
| 741 |
NumRegs = |
--- |
741 |
NumRegs = |
--- |
| 742 |
TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, |
0 |
742 |
TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, |
0 |
| 743 |
NumIntermediates, RegisterVT); |
--- |
743 |
NumIntermediates, RegisterVT); |
--- |
| 744 |
} |
--- |
744 |
} |
--- |
| 745 |
|
--- |
745 |
|
--- |
| 746 |
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); |
0 |
746 |
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); |
0 |
| 747 |
NumParts = NumRegs; // Silence a compiler warning. |
0 |
747 |
NumParts = NumRegs; // Silence a compiler warning. |
0 |
| 748 |
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); |
0 |
748 |
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); |
0 |
| 749 |
|
--- |
749 |
|
--- |
| 750 |
assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() && |
0 |
750 |
assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() && |
0 |
| 751 |
"Mixing scalable and fixed vectors when copying in parts"); |
--- |
751 |
"Mixing scalable and fixed vectors when copying in parts"); |
--- |
| 752 |
|
--- |
752 |
|
--- |
| 753 |
std::optional DestEltCnt; |
0 |
753 |
std::optional DestEltCnt; |
0 |
| 754 |
|
--- |
754 |
|
--- |
| 755 |
if (IntermediateVT.isVector()) |
0 |
755 |
if (IntermediateVT.isVector()) |
0 |
| 756 |
DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates; |
0 |
756 |
DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates; |
0 |
| 757 |
else |
--- |
757 |
else |
--- |
| 758 |
DestEltCnt = ElementCount::getFixed(NumIntermediates); |
0 |
758 |
DestEltCnt = ElementCount::getFixed(NumIntermediates); |
0 |
| 759 |
|
--- |
759 |
|
--- |
| 760 |
EVT BuiltVectorTy = EVT::getVectorVT( |
0 |
760 |
EVT BuiltVectorTy = EVT::getVectorVT( |
0 |
| 761 |
*DAG.getContext(), IntermediateVT.getScalarType(), *DestEltCnt); |
0 |
761 |
*DAG.getContext(), IntermediateVT.getScalarType(), *DestEltCnt); |
0 |
| 762 |
|
--- |
762 |
|
--- |
| 763 |
if (ValueVT == BuiltVectorTy) { |
0 |
763 |
if (ValueVT == BuiltVectorTy) { |
0 |
| 764 |
// Nothing to do. |
--- |
764 |
// Nothing to do. |
--- |
| 765 |
} else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) { |
0 |
765 |
} else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) { |
0 |
| 766 |
// Bitconvert vector->vector case. |
--- |
766 |
// Bitconvert vector->vector case. |
--- |
| 767 |
Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val); |
0 |
767 |
Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val); |
0 |
| 768 |
} else { |
--- |
768 |
} else { |
--- |
| 769 |
if (BuiltVectorTy.getVectorElementType().bitsGT( |
0 |
769 |
if (BuiltVectorTy.getVectorElementType().bitsGT( |
0 |
| 770 |
ValueVT.getVectorElementType())) { |
--- |
770 |
ValueVT.getVectorElementType())) { |
--- |
| 771 |
// Integer promotion. |
--- |
771 |
// Integer promotion. |
--- |
| 772 |
ValueVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
772 |
ValueVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
| 773 |
BuiltVectorTy.getVectorElementType(), |
--- |
773 |
BuiltVectorTy.getVectorElementType(), |
--- |
| 774 |
ValueVT.getVectorElementCount()); |
--- |
774 |
ValueVT.getVectorElementCount()); |
--- |
| 775 |
Val = DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); |
0 |
775 |
Val = DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); |
0 |
| 776 |
} |
--- |
776 |
} |
--- |
| 777 |
|
--- |
777 |
|
--- |
| 778 |
if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy)) { |
0 |
778 |
if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy)) { |
0 |
| 779 |
Val = Widened; |
0 |
779 |
Val = Widened; |
0 |
| 780 |
} |
--- |
780 |
} |
--- |
| 781 |
} |
--- |
781 |
} |
--- |
| 782 |
|
--- |
782 |
|
--- |
| 783 |
assert(Val.getValueType() == BuiltVectorTy && "Unexpected vector value type"); |
0 |
783 |
assert(Val.getValueType() == BuiltVectorTy && "Unexpected vector value type"); |
0 |
| 784 |
|
--- |
784 |
|
--- |
| 785 |
// Split the vector into intermediate operands. |
--- |
785 |
// Split the vector into intermediate operands. |
--- |
| 786 |
SmallVector Ops(NumIntermediates); |
0 |
786 |
SmallVector Ops(NumIntermediates); |
0 |
| 787 |
for (unsigned i = 0; i != NumIntermediates; ++i) { |
0 |
787 |
for (unsigned i = 0; i != NumIntermediates; ++i) { |
0 |
| 788 |
if (IntermediateVT.isVector()) { |
0 |
788 |
if (IntermediateVT.isVector()) { |
0 |
| 789 |
// This does something sensible for scalable vectors - see the |
--- |
789 |
// This does something sensible for scalable vectors - see the |
--- |
| 790 |
// definition of EXTRACT_SUBVECTOR for further details. |
--- |
790 |
// definition of EXTRACT_SUBVECTOR for further details. |
--- |
| 791 |
unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements(); |
0 |
791 |
unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements(); |
0 |
| 792 |
Ops[i] = |
0 |
792 |
Ops[i] = |
0 |
| 793 |
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, |
0 |
793 |
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, |
0 |
| 794 |
DAG.getVectorIdxConstant(i * IntermediateNumElts, DL)); |
0 |
794 |
DAG.getVectorIdxConstant(i * IntermediateNumElts, DL)); |
0 |
| 795 |
} else { |
--- |
795 |
} else { |
--- |
| 796 |
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val, |
0 |
796 |
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val, |
0 |
| 797 |
DAG.getVectorIdxConstant(i, DL)); |
--- |
797 |
DAG.getVectorIdxConstant(i, DL)); |
--- |
| 798 |
} |
--- |
798 |
} |
--- |
| 799 |
} |
--- |
799 |
} |
--- |
| 800 |
|
--- |
800 |
|
--- |
| 801 |
// Split the intermediate operands into legal parts. |
--- |
801 |
// Split the intermediate operands into legal parts. |
--- |
| 802 |
if (NumParts == NumIntermediates) { |
0 |
802 |
if (NumParts == NumIntermediates) { |
0 |
| 803 |
// If the register was not expanded, promote or copy the value, |
--- |
803 |
// If the register was not expanded, promote or copy the value, |
--- |
| 804 |
// as appropriate. |
--- |
804 |
// as appropriate. |
--- |
| 805 |
for (unsigned i = 0; i != NumParts; ++i) |
0 |
805 |
for (unsigned i = 0; i != NumParts; ++i) |
0 |
| 806 |
getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv); |
0 |
806 |
getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv); |
0 |
| 807 |
} else if (NumParts > 0) { |
0 |
807 |
} else if (NumParts > 0) { |
0 |
| 808 |
// If the intermediate type was expanded, split each the value into |
--- |
808 |
// If the intermediate type was expanded, split each the value into |
--- |
| 809 |
// legal parts. |
--- |
809 |
// legal parts. |
--- |
| 810 |
assert(NumIntermediates != 0 && "division by zero"); |
0 |
810 |
assert(NumIntermediates != 0 && "division by zero"); |
0 |
| 811 |
assert(NumParts % NumIntermediates == 0 && |
0 |
811 |
assert(NumParts % NumIntermediates == 0 && |
0 |
| 812 |
"Must expand into a divisible number of parts!"); |
--- |
812 |
"Must expand into a divisible number of parts!"); |
--- |
| 813 |
unsigned Factor = NumParts / NumIntermediates; |
0 |
813 |
unsigned Factor = NumParts / NumIntermediates; |
0 |
| 814 |
for (unsigned i = 0; i != NumIntermediates; ++i) |
0 |
814 |
for (unsigned i = 0; i != NumIntermediates; ++i) |
0 |
| 815 |
getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V, |
0 |
815 |
getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V, |
0 |
| 816 |
CallConv); |
--- |
816 |
CallConv); |
--- |
| 817 |
} |
--- |
817 |
} |
--- |
| 818 |
} |
0 |
818 |
} |
0 |
| 819 |
|
--- |
819 |
|
--- |
| 820 |
RegsForValue::RegsForValue(const SmallVector ®s, MVT regvt, |
0 |
820 |
RegsForValue::RegsForValue(const SmallVector ®s, MVT regvt, |
0 |
| 821 |
EVT valuevt, std::optional CC) |
--- |
821 |
EVT valuevt, std::optional CC) |
--- |
| 822 |
: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), |
0 |
822 |
: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), |
0 |
| 823 |
RegCount(1, regs.size()), CallConv(CC) {} |
0 |
823 |
RegCount(1, regs.size()), CallConv(CC) {} |
0 |
| 824 |
|
--- |
824 |
|
--- |
| 825 |
RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI, |
0 |
825 |
RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI, |
0 |
| 826 |
const DataLayout &DL, unsigned Reg, Type *Ty, |
--- |
826 |
const DataLayout &DL, unsigned Reg, Type *Ty, |
--- |
| 827 |
std::optional CC) { |
0 |
827 |
std::optional CC) { |
0 |
| 828 |
ComputeValueVTs(TLI, DL, Ty, ValueVTs); |
0 |
828 |
ComputeValueVTs(TLI, DL, Ty, ValueVTs); |
0 |
| 829 |
|
--- |
829 |
|
--- |
| 830 |
CallConv = CC; |
0 |
830 |
CallConv = CC; |
0 |
| 831 |
|
--- |
831 |
|
--- |
| 832 |
for (EVT ValueVT : ValueVTs) { |
0 |
832 |
for (EVT ValueVT : ValueVTs) { |
0 |
| 833 |
unsigned NumRegs = |
--- |
833 |
unsigned NumRegs = |
--- |
| 834 |
isABIMangled() |
0 |
834 |
isABIMangled() |
0 |
| 835 |
? TLI.getNumRegistersForCallingConv(Context, *CC, ValueVT) |
0 |
835 |
? TLI.getNumRegistersForCallingConv(Context, *CC, ValueVT) |
0 |
| 836 |
: TLI.getNumRegisters(Context, ValueVT); |
0 |
836 |
: TLI.getNumRegisters(Context, ValueVT); |
0 |
| 837 |
MVT RegisterVT = |
--- |
837 |
MVT RegisterVT = |
--- |
| 838 |
isABIMangled() |
0 |
838 |
isABIMangled() |
0 |
| 839 |
? TLI.getRegisterTypeForCallingConv(Context, *CC, ValueVT) |
0 |
839 |
? TLI.getRegisterTypeForCallingConv(Context, *CC, ValueVT) |
0 |
| 840 |
: TLI.getRegisterType(Context, ValueVT); |
0 |
840 |
: TLI.getRegisterType(Context, ValueVT); |
0 |
| 841 |
for (unsigned i = 0; i != NumRegs; ++i) |
0 |
841 |
for (unsigned i = 0; i != NumRegs; ++i) |
0 |
| 842 |
Regs.push_back(Reg + i); |
0 |
842 |
Regs.push_back(Reg + i); |
0 |
| 843 |
RegVTs.push_back(RegisterVT); |
0 |
843 |
RegVTs.push_back(RegisterVT); |
0 |
| 844 |
RegCount.push_back(NumRegs); |
0 |
844 |
RegCount.push_back(NumRegs); |
0 |
| 845 |
Reg += NumRegs; |
0 |
845 |
Reg += NumRegs; |
0 |
| 846 |
} |
--- |
846 |
} |
--- |
| 847 |
} |
0 |
847 |
} |
0 |
| 848 |
|
--- |
848 |
|
--- |
| 849 |
SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, |
0 |
849 |
SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, |
0 |
| 850 |
FunctionLoweringInfo &FuncInfo, |
--- |
850 |
FunctionLoweringInfo &FuncInfo, |
--- |
| 851 |
const SDLoc &dl, SDValue &Chain, |
--- |
851 |
const SDLoc &dl, SDValue &Chain, |
--- |
| 852 |
SDValue *Glue, const Value *V) const { |
--- |
852 |
SDValue *Glue, const Value *V) const { |
--- |
| 853 |
// A Value with type {} or [0 x %t] needs no registers. |
--- |
853 |
// A Value with type {} or [0 x %t] needs no registers. |
--- |
| 854 |
if (ValueVTs.empty()) |
0 |
854 |
if (ValueVTs.empty()) |
0 |
| 855 |
return SDValue(); |
0 |
855 |
return SDValue(); |
0 |
| 856 |
|
--- |
856 |
|
--- |
| 857 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
857 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 858 |
|
--- |
858 |
|
--- |
| 859 |
// Assemble the legal parts into the final values. |
--- |
859 |
// Assemble the legal parts into the final values. |
--- |
| 860 |
SmallVector Values(ValueVTs.size()); |
0 |
860 |
SmallVector Values(ValueVTs.size()); |
0 |
| 861 |
SmallVector Parts; |
0 |
861 |
SmallVector Parts; |
0 |
| 862 |
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { |
0 |
862 |
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { |
0 |
| 863 |
// Copy the legal parts from the registers. |
--- |
863 |
// Copy the legal parts from the registers. |
--- |
| 864 |
EVT ValueVT = ValueVTs[Value]; |
0 |
864 |
EVT ValueVT = ValueVTs[Value]; |
0 |
| 865 |
unsigned NumRegs = RegCount[Value]; |
0 |
865 |
unsigned NumRegs = RegCount[Value]; |
0 |
| 866 |
MVT RegisterVT = isABIMangled() |
0 |
866 |
MVT RegisterVT = isABIMangled() |
0 |
| 867 |
? TLI.getRegisterTypeForCallingConv( |
0 |
867 |
? TLI.getRegisterTypeForCallingConv( |
0 |
| 868 |
*DAG.getContext(), *CallConv, RegVTs[Value]) |
0 |
868 |
*DAG.getContext(), *CallConv, RegVTs[Value]) |
0 |
| 869 |
: RegVTs[Value]; |
0 |
869 |
: RegVTs[Value]; |
0 |
| 870 |
|
--- |
870 |
|
--- |
| 871 |
Parts.resize(NumRegs); |
0 |
871 |
Parts.resize(NumRegs); |
0 |
| 872 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
872 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
| 873 |
SDValue P; |
0 |
873 |
SDValue P; |
0 |
| 874 |
if (!Glue) { |
0 |
874 |
if (!Glue) { |
0 |
| 875 |
P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); |
0 |
875 |
P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); |
0 |
| 876 |
} else { |
--- |
876 |
} else { |
--- |
| 877 |
P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Glue); |
0 |
877 |
P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Glue); |
0 |
| 878 |
*Glue = P.getValue(2); |
0 |
878 |
*Glue = P.getValue(2); |
0 |
| 879 |
} |
--- |
879 |
} |
--- |
| 880 |
|
--- |
880 |
|
--- |
| 881 |
Chain = P.getValue(1); |
0 |
881 |
Chain = P.getValue(1); |
0 |
| 882 |
Parts[i] = P; |
0 |
882 |
Parts[i] = P; |
0 |
| 883 |
|
--- |
883 |
|
--- |
| 884 |
// If the source register was virtual and if we know something about it, |
--- |
884 |
// If the source register was virtual and if we know something about it, |
--- |
| 885 |
// add an assert node. |
--- |
885 |
// add an assert node. |
--- |
| 886 |
if (!Register::isVirtualRegister(Regs[Part + i]) || |
0 |
886 |
if (!Register::isVirtualRegister(Regs[Part + i]) || |
0 |
| 887 |
!RegisterVT.isInteger()) |
0 |
887 |
!RegisterVT.isInteger()) |
0 |
| 888 |
continue; |
0 |
888 |
continue; |
0 |
| 889 |
|
--- |
889 |
|
--- |
| 890 |
const FunctionLoweringInfo::LiveOutInfo *LOI = |
--- |
890 |
const FunctionLoweringInfo::LiveOutInfo *LOI = |
--- |
| 891 |
FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); |
0 |
891 |
FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); |
0 |
| 892 |
if (!LOI) |
0 |
892 |
if (!LOI) |
0 |
| 893 |
continue; |
0 |
893 |
continue; |
0 |
| 894 |
|
--- |
894 |
|
--- |
| 895 |
unsigned RegSize = RegisterVT.getScalarSizeInBits(); |
0 |
895 |
unsigned RegSize = RegisterVT.getScalarSizeInBits(); |
0 |
| 896 |
unsigned NumSignBits = LOI->NumSignBits; |
0 |
896 |
unsigned NumSignBits = LOI->NumSignBits; |
0 |
| 897 |
unsigned NumZeroBits = LOI->Known.countMinLeadingZeros(); |
0 |
897 |
unsigned NumZeroBits = LOI->Known.countMinLeadingZeros(); |
0 |
| 898 |
|
--- |
898 |
|
--- |
| 899 |
if (NumZeroBits == RegSize) { |
0 |
899 |
if (NumZeroBits == RegSize) { |
0 |
| 900 |
// The current value is a zero. |
--- |
900 |
// The current value is a zero. |
--- |
| 901 |
// Explicitly express that as it would be easier for |
--- |
901 |
// Explicitly express that as it would be easier for |
--- |
| 902 |
// optimizations to kick in. |
--- |
902 |
// optimizations to kick in. |
--- |
| 903 |
Parts[i] = DAG.getConstant(0, dl, RegisterVT); |
0 |
903 |
Parts[i] = DAG.getConstant(0, dl, RegisterVT); |
0 |
| 904 |
continue; |
0 |
904 |
continue; |
0 |
| 905 |
} |
--- |
905 |
} |
--- |
| 906 |
|
--- |
906 |
|
--- |
| 907 |
// FIXME: We capture more information than the dag can represent. For |
--- |
907 |
// FIXME: We capture more information than the dag can represent. For |
--- |
| 908 |
// now, just use the tightest assertzext/assertsext possible. |
--- |
908 |
// now, just use the tightest assertzext/assertsext possible. |
--- |
| 909 |
bool isSExt; |
--- |
909 |
bool isSExt; |
--- |
| 910 |
EVT FromVT(MVT::Other); |
0 |
910 |
EVT FromVT(MVT::Other); |
0 |
| 911 |
if (NumZeroBits) { |
0 |
911 |
if (NumZeroBits) { |
0 |
| 912 |
FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits); |
0 |
912 |
FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits); |
0 |
| 913 |
isSExt = false; |
0 |
913 |
isSExt = false; |
0 |
| 914 |
} else if (NumSignBits > 1) { |
0 |
914 |
} else if (NumSignBits > 1) { |
0 |
| 915 |
FromVT = |
--- |
915 |
FromVT = |
--- |
| 916 |
EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1); |
0 |
916 |
EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1); |
0 |
| 917 |
isSExt = true; |
0 |
917 |
isSExt = true; |
0 |
| 918 |
} else { |
--- |
918 |
} else { |
--- |
| 919 |
continue; |
0 |
919 |
continue; |
0 |
| 920 |
} |
--- |
920 |
} |
--- |
| 921 |
// Add an assertion node. |
--- |
921 |
// Add an assertion node. |
--- |
| 922 |
assert(FromVT != MVT::Other); |
0 |
922 |
assert(FromVT != MVT::Other); |
0 |
| 923 |
Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, |
0 |
923 |
Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, |
0 |
| 924 |
RegisterVT, P, DAG.getValueType(FromVT)); |
--- |
924 |
RegisterVT, P, DAG.getValueType(FromVT)); |
--- |
| 925 |
} |
--- |
925 |
} |
--- |
| 926 |
|
--- |
926 |
|
--- |
| 927 |
Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs, |
0 |
927 |
Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs, |
0 |
| 928 |
RegisterVT, ValueVT, V, CallConv); |
--- |
928 |
RegisterVT, ValueVT, V, CallConv); |
--- |
| 929 |
Part += NumRegs; |
0 |
929 |
Part += NumRegs; |
0 |
| 930 |
Parts.clear(); |
0 |
930 |
Parts.clear(); |
0 |
| 931 |
} |
--- |
931 |
} |
--- |
| 932 |
|
--- |
932 |
|
--- |
| 933 |
return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); |
0 |
933 |
return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); |
0 |
| 934 |
} |
0 |
934 |
} |
0 |
| 935 |
|
--- |
935 |
|
--- |
| 936 |
void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, |
0 |
936 |
void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, |
0 |
| 937 |
const SDLoc &dl, SDValue &Chain, SDValue *Glue, |
--- |
937 |
const SDLoc &dl, SDValue &Chain, SDValue *Glue, |
--- |
| 938 |
const Value *V, |
--- |
938 |
const Value *V, |
--- |
| 939 |
ISD::NodeType PreferredExtendType) const { |
--- |
939 |
ISD::NodeType PreferredExtendType) const { |
--- |
| 940 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
940 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 941 |
ISD::NodeType ExtendKind = PreferredExtendType; |
0 |
941 |
ISD::NodeType ExtendKind = PreferredExtendType; |
0 |
| 942 |
|
--- |
942 |
|
--- |
| 943 |
// Get the list of the values's legal parts. |
--- |
943 |
// Get the list of the values's legal parts. |
--- |
| 944 |
unsigned NumRegs = Regs.size(); |
0 |
944 |
unsigned NumRegs = Regs.size(); |
0 |
| 945 |
SmallVector Parts(NumRegs); |
0 |
945 |
SmallVector Parts(NumRegs); |
0 |
| 946 |
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { |
0 |
946 |
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { |
0 |
| 947 |
unsigned NumParts = RegCount[Value]; |
0 |
947 |
unsigned NumParts = RegCount[Value]; |
0 |
| 948 |
|
--- |
948 |
|
--- |
| 949 |
MVT RegisterVT = isABIMangled() |
0 |
949 |
MVT RegisterVT = isABIMangled() |
0 |
| 950 |
? TLI.getRegisterTypeForCallingConv( |
0 |
950 |
? TLI.getRegisterTypeForCallingConv( |
0 |
| 951 |
*DAG.getContext(), *CallConv, RegVTs[Value]) |
0 |
951 |
*DAG.getContext(), *CallConv, RegVTs[Value]) |
0 |
| 952 |
: RegVTs[Value]; |
0 |
952 |
: RegVTs[Value]; |
0 |
| 953 |
|
--- |
953 |
|
--- |
| 954 |
if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) |
0 |
954 |
if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) |
0 |
| 955 |
ExtendKind = ISD::ZERO_EXTEND; |
0 |
955 |
ExtendKind = ISD::ZERO_EXTEND; |
0 |
| 956 |
|
--- |
956 |
|
--- |
| 957 |
getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], |
0 |
957 |
getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], |
0 |
| 958 |
NumParts, RegisterVT, V, CallConv, ExtendKind); |
--- |
958 |
NumParts, RegisterVT, V, CallConv, ExtendKind); |
--- |
| 959 |
Part += NumParts; |
0 |
959 |
Part += NumParts; |
0 |
| 960 |
} |
--- |
960 |
} |
--- |
| 961 |
|
--- |
961 |
|
--- |
| 962 |
// Copy the parts into the registers. |
--- |
962 |
// Copy the parts into the registers. |
--- |
| 963 |
SmallVector Chains(NumRegs); |
0 |
963 |
SmallVector Chains(NumRegs); |
0 |
| 964 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
964 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
| 965 |
SDValue Part; |
0 |
965 |
SDValue Part; |
0 |
| 966 |
if (!Glue) { |
0 |
966 |
if (!Glue) { |
0 |
| 967 |
Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); |
0 |
967 |
Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); |
0 |
| 968 |
} else { |
--- |
968 |
} else { |
--- |
| 969 |
Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Glue); |
0 |
969 |
Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Glue); |
0 |
| 970 |
*Glue = Part.getValue(1); |
0 |
970 |
*Glue = Part.getValue(1); |
0 |
| 971 |
} |
--- |
971 |
} |
--- |
| 972 |
|
--- |
972 |
|
--- |
| 973 |
Chains[i] = Part.getValue(0); |
0 |
973 |
Chains[i] = Part.getValue(0); |
0 |
| 974 |
} |
--- |
974 |
} |
--- |
| 975 |
|
--- |
975 |
|
--- |
| 976 |
if (NumRegs == 1 || Glue) |
0 |
976 |
if (NumRegs == 1 || Glue) |
0 |
| 977 |
// If NumRegs > 1 && Glue is used then the use of the last CopyToReg is |
--- |
977 |
// If NumRegs > 1 && Glue is used then the use of the last CopyToReg is |
--- |
| 978 |
// flagged to it. That is the CopyToReg nodes and the user are considered |
--- |
978 |
// flagged to it. That is the CopyToReg nodes and the user are considered |
--- |
| 979 |
// a single scheduling unit. If we create a TokenFactor and return it as |
--- |
979 |
// a single scheduling unit. If we create a TokenFactor and return it as |
--- |
| 980 |
// chain, then the TokenFactor is both a predecessor (operand) of the |
--- |
980 |
// chain, then the TokenFactor is both a predecessor (operand) of the |
--- |
| 981 |
// user as well as a successor (the TF operands are flagged to the user). |
--- |
981 |
// user as well as a successor (the TF operands are flagged to the user). |
--- |
| 982 |
// c1, f1 = CopyToReg |
--- |
982 |
// c1, f1 = CopyToReg |
--- |
| 983 |
// c2, f2 = CopyToReg |
--- |
983 |
// c2, f2 = CopyToReg |
--- |
| 984 |
// c3 = TokenFactor c1, c2 |
--- |
984 |
// c3 = TokenFactor c1, c2 |
--- |
| 985 |
// ... |
--- |
985 |
// ... |
--- |
| 986 |
// = op c3, ..., f2 |
--- |
986 |
// = op c3, ..., f2 |
--- |
| 987 |
Chain = Chains[NumRegs-1]; |
0 |
987 |
Chain = Chains[NumRegs-1]; |
0 |
| 988 |
else |
--- |
988 |
else |
--- |
| 989 |
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); |
0 |
989 |
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); |
0 |
| 990 |
} |
0 |
990 |
} |
0 |
| 991 |
|
--- |
991 |
|
--- |
| 992 |
void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, |
0 |
992 |
void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, |
0 |
| 993 |
unsigned MatchingIdx, const SDLoc &dl, |
--- |
993 |
unsigned MatchingIdx, const SDLoc &dl, |
--- |
| 994 |
SelectionDAG &DAG, |
--- |
994 |
SelectionDAG &DAG, |
--- |
| 995 |
std::vector &Ops) const { |
--- |
995 |
std::vector &Ops) const { |
--- |
| 996 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
996 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 997 |
|
--- |
997 |
|
--- |
| 998 |
unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); |
0 |
998 |
unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); |
0 |
| 999 |
if (HasMatching) |
0 |
999 |
if (HasMatching) |
0 |
| 1000 |
Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); |
0 |
1000 |
Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); |
0 |
| 1001 |
else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) { |
0 |
1001 |
else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) { |
0 |
| 1002 |
// Put the register class of the virtual registers in the flag word. That |
--- |
1002 |
// Put the register class of the virtual registers in the flag word. That |
--- |
| 1003 |
// way, later passes can recompute register class constraints for inline |
--- |
1003 |
// way, later passes can recompute register class constraints for inline |
--- |
| 1004 |
// assembly as well as normal instructions. |
--- |
1004 |
// assembly as well as normal instructions. |
--- |
| 1005 |
// Don't do this for tied operands that can use the regclass information |
--- |
1005 |
// Don't do this for tied operands that can use the regclass information |
--- |
| 1006 |
// from the def. |
--- |
1006 |
// from the def. |
--- |
| 1007 |
const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); |
0 |
1007 |
const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); |
0 |
| 1008 |
const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); |
0 |
1008 |
const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); |
0 |
| 1009 |
Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); |
0 |
1009 |
Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); |
0 |
| 1010 |
} |
--- |
1010 |
} |
--- |
| 1011 |
|
--- |
1011 |
|
--- |
| 1012 |
SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32); |
0 |
1012 |
SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32); |
0 |
| 1013 |
Ops.push_back(Res); |
0 |
1013 |
Ops.push_back(Res); |
0 |
| 1014 |
|
--- |
1014 |
|
--- |
| 1015 |
if (Code == InlineAsm::Kind_Clobber) { |
0 |
1015 |
if (Code == InlineAsm::Kind_Clobber) { |
0 |
| 1016 |
// Clobbers should always have a 1:1 mapping with registers, and may |
--- |
1016 |
// Clobbers should always have a 1:1 mapping with registers, and may |
--- |
| 1017 |
// reference registers that have illegal (e.g. vector) types. Hence, we |
--- |
1017 |
// reference registers that have illegal (e.g. vector) types. Hence, we |
--- |
| 1018 |
// shouldn't try to apply any sort of splitting logic to them. |
--- |
1018 |
// shouldn't try to apply any sort of splitting logic to them. |
--- |
| 1019 |
assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && |
0 |
1019 |
assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && |
0 |
| 1020 |
"No 1:1 mapping from clobbers to regs?"); |
--- |
1020 |
"No 1:1 mapping from clobbers to regs?"); |
--- |
| 1021 |
Register SP = TLI.getStackPointerRegisterToSaveRestore(); |
0 |
1021 |
Register SP = TLI.getStackPointerRegisterToSaveRestore(); |
0 |
| 1022 |
(void)SP; |
--- |
1022 |
(void)SP; |
--- |
| 1023 |
for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) { |
0 |
1023 |
for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) { |
0 |
| 1024 |
Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); |
0 |
1024 |
Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); |
0 |
| 1025 |
assert( |
0 |
1025 |
assert( |
0 |
| 1026 |
(Regs[I] != SP || |
--- |
1026 |
(Regs[I] != SP || |
--- |
| 1027 |
DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && |
--- |
1027 |
DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && |
--- |
| 1028 |
"If we clobbered the stack pointer, MFI should know about it."); |
--- |
1028 |
"If we clobbered the stack pointer, MFI should know about it."); |
--- |
| 1029 |
} |
--- |
1029 |
} |
--- |
| 1030 |
return; |
0 |
1030 |
return; |
0 |
| 1031 |
} |
--- |
1031 |
} |
--- |
| 1032 |
|
--- |
1032 |
|
--- |
| 1033 |
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { |
0 |
1033 |
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { |
0 |
| 1034 |
MVT RegisterVT = RegVTs[Value]; |
0 |
1034 |
MVT RegisterVT = RegVTs[Value]; |
0 |
| 1035 |
unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value], |
0 |
1035 |
unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value], |
0 |
| 1036 |
RegisterVT); |
--- |
1036 |
RegisterVT); |
--- |
| 1037 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
1037 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
| 1038 |
assert(Reg < Regs.size() && "Mismatch in # registers expected"); |
0 |
1038 |
assert(Reg < Regs.size() && "Mismatch in # registers expected"); |
0 |
| 1039 |
unsigned TheReg = Regs[Reg++]; |
0 |
1039 |
unsigned TheReg = Regs[Reg++]; |
0 |
| 1040 |
Ops.push_back(DAG.getRegister(TheReg, RegisterVT)); |
0 |
1040 |
Ops.push_back(DAG.getRegister(TheReg, RegisterVT)); |
0 |
| 1041 |
} |
--- |
1041 |
} |
--- |
| 1042 |
} |
--- |
1042 |
} |
--- |
| 1043 |
} |
--- |
1043 |
} |
--- |
| 1044 |
|
--- |
1044 |
|
--- |
| 1045 |
SmallVector, 4> |
--- |
1045 |
SmallVector, 4> |
--- |
| 1046 |
RegsForValue::getRegsAndSizes() const { |
0 |
1046 |
RegsForValue::getRegsAndSizes() const { |
0 |
| 1047 |
SmallVector, 4> OutVec; |
0 |
1047 |
SmallVector, 4> OutVec; |
0 |
| 1048 |
unsigned I = 0; |
0 |
1048 |
unsigned I = 0; |
0 |
| 1049 |
for (auto CountAndVT : zip_first(RegCount, RegVTs)) { |
0 |
1049 |
for (auto CountAndVT : zip_first(RegCount, RegVTs)) { |
0 |
| 1050 |
unsigned RegCount = std::get<0>(CountAndVT); |
0 |
1050 |
unsigned RegCount = std::get<0>(CountAndVT); |
0 |
| 1051 |
MVT RegisterVT = std::get<1>(CountAndVT); |
0 |
1051 |
MVT RegisterVT = std::get<1>(CountAndVT); |
0 |
| 1052 |
TypeSize RegisterSize = RegisterVT.getSizeInBits(); |
0 |
1052 |
TypeSize RegisterSize = RegisterVT.getSizeInBits(); |
0 |
| 1053 |
for (unsigned E = I + RegCount; I != E; ++I) |
0 |
1053 |
for (unsigned E = I + RegCount; I != E; ++I) |
0 |
| 1054 |
OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); |
0 |
1054 |
OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); |
0 |
| 1055 |
} |
--- |
1055 |
} |
--- |
| 1056 |
return OutVec; |
0 |
1056 |
return OutVec; |
0 |
| 1057 |
} |
--- |
1057 |
} |
--- |
| 1058 |
|
--- |
1058 |
|
--- |
| 1059 |
void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa, |
1 |
1059 |
void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa, |
1 |
| 1060 |
AssumptionCache *ac, |
--- |
1060 |
AssumptionCache *ac, |
--- |
| 1061 |
const TargetLibraryInfo *li) { |
--- |
1061 |
const TargetLibraryInfo *li) { |
--- |
| 1062 |
AA = aa; |
1 |
1062 |
AA = aa; |
1 |
| 1063 |
AC = ac; |
1 |
1063 |
AC = ac; |
1 |
| 1064 |
GFI = gfi; |
1 |
1064 |
GFI = gfi; |
1 |
| 1065 |
LibInfo = li; |
1 |
1065 |
LibInfo = li; |
1 |
| 1066 |
Context = DAG.getContext(); |
1 |
1066 |
Context = DAG.getContext(); |
1 |
| 1067 |
LPadToCallSiteMap.clear(); |
1 |
1067 |
LPadToCallSiteMap.clear(); |
1 |
| 1068 |
SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout()); |
1 |
1068 |
SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout()); |
1 |
| 1069 |
AssignmentTrackingEnabled = isAssignmentTrackingEnabled( |
1 |
1069 |
AssignmentTrackingEnabled = isAssignmentTrackingEnabled( |
1 |
| 1070 |
*DAG.getMachineFunction().getFunction().getParent()); |
1 |
1070 |
*DAG.getMachineFunction().getFunction().getParent()); |
1 |
| 1071 |
} |
1 |
1071 |
} |
1 |
| 1072 |
|
--- |
1072 |
|
--- |
| 1073 |
void SelectionDAGBuilder::clear() { |
4 |
1073 |
void SelectionDAGBuilder::clear() { |
4 |
| 1074 |
NodeMap.clear(); |
4 |
1074 |
NodeMap.clear(); |
4 |
| 1075 |
UnusedArgNodeMap.clear(); |
4 |
1075 |
UnusedArgNodeMap.clear(); |
4 |
| 1076 |
PendingLoads.clear(); |
4 |
1076 |
PendingLoads.clear(); |
4 |
| 1077 |
PendingExports.clear(); |
4 |
1077 |
PendingExports.clear(); |
4 |
| 1078 |
PendingConstrainedFP.clear(); |
4 |
1078 |
PendingConstrainedFP.clear(); |
4 |
| 1079 |
PendingConstrainedFPStrict.clear(); |
4 |
1079 |
PendingConstrainedFPStrict.clear(); |
4 |
| 1080 |
CurInst = nullptr; |
4 |
1080 |
CurInst = nullptr; |
4 |
| 1081 |
HasTailCall = false; |
4 |
1081 |
HasTailCall = false; |
4 |
| 1082 |
SDNodeOrder = LowestSDNodeOrder; |
4 |
1082 |
SDNodeOrder = LowestSDNodeOrder; |
4 |
| 1083 |
StatepointLowering.clear(); |
4 |
1083 |
StatepointLowering.clear(); |
4 |
| 1084 |
} |
4 |
1084 |
} |
4 |
| 1085 |
|
--- |
1085 |
|
--- |
| 1086 |
void SelectionDAGBuilder::clearDanglingDebugInfo() { |
5 |
1086 |
void SelectionDAGBuilder::clearDanglingDebugInfo() { |
5 |
| 1087 |
DanglingDebugInfoMap.clear(); |
5 |
1087 |
DanglingDebugInfoMap.clear(); |
5 |
| 1088 |
} |
5 |
1088 |
} |
5 |
| 1089 |
|
--- |
1089 |
|
--- |
| 1090 |
// Update DAG root to include dependencies on Pending chains. |
--- |
1090 |
// Update DAG root to include dependencies on Pending chains. |
--- |
| 1091 |
SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl &Pending) { |
12 |
1091 |
SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl &Pending) { |
12 |
| 1092 |
SDValue Root = DAG.getRoot(); |
12 |
1092 |
SDValue Root = DAG.getRoot(); |
12 |
| 1093 |
|
--- |
1093 |
|
--- |
| 1094 |
if (Pending.empty()) |
12 |
1094 |
if (Pending.empty()) |
12 |
| 1095 |
return Root; |
10 |
1095 |
return Root; |
10 |
| 1096 |
|
--- |
1096 |
|
--- |
| 1097 |
// Add current root to PendingChains, unless we already indirectly |
--- |
1097 |
// Add current root to PendingChains, unless we already indirectly |
--- |
| 1098 |
// depend on it. |
--- |
1098 |
// depend on it. |
--- |
| 1099 |
if (Root.getOpcode() != ISD::EntryToken) { |
2 |
1099 |
if (Root.getOpcode() != ISD::EntryToken) { |
2 |
| 1100 |
unsigned i = 0, e = Pending.size(); |
0 |
1100 |
unsigned i = 0, e = Pending.size(); |
0 |
| 1101 |
for (; i != e; ++i) { |
0 |
1101 |
for (; i != e; ++i) { |
0 |
| 1102 |
assert(Pending[i].getNode()->getNumOperands() > 1); |
0 |
1102 |
assert(Pending[i].getNode()->getNumOperands() > 1); |
0 |
| 1103 |
if (Pending[i].getNode()->getOperand(0) == Root) |
0 |
1103 |
if (Pending[i].getNode()->getOperand(0) == Root) |
0 |
| 1104 |
break; // Don't add the root if we already indirectly depend on it. |
0 |
1104 |
break; // Don't add the root if we already indirectly depend on it. |
0 |
| 1105 |
} |
--- |
1105 |
} |
--- |
| 1106 |
|
--- |
1106 |
|
--- |
| 1107 |
if (i == e) |
0 |
1107 |
if (i == e) |
0 |
| 1108 |
Pending.push_back(Root); |
0 |
1108 |
Pending.push_back(Root); |
0 |
| 1109 |
} |
--- |
1109 |
} |
--- |
| 1110 |
|
--- |
1110 |
|
--- |
| 1111 |
if (Pending.size() == 1) |
2 |
1111 |
if (Pending.size() == 1) |
2 |
| 1112 |
Root = Pending[0]; |
2 |
1112 |
Root = Pending[0]; |
2 |
| 1113 |
else |
--- |
1113 |
else |
--- |
| 1114 |
Root = DAG.getTokenFactor(getCurSDLoc(), Pending); |
0 |
1114 |
Root = DAG.getTokenFactor(getCurSDLoc(), Pending); |
0 |
| 1115 |
|
--- |
1115 |
|
--- |
| 1116 |
DAG.setRoot(Root); |
2 |
1116 |
DAG.setRoot(Root); |
2 |
| 1117 |
Pending.clear(); |
2 |
1117 |
Pending.clear(); |
2 |
| 1118 |
return Root; |
2 |
1118 |
return Root; |
2 |
| 1119 |
} |
--- |
1119 |
} |
--- |
| 1120 |
|
--- |
1120 |
|
--- |
| 1121 |
SDValue SelectionDAGBuilder::getMemoryRoot() { |
4 |
1121 |
SDValue SelectionDAGBuilder::getMemoryRoot() { |
4 |
| 1122 |
return updateRoot(PendingLoads); |
4 |
1122 |
return updateRoot(PendingLoads); |
4 |
| 1123 |
} |
--- |
1123 |
} |
--- |
| 1124 |
|
--- |
1124 |
|
--- |
| 1125 |
SDValue SelectionDAGBuilder::getRoot() { |
0 |
1125 |
SDValue SelectionDAGBuilder::getRoot() { |
0 |
| 1126 |
// Chain up all pending constrained intrinsics together with all |
--- |
1126 |
// Chain up all pending constrained intrinsics together with all |
--- |
| 1127 |
// pending loads, by simply appending them to PendingLoads and |
--- |
1127 |
// pending loads, by simply appending them to PendingLoads and |
--- |
| 1128 |
// then calling getMemoryRoot(). |
--- |
1128 |
// then calling getMemoryRoot(). |
--- |
| 1129 |
PendingLoads.reserve(PendingLoads.size() + |
0 |
1129 |
PendingLoads.reserve(PendingLoads.size() + |
0 |
| 1130 |
PendingConstrainedFP.size() + |
0 |
1130 |
PendingConstrainedFP.size() + |
0 |
| 1131 |
PendingConstrainedFPStrict.size()); |
0 |
1131 |
PendingConstrainedFPStrict.size()); |
0 |
| 1132 |
PendingLoads.append(PendingConstrainedFP.begin(), |
0 |
1132 |
PendingLoads.append(PendingConstrainedFP.begin(), |
0 |
| 1133 |
PendingConstrainedFP.end()); |
--- |
1133 |
PendingConstrainedFP.end()); |
--- |
| 1134 |
PendingLoads.append(PendingConstrainedFPStrict.begin(), |
0 |
1134 |
PendingLoads.append(PendingConstrainedFPStrict.begin(), |
0 |
| 1135 |
PendingConstrainedFPStrict.end()); |
--- |
1135 |
PendingConstrainedFPStrict.end()); |
--- |
| 1136 |
PendingConstrainedFP.clear(); |
0 |
1136 |
PendingConstrainedFP.clear(); |
0 |
| 1137 |
PendingConstrainedFPStrict.clear(); |
0 |
1137 |
PendingConstrainedFPStrict.clear(); |
0 |
| 1138 |
return getMemoryRoot(); |
0 |
1138 |
return getMemoryRoot(); |
0 |
| 1139 |
} |
--- |
1139 |
} |
--- |
| 1140 |
|
--- |
1140 |
|
--- |
| 1141 |
SDValue SelectionDAGBuilder::getControlRoot() { |
8 |
1141 |
SDValue SelectionDAGBuilder::getControlRoot() { |
8 |
| 1142 |
// We need to emit pending fpexcept.strict constrained intrinsics, |
--- |
1142 |
// We need to emit pending fpexcept.strict constrained intrinsics, |
--- |
| 1143 |
// so append them to the PendingExports list. |
--- |
1143 |
// so append them to the PendingExports list. |
--- |
| 1144 |
PendingExports.append(PendingConstrainedFPStrict.begin(), |
8 |
1144 |
PendingExports.append(PendingConstrainedFPStrict.begin(), |
8 |
| 1145 |
PendingConstrainedFPStrict.end()); |
--- |
1145 |
PendingConstrainedFPStrict.end()); |
--- |
| 1146 |
PendingConstrainedFPStrict.clear(); |
8 |
1146 |
PendingConstrainedFPStrict.clear(); |
8 |
| 1147 |
return updateRoot(PendingExports); |
8 |
1147 |
return updateRoot(PendingExports); |
8 |
| 1148 |
} |
--- |
1148 |
} |
--- |
| 1149 |
|
--- |
1149 |
|
--- |
| 1150 |
void SelectionDAGBuilder::visit(const Instruction &I) { |
20 |
1150 |
void SelectionDAGBuilder::visit(const Instruction &I) { |
17 |
| 1151 |
// Set up outgoing PHI node register values before emitting the terminator. |
--- |
1151 |
// Set up outgoing PHI node register values before emitting the terminator. |
--- |
| 1152 |
if (I.isTerminator()) { |
20 |
1152 |
if (I.isTerminator()) { |
17 |
| 1153 |
HandlePHINodesInSuccessorBlocks(I.getParent()); |
4 |
1153 |
HandlePHINodesInSuccessorBlocks(I.getParent()); |
4 |
| 1154 |
} |
--- |
1154 |
} |
--- |
| 1155 |
|
--- |
1155 |
|
--- |
| 1156 |
// Add SDDbgValue nodes for any var locs here. Do so before updating |
--- |
1156 |
// Add SDDbgValue nodes for any var locs here. Do so before updating |
--- |
| 1157 |
// SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}. |
--- |
1157 |
// SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}. |
--- |
| 1158 |
if (FunctionVarLocs const *FnVarLocs = DAG.getFunctionVarLocs()) { |
20 |
1158 |
if (FunctionVarLocs const *FnVarLocs = DAG.getFunctionVarLocs()) { |
17 |
| 1159 |
// Add SDDbgValue nodes for any var locs here. Do so before updating |
--- |
1159 |
// Add SDDbgValue nodes for any var locs here. Do so before updating |
--- |
| 1160 |
// SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}. |
--- |
1160 |
// SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}. |
--- |
| 1161 |
for (auto It = FnVarLocs->locs_begin(&I), End = FnVarLocs->locs_end(&I); |
0 |
1161 |
for (auto It = FnVarLocs->locs_begin(&I), End = FnVarLocs->locs_end(&I); |
0 |
| 1162 |
It != End; ++It) { |
0 |
1162 |
It != End; ++It) { |
0 |
| 1163 |
auto *Var = FnVarLocs->getDILocalVariable(It->VariableID); |
0 |
1163 |
auto *Var = FnVarLocs->getDILocalVariable(It->VariableID); |
0 |
| 1164 |
dropDanglingDebugInfo(Var, It->Expr); |
0 |
1164 |
dropDanglingDebugInfo(Var, It->Expr); |
0 |
| 1165 |
if (It->Values.isKillLocation(It->Expr)) { |
0 |
1165 |
if (It->Values.isKillLocation(It->Expr)) { |
0 |
| 1166 |
handleKillDebugValue(Var, It->Expr, It->DL, SDNodeOrder); |
0 |
1166 |
handleKillDebugValue(Var, It->Expr, It->DL, SDNodeOrder); |
0 |
| 1167 |
continue; |
0 |
1167 |
continue; |
0 |
| 1168 |
} |
--- |
1168 |
} |
--- |
| 1169 |
SmallVector Values(It->Values.location_ops()); |
0 |
1169 |
SmallVector Values(It->Values.location_ops()); |
0 |
| 1170 |
if (!handleDebugValue(Values, Var, It->Expr, It->DL, SDNodeOrder, |
0 |
1170 |
if (!handleDebugValue(Values, Var, It->Expr, It->DL, SDNodeOrder, |
0 |
| 1171 |
It->Values.hasArgList())) |
0 |
1171 |
It->Values.hasArgList())) |
0 |
| 1172 |
addDanglingDebugInfo(It, SDNodeOrder); |
0 |
1172 |
addDanglingDebugInfo(It, SDNodeOrder); |
0 |
| 1173 |
} |
0 |
1173 |
} |
0 |
| 1174 |
} |
--- |
1174 |
} |
--- |
| 1175 |
|
--- |
1175 |
|
--- |
| 1176 |
// Increase the SDNodeOrder if dealing with a non-debug instruction. |
--- |
1176 |
// Increase the SDNodeOrder if dealing with a non-debug instruction. |
--- |
| 1177 |
if (!isa(I)) |
20 |
1177 |
if (!isa(I)) |
17 |
| 1178 |
++SDNodeOrder; |
17 |
1178 |
++SDNodeOrder; |
17 |
| 1179 |
|
--- |
1179 |
|
--- |
| 1180 |
CurInst = &I; |
20 |
1180 |
CurInst = &I; |
17 |
| 1181 |
|
--- |
1181 |
|
--- |
| 1182 |
// Set inserted listener only if required. |
--- |
1182 |
// Set inserted listener only if required. |
--- |
| 1183 |
bool NodeInserted = false; |
20 |
1183 |
bool NodeInserted = false; |
17 |
| 1184 |
std::unique_ptr InsertedListener; |
20 |
1184 |
std::unique_ptr InsertedListener; |
17 |
| 1185 |
MDNode *PCSectionsMD = I.getMetadata(LLVMContext::MD_pcsections); |
20 |
1185 |
MDNode *PCSectionsMD = I.getMetadata(LLVMContext::MD_pcsections); |
17 |
| 1186 |
if (PCSectionsMD) { |
20 |
1186 |
if (PCSectionsMD) { |
17 |
| 1187 |
InsertedListener = std::make_unique( |
0 |
1187 |
InsertedListener = std::make_unique( |
0 |
| 1188 |
DAG, [&](SDNode *) { NodeInserted = true; }); |
0 |
1188 |
DAG, [&](SDNode *) { NodeInserted = true; }); |
0 |
| 1189 |
} |
--- |
1189 |
} |
--- |
| 1190 |
|
--- |
1190 |
|
--- |
| 1191 |
visit(I.getOpcode(), I); |
20 |
1191 |
visit(I.getOpcode(), I); |
17 |
| 1192 |
|
--- |
1192 |
|
--- |
| 1193 |
if (!I.isTerminator() && !HasTailCall && |
36 |
1193 |
if (!I.isTerminator() && !HasTailCall && |
30 |
| 1194 |
!isa(I)) // statepoints handle their exports internally |
16 |
1194 |
!isa(I)) // statepoints handle their exports internally |
13 |
| 1195 |
CopyToExportRegsIfNeeded(&I); |
16 |
1195 |
CopyToExportRegsIfNeeded(&I); |
13 |
| 1196 |
|
--- |
1196 |
|
--- |
| 1197 |
// Handle metadata. |
--- |
1197 |
// Handle metadata. |
--- |
| 1198 |
if (PCSectionsMD) { |
20 |
1198 |
if (PCSectionsMD) { |
17 |
| 1199 |
auto It = NodeMap.find(&I); |
0 |
1199 |
auto It = NodeMap.find(&I); |
0 |
| 1200 |
if (It != NodeMap.end()) { |
0 |
1200 |
if (It != NodeMap.end()) { |
0 |
| 1201 |
DAG.addPCSections(It->second.getNode(), PCSectionsMD); |
0 |
1201 |
DAG.addPCSections(It->second.getNode(), PCSectionsMD); |
0 |
| 1202 |
} else if (NodeInserted) { |
0 |
1202 |
} else if (NodeInserted) { |
0 |
| 1203 |
// This should not happen; if it does, don't let it go unnoticed so we can |
--- |
1203 |
// This should not happen; if it does, don't let it go unnoticed so we can |
--- |
| 1204 |
// fix it. Relevant visit*() function is probably missing a setValue(). |
--- |
1204 |
// fix it. Relevant visit*() function is probably missing a setValue(). |
--- |
| 1205 |
errs() << "warning: loosing !pcsections metadata [" |
0 |
1205 |
errs() << "warning: loosing !pcsections metadata [" |
0 |
| 1206 |
<< I.getModule()->getName() << "]\n"; |
0 |
1206 |
<< I.getModule()->getName() << "]\n"; |
0 |
| 1207 |
LLVM_DEBUG(I.dump()); |
0 |
1207 |
LLVM_DEBUG(I.dump()); |
0 |
| 1208 |
assert(false); |
0 |
1208 |
assert(false); |
0 |
| 1209 |
} |
--- |
1209 |
} |
--- |
| 1210 |
} |
--- |
1210 |
} |
--- |
| 1211 |
|
--- |
1211 |
|
--- |
| 1212 |
CurInst = nullptr; |
20 |
1212 |
CurInst = nullptr; |
17 |
| 1213 |
} |
20 |
1213 |
} |
17 |
| 1214 |
|
--- |
1214 |
|
--- |
| 1215 |
void SelectionDAGBuilder::visitPHI(const PHINode &) { |
0 |
1215 |
void SelectionDAGBuilder::visitPHI(const PHINode &) { |
0 |
| 1216 |
llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); |
0 |
1216 |
llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); |
0 |
| 1217 |
} |
--- |
1217 |
} |
--- |
| 1218 |
|
--- |
1218 |
|
--- |
| 1219 |
void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { |
20 |
1219 |
void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { |
17 |
| 1220 |
// Note: this doesn't use InstVisitor, because it has to work with |
--- |
1220 |
// Note: this doesn't use InstVisitor, because it has to work with |
--- |
| 1221 |
// ConstantExpr's in addition to instructions. |
--- |
1221 |
// ConstantExpr's in addition to instructions. |
--- |
| 1222 |
switch (Opcode) { |
20 |
1222 |
switch (Opcode) { |
17 |
| 1223 |
default: llvm_unreachable("Unknown instruction type encountered!"); |
0 |
1223 |
default: llvm_unreachable("Unknown instruction type encountered!"); |
0 |
| 1224 |
// Build the switch statement using the Instruction.def file. |
--- |
1224 |
// Build the switch statement using the Instruction.def file. |
--- |
| 1225 |
#define HANDLE_INST(NUM, OPCODE, CLASS) \ |
--- |
1225 |
#define HANDLE_INST(NUM, OPCODE, CLASS) \ |
--- |
| 1226 |
case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; |
--- |
1226 |
case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; |
--- |
| 1227 |
#include "llvm/IR/Instruction.def" |
--- |
1227 |
#include "llvm/IR/Instruction.def" |
--- |
| 1228 |
} |
--- |
1228 |
} |
--- |
| 1229 |
} |
20 |
1229 |
} |
17 |
| 1230 |
|
--- |
1230 |
|
--- |
| 1231 |
static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG, |
0 |
1231 |
static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG, |
0 |
| 1232 |
DILocalVariable *Variable, |
--- |
1232 |
DILocalVariable *Variable, |
--- |
| 1233 |
DebugLoc DL, unsigned Order, |
--- |
1233 |
DebugLoc DL, unsigned Order, |
--- |
| 1234 |
RawLocationWrapper Values, |
--- |
1234 |
RawLocationWrapper Values, |
--- |
| 1235 |
DIExpression *Expression) { |
--- |
1235 |
DIExpression *Expression) { |
--- |
| 1236 |
if (!Values.hasArgList()) |
0 |
1236 |
if (!Values.hasArgList()) |
0 |
| 1237 |
return false; |
0 |
1237 |
return false; |
0 |
| 1238 |
// For variadic dbg_values we will now insert an undef. |
--- |
1238 |
// For variadic dbg_values we will now insert an undef. |
--- |
| 1239 |
// FIXME: We can potentially recover these! |
--- |
1239 |
// FIXME: We can potentially recover these! |
--- |
| 1240 |
SmallVector Locs; |
0 |
1240 |
SmallVector Locs; |
0 |
| 1241 |
for (const Value *V : Values.location_ops()) { |
0 |
1241 |
for (const Value *V : Values.location_ops()) { |
0 |
| 1242 |
auto *Undef = UndefValue::get(V->getType()); |
0 |
1242 |
auto *Undef = UndefValue::get(V->getType()); |
0 |
| 1243 |
Locs.push_back(SDDbgOperand::fromConst(Undef)); |
0 |
1243 |
Locs.push_back(SDDbgOperand::fromConst(Undef)); |
0 |
| 1244 |
} |
--- |
1244 |
} |
--- |
| 1245 |
SDDbgValue *SDV = DAG.getDbgValueList(Variable, Expression, Locs, {}, |
0 |
1245 |
SDDbgValue *SDV = DAG.getDbgValueList(Variable, Expression, Locs, {}, |
0 |
| 1246 |
/*IsIndirect=*/false, DL, Order, |
--- |
1246 |
/*IsIndirect=*/false, DL, Order, |
--- |
| 1247 |
/*IsVariadic=*/true); |
--- |
1247 |
/*IsVariadic=*/true); |
--- |
| 1248 |
DAG.AddDbgValue(SDV, /*isParameter=*/false); |
0 |
1248 |
DAG.AddDbgValue(SDV, /*isParameter=*/false); |
0 |
| 1249 |
return true; |
0 |
1249 |
return true; |
0 |
| 1250 |
} |
0 |
1250 |
} |
0 |
| 1251 |
|
--- |
1251 |
|
--- |
| 1252 |
void SelectionDAGBuilder::addDanglingDebugInfo(const VarLocInfo *VarLoc, |
0 |
1252 |
void SelectionDAGBuilder::addDanglingDebugInfo(const VarLocInfo *VarLoc, |
0 |
| 1253 |
unsigned Order) { |
--- |
1253 |
unsigned Order) { |
--- |
| 1254 |
if (!handleDanglingVariadicDebugInfo( |
0 |
1254 |
if (!handleDanglingVariadicDebugInfo( |
0 |
| 1255 |
DAG, |
--- |
1255 |
DAG, |
--- |
| 1256 |
const_cast(DAG.getFunctionVarLocs() |
0 |
1256 |
const_cast(DAG.getFunctionVarLocs() |
0 |
| 1257 |
->getVariable(VarLoc->VariableID) |
0 |
1257 |
->getVariable(VarLoc->VariableID) |
0 |
| 1258 |
.getVariable()), |
0 |
1258 |
.getVariable()), |
0 |
| 1259 |
VarLoc->DL, Order, VarLoc->Values, VarLoc->Expr)) { |
0 |
1259 |
VarLoc->DL, Order, VarLoc->Values, VarLoc->Expr)) { |
0 |
| 1260 |
DanglingDebugInfoMap[VarLoc->Values.getVariableLocationOp(0)].emplace_back( |
0 |
1260 |
DanglingDebugInfoMap[VarLoc->Values.getVariableLocationOp(0)].emplace_back( |
0 |
| 1261 |
VarLoc, Order); |
--- |
1261 |
VarLoc, Order); |
--- |
| 1262 |
} |
--- |
1262 |
} |
--- |
| 1263 |
} |
0 |
1263 |
} |
0 |
| 1264 |
|
--- |
1264 |
|
--- |
| 1265 |
void SelectionDAGBuilder::addDanglingDebugInfo(const DbgValueInst *DI, |
0 |
1265 |
void SelectionDAGBuilder::addDanglingDebugInfo(const DbgValueInst *DI, |
0 |
| 1266 |
unsigned Order) { |
--- |
1266 |
unsigned Order) { |
--- |
| 1267 |
// We treat variadic dbg_values differently at this stage. |
--- |
1267 |
// We treat variadic dbg_values differently at this stage. |
--- |
| 1268 |
if (!handleDanglingVariadicDebugInfo( |
0 |
1268 |
if (!handleDanglingVariadicDebugInfo( |
0 |
| 1269 |
DAG, DI->getVariable(), DI->getDebugLoc(), Order, |
--- |
1269 |
DAG, DI->getVariable(), DI->getDebugLoc(), Order, |
--- |
| 1270 |
DI->getWrappedLocation(), DI->getExpression())) { |
--- |
1270 |
DI->getWrappedLocation(), DI->getExpression())) { |
--- |
| 1271 |
// TODO: Dangling debug info will eventually either be resolved or produce |
--- |
1271 |
// TODO: Dangling debug info will eventually either be resolved or produce |
--- |
| 1272 |
// an Undef DBG_VALUE. However in the resolution case, a gap may appear |
--- |
1272 |
// an Undef DBG_VALUE. However in the resolution case, a gap may appear |
--- |
| 1273 |
// between the original dbg.value location and its resolved DBG_VALUE, |
--- |
1273 |
// between the original dbg.value location and its resolved DBG_VALUE, |
--- |
| 1274 |
// which we should ideally fill with an extra Undef DBG_VALUE. |
--- |
1274 |
// which we should ideally fill with an extra Undef DBG_VALUE. |
--- |
| 1275 |
assert(DI->getNumVariableLocationOps() == 1 && |
0 |
1275 |
assert(DI->getNumVariableLocationOps() == 1 && |
0 |
| 1276 |
"DbgValueInst without an ArgList should have a single location " |
--- |
1276 |
"DbgValueInst without an ArgList should have a single location " |
--- |
| 1277 |
"operand."); |
--- |
1277 |
"operand."); |
--- |
| 1278 |
DanglingDebugInfoMap[DI->getValue(0)].emplace_back(DI, Order); |
0 |
1278 |
DanglingDebugInfoMap[DI->getValue(0)].emplace_back(DI, Order); |
0 |
| 1279 |
} |
--- |
1279 |
} |
--- |
| 1280 |
} |
0 |
1280 |
} |
0 |
| 1281 |
|
--- |
1281 |
|
--- |
| 1282 |
void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable, |
0 |
1282 |
void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable, |
0 |
| 1283 |
const DIExpression *Expr) { |
--- |
1283 |
const DIExpression *Expr) { |
--- |
| 1284 |
auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) { |
0 |
1284 |
auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) { |
0 |
| 1285 |
DIVariable *DanglingVariable = DDI.getVariable(DAG.getFunctionVarLocs()); |
0 |
1285 |
DIVariable *DanglingVariable = DDI.getVariable(DAG.getFunctionVarLocs()); |
0 |
| 1286 |
DIExpression *DanglingExpr = DDI.getExpression(); |
0 |
1286 |
DIExpression *DanglingExpr = DDI.getExpression(); |
0 |
| 1287 |
if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) { |
0 |
1287 |
if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) { |
0 |
| 1288 |
LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << printDDI(DDI) |
0 |
1288 |
LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << printDDI(DDI) |
0 |
| 1289 |
<< "\n"); |
--- |
1289 |
<< "\n"); |
--- |
| 1290 |
return true; |
0 |
1290 |
return true; |
0 |
| 1291 |
} |
--- |
1291 |
} |
--- |
| 1292 |
return false; |
0 |
1292 |
return false; |
0 |
| 1293 |
}; |
0 |
1293 |
}; |
0 |
| 1294 |
|
--- |
1294 |
|
--- |
| 1295 |
for (auto &DDIMI : DanglingDebugInfoMap) { |
0 |
1295 |
for (auto &DDIMI : DanglingDebugInfoMap) { |
0 |
| 1296 |
DanglingDebugInfoVector &DDIV = DDIMI.second; |
0 |
1296 |
DanglingDebugInfoVector &DDIV = DDIMI.second; |
0 |
| 1297 |
|
--- |
1297 |
|
--- |
| 1298 |
// If debug info is to be dropped, run it through final checks to see |
--- |
1298 |
// If debug info is to be dropped, run it through final checks to see |
--- |
| 1299 |
// whether it can be salvaged. |
--- |
1299 |
// whether it can be salvaged. |
--- |
| 1300 |
for (auto &DDI : DDIV) |
0 |
1300 |
for (auto &DDI : DDIV) |
0 |
| 1301 |
if (isMatchingDbgValue(DDI)) |
0 |
1301 |
if (isMatchingDbgValue(DDI)) |
0 |
| 1302 |
salvageUnresolvedDbgValue(DDI); |
0 |
1302 |
salvageUnresolvedDbgValue(DDI); |
0 |
| 1303 |
|
--- |
1303 |
|
--- |
| 1304 |
erase_if(DDIV, isMatchingDbgValue); |
0 |
1304 |
erase_if(DDIV, isMatchingDbgValue); |
0 |
| 1305 |
} |
--- |
1305 |
} |
--- |
| 1306 |
} |
0 |
1306 |
} |
0 |
| 1307 |
|
--- |
1307 |
|
--- |
| 1308 |
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, |
--- |
1308 |
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, |
--- |
| 1309 |
// generate the debug data structures now that we've seen its definition. |
--- |
1309 |
// generate the debug data structures now that we've seen its definition. |
--- |
| 1310 |
void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, |
7 |
1310 |
void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, |
7 |
| 1311 |
SDValue Val) { |
--- |
1311 |
SDValue Val) { |
--- |
| 1312 |
auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V); |
7 |
1312 |
auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V); |
7 |
| 1313 |
if (DanglingDbgInfoIt == DanglingDebugInfoMap.end()) |
7 |
1313 |
if (DanglingDbgInfoIt == DanglingDebugInfoMap.end()) |
7 |
| 1314 |
return; |
7 |
1314 |
return; |
7 |
| 1315 |
|
--- |
1315 |
|
--- |
| 1316 |
DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second; |
0 |
1316 |
DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second; |
0 |
| 1317 |
for (auto &DDI : DDIV) { |
0 |
1317 |
for (auto &DDI : DDIV) { |
0 |
| 1318 |
DebugLoc DL = DDI.getDebugLoc(); |
0 |
1318 |
DebugLoc DL = DDI.getDebugLoc(); |
0 |
| 1319 |
unsigned ValSDNodeOrder = Val.getNode()->getIROrder(); |
0 |
1319 |
unsigned ValSDNodeOrder = Val.getNode()->getIROrder(); |
0 |
| 1320 |
unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); |
0 |
1320 |
unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); |
0 |
| 1321 |
DILocalVariable *Variable = DDI.getVariable(DAG.getFunctionVarLocs()); |
0 |
1321 |
DILocalVariable *Variable = DDI.getVariable(DAG.getFunctionVarLocs()); |
0 |
| 1322 |
DIExpression *Expr = DDI.getExpression(); |
0 |
1322 |
DIExpression *Expr = DDI.getExpression(); |
0 |
| 1323 |
assert(Variable->isValidLocationForIntrinsic(DL) && |
0 |
1323 |
assert(Variable->isValidLocationForIntrinsic(DL) && |
0 |
| 1324 |
"Expected inlined-at fields to agree"); |
--- |
1324 |
"Expected inlined-at fields to agree"); |
--- |
| 1325 |
SDDbgValue *SDV; |
--- |
1325 |
SDDbgValue *SDV; |
--- |
| 1326 |
if (Val.getNode()) { |
0 |
1326 |
if (Val.getNode()) { |
0 |
| 1327 |
// FIXME: I doubt that it is correct to resolve a dangling DbgValue as a |
--- |
1327 |
// FIXME: I doubt that it is correct to resolve a dangling DbgValue as a |
--- |
| 1328 |
// FuncArgumentDbgValue (it would be hoisted to the function entry, and if |
--- |
1328 |
// FuncArgumentDbgValue (it would be hoisted to the function entry, and if |
--- |
| 1329 |
// we couldn't resolve it directly when examining the DbgValue intrinsic |
--- |
1329 |
// we couldn't resolve it directly when examining the DbgValue intrinsic |
--- |
| 1330 |
// in the first place we should not be more successful here). Unless we |
--- |
1330 |
// in the first place we should not be more successful here). Unless we |
--- |
| 1331 |
// have some test case that prove this to be correct we should avoid |
--- |
1331 |
// have some test case that prove this to be correct we should avoid |
--- |
| 1332 |
// calling EmitFuncArgumentDbgValue here. |
--- |
1332 |
// calling EmitFuncArgumentDbgValue here. |
--- |
| 1333 |
if (!EmitFuncArgumentDbgValue(V, Variable, Expr, DL, |
0 |
1333 |
if (!EmitFuncArgumentDbgValue(V, Variable, Expr, DL, |
0 |
| 1334 |
FuncArgumentDbgValueKind::Value, Val)) { |
--- |
1334 |
FuncArgumentDbgValueKind::Value, Val)) { |
--- |
| 1335 |
LLVM_DEBUG(dbgs() << "Resolve dangling debug info for " << printDDI(DDI) |
0 |
1335 |
LLVM_DEBUG(dbgs() << "Resolve dangling debug info for " << printDDI(DDI) |
0 |
| 1336 |
<< "\n"); |
--- |
1336 |
<< "\n"); |
--- |
| 1337 |
LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump()); |
0 |
1337 |
LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump()); |
0 |
| 1338 |
// Increase the SDNodeOrder for the DbgValue here to make sure it is |
--- |
1338 |
// Increase the SDNodeOrder for the DbgValue here to make sure it is |
--- |
| 1339 |
// inserted after the definition of Val when emitting the instructions |
--- |
1339 |
// inserted after the definition of Val when emitting the instructions |
--- |
| 1340 |
// after ISel. An alternative could be to teach |
--- |
1340 |
// after ISel. An alternative could be to teach |
--- |
| 1341 |
// ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly. |
--- |
1341 |
// ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly. |
--- |
| 1342 |
LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() |
0 |
1342 |
LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() |
0 |
| 1343 |
<< "changing SDNodeOrder from " << DbgSDNodeOrder << " to " |
--- |
1343 |
<< "changing SDNodeOrder from " << DbgSDNodeOrder << " to " |
--- |
| 1344 |
<< ValSDNodeOrder << "\n"); |
--- |
1344 |
<< ValSDNodeOrder << "\n"); |
--- |
| 1345 |
SDV = getDbgValue(Val, Variable, Expr, DL, |
0 |
1345 |
SDV = getDbgValue(Val, Variable, Expr, DL, |
0 |
| 1346 |
std::max(DbgSDNodeOrder, ValSDNodeOrder)); |
0 |
1346 |
std::max(DbgSDNodeOrder, ValSDNodeOrder)); |
0 |
| 1347 |
DAG.AddDbgValue(SDV, false); |
0 |
1347 |
DAG.AddDbgValue(SDV, false); |
0 |
| 1348 |
} else |
--- |
1348 |
} else |
--- |
| 1349 |
LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " |
0 |
1349 |
LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " |
0 |
| 1350 |
<< printDDI(DDI) << " in EmitFuncArgumentDbgValue\n"); |
--- |
1350 |
<< printDDI(DDI) << " in EmitFuncArgumentDbgValue\n"); |
--- |
| 1351 |
} else { |
--- |
1351 |
} else { |
--- |
| 1352 |
LLVM_DEBUG(dbgs() << "Dropping debug info for " << printDDI(DDI) << "\n"); |
0 |
1352 |
LLVM_DEBUG(dbgs() << "Dropping debug info for " << printDDI(DDI) << "\n"); |
0 |
| 1353 |
auto Undef = UndefValue::get(V->getType()); |
0 |
1353 |
auto Undef = UndefValue::get(V->getType()); |
0 |
| 1354 |
auto SDV = |
--- |
1354 |
auto SDV = |
--- |
| 1355 |
DAG.getConstantDbgValue(Variable, Expr, Undef, DL, DbgSDNodeOrder); |
0 |
1355 |
DAG.getConstantDbgValue(Variable, Expr, Undef, DL, DbgSDNodeOrder); |
0 |
| 1356 |
DAG.AddDbgValue(SDV, false); |
0 |
1356 |
DAG.AddDbgValue(SDV, false); |
0 |
| 1357 |
} |
--- |
1357 |
} |
--- |
| 1358 |
} |
0 |
1358 |
} |
0 |
| 1359 |
DDIV.clear(); |
0 |
1359 |
DDIV.clear(); |
0 |
| 1360 |
} |
--- |
1360 |
} |
--- |
| 1361 |
|
--- |
1361 |
|
--- |
| 1362 |
void SelectionDAGBuilder::salvageUnresolvedDbgValue(DanglingDebugInfo &DDI) { |
0 |
1362 |
void SelectionDAGBuilder::salvageUnresolvedDbgValue(DanglingDebugInfo &DDI) { |
0 |
| 1363 |
// TODO: For the variadic implementation, instead of only checking the fail |
--- |
1363 |
// TODO: For the variadic implementation, instead of only checking the fail |
--- |
| 1364 |
// state of `handleDebugValue`, we need know specifically which values were |
--- |
1364 |
// state of `handleDebugValue`, we need know specifically which values were |
--- |
| 1365 |
// invalid, so that we attempt to salvage only those values when processing |
--- |
1365 |
// invalid, so that we attempt to salvage only those values when processing |
--- |
| 1366 |
// a DIArgList. |
--- |
1366 |
// a DIArgList. |
--- |
| 1367 |
Value *V = DDI.getVariableLocationOp(0); |
0 |
1367 |
Value *V = DDI.getVariableLocationOp(0); |
0 |
| 1368 |
Value *OrigV = V; |
0 |
1368 |
Value *OrigV = V; |
0 |
| 1369 |
DILocalVariable *Var = DDI.getVariable(DAG.getFunctionVarLocs()); |
0 |
1369 |
DILocalVariable *Var = DDI.getVariable(DAG.getFunctionVarLocs()); |
0 |
| 1370 |
DIExpression *Expr = DDI.getExpression(); |
0 |
1370 |
DIExpression *Expr = DDI.getExpression(); |
0 |
| 1371 |
DebugLoc DL = DDI.getDebugLoc(); |
0 |
1371 |
DebugLoc DL = DDI.getDebugLoc(); |
0 |
| 1372 |
unsigned SDOrder = DDI.getSDNodeOrder(); |
0 |
1372 |
unsigned SDOrder = DDI.getSDNodeOrder(); |
0 |
| 1373 |
|
--- |
1373 |
|
--- |
| 1374 |
// Currently we consider only dbg.value intrinsics -- we tell the salvager |
--- |
1374 |
// Currently we consider only dbg.value intrinsics -- we tell the salvager |
--- |
| 1375 |
// that DW_OP_stack_value is desired. |
--- |
1375 |
// that DW_OP_stack_value is desired. |
--- |
| 1376 |
bool StackValue = true; |
0 |
1376 |
bool StackValue = true; |
0 |
| 1377 |
|
--- |
1377 |
|
--- |
| 1378 |
// Can this Value can be encoded without any further work? |
--- |
1378 |
// Can this Value can be encoded without any further work? |
--- |
| 1379 |
if (handleDebugValue(V, Var, Expr, DL, SDOrder, /*IsVariadic=*/false)) |
0 |
1379 |
if (handleDebugValue(V, Var, Expr, DL, SDOrder, /*IsVariadic=*/false)) |
0 |
| 1380 |
return; |
0 |
1380 |
return; |
0 |
| 1381 |
|
--- |
1381 |
|
--- |
| 1382 |
// Attempt to salvage back through as many instructions as possible. Bail if |
--- |
1382 |
// Attempt to salvage back through as many instructions as possible. Bail if |
--- |
| 1383 |
// a non-instruction is seen, such as a constant expression or global |
--- |
1383 |
// a non-instruction is seen, such as a constant expression or global |
--- |
| 1384 |
// variable. FIXME: Further work could recover those too. |
--- |
1384 |
// variable. FIXME: Further work could recover those too. |
--- |
| 1385 |
while (isa(V)) { |
0 |
1385 |
while (isa(V)) { |
0 |
| 1386 |
Instruction &VAsInst = *cast(V); |
0 |
1386 |
Instruction &VAsInst = *cast(V); |
0 |
| 1387 |
// Temporary "0", awaiting real implementation. |
--- |
1387 |
// Temporary "0", awaiting real implementation. |
--- |
| 1388 |
SmallVector Ops; |
0 |
1388 |
SmallVector Ops; |
0 |
| 1389 |
SmallVector AdditionalValues; |
0 |
1389 |
SmallVector AdditionalValues; |
0 |
| 1390 |
V = salvageDebugInfoImpl(VAsInst, Expr->getNumLocationOperands(), Ops, |
0 |
1390 |
V = salvageDebugInfoImpl(VAsInst, Expr->getNumLocationOperands(), Ops, |
0 |
| 1391 |
AdditionalValues); |
--- |
1391 |
AdditionalValues); |
--- |
| 1392 |
// If we cannot salvage any further, and haven't yet found a suitable debug |
--- |
1392 |
// If we cannot salvage any further, and haven't yet found a suitable debug |
--- |
| 1393 |
// expression, bail out. |
--- |
1393 |
// expression, bail out. |
--- |
| 1394 |
if (!V) |
0 |
1394 |
if (!V) |
0 |
| 1395 |
break; |
0 |
1395 |
break; |
0 |
| 1396 |
|
--- |
1396 |
|
--- |
| 1397 |
// TODO: If AdditionalValues isn't empty, then the salvage can only be |
--- |
1397 |
// TODO: If AdditionalValues isn't empty, then the salvage can only be |
--- |
| 1398 |
// represented with a DBG_VALUE_LIST, so we give up. When we have support |
--- |
1398 |
// represented with a DBG_VALUE_LIST, so we give up. When we have support |
--- |
| 1399 |
// here for variadic dbg_values, remove that condition. |
--- |
1399 |
// here for variadic dbg_values, remove that condition. |
--- |
| 1400 |
if (!AdditionalValues.empty()) |
0 |
1400 |
if (!AdditionalValues.empty()) |
0 |
| 1401 |
break; |
0 |
1401 |
break; |
0 |
| 1402 |
|
--- |
1402 |
|
--- |
| 1403 |
// New value and expr now represent this debuginfo. |
--- |
1403 |
// New value and expr now represent this debuginfo. |
--- |
| 1404 |
Expr = DIExpression::appendOpsToArg(Expr, Ops, 0, StackValue); |
0 |
1404 |
Expr = DIExpression::appendOpsToArg(Expr, Ops, 0, StackValue); |
0 |
| 1405 |
|
--- |
1405 |
|
--- |
| 1406 |
// Some kind of simplification occurred: check whether the operand of the |
--- |
1406 |
// Some kind of simplification occurred: check whether the operand of the |
--- |
| 1407 |
// salvaged debug expression can be encoded in this DAG. |
--- |
1407 |
// salvaged debug expression can be encoded in this DAG. |
--- |
| 1408 |
if (handleDebugValue(V, Var, Expr, DL, SDOrder, /*IsVariadic=*/false)) { |
0 |
1408 |
if (handleDebugValue(V, Var, Expr, DL, SDOrder, /*IsVariadic=*/false)) { |
0 |
| 1409 |
LLVM_DEBUG( |
0 |
1409 |
LLVM_DEBUG( |
0 |
| 1410 |
dbgs() << "Salvaged debug location info for:\n " << *Var << "\n" |
--- |
1410 |
dbgs() << "Salvaged debug location info for:\n " << *Var << "\n" |
--- |
| 1411 |
<< *OrigV << "\nBy stripping back to:\n " << *V << "\n"); |
--- |
1411 |
<< *OrigV << "\nBy stripping back to:\n " << *V << "\n"); |
--- |
| 1412 |
return; |
0 |
1412 |
return; |
0 |
| 1413 |
} |
--- |
1413 |
} |
--- |
| 1414 |
} |
0 |
1414 |
} |
0 |
| 1415 |
|
--- |
1415 |
|
--- |
| 1416 |
// This was the final opportunity to salvage this debug information, and it |
--- |
1416 |
// This was the final opportunity to salvage this debug information, and it |
--- |
| 1417 |
// couldn't be done. Place an undef DBG_VALUE at this location to terminate |
--- |
1417 |
// couldn't be done. Place an undef DBG_VALUE at this location to terminate |
--- |
| 1418 |
// any earlier variable location. |
--- |
1418 |
// any earlier variable location. |
--- |
| 1419 |
assert(OrigV && "V shouldn't be null"); |
0 |
1419 |
assert(OrigV && "V shouldn't be null"); |
0 |
| 1420 |
auto *Undef = UndefValue::get(OrigV->getType()); |
0 |
1420 |
auto *Undef = UndefValue::get(OrigV->getType()); |
0 |
| 1421 |
auto *SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder); |
0 |
1421 |
auto *SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder); |
0 |
| 1422 |
DAG.AddDbgValue(SDV, false); |
0 |
1422 |
DAG.AddDbgValue(SDV, false); |
0 |
| 1423 |
LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << printDDI(DDI) |
0 |
1423 |
LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << printDDI(DDI) |
0 |
| 1424 |
<< "\n"); |
--- |
1424 |
<< "\n"); |
--- |
| 1425 |
} |
0 |
1425 |
} |
0 |
| 1426 |
|
--- |
1426 |
|
--- |
| 1427 |
void SelectionDAGBuilder::handleKillDebugValue(DILocalVariable *Var, |
0 |
1427 |
void SelectionDAGBuilder::handleKillDebugValue(DILocalVariable *Var, |
0 |
| 1428 |
DIExpression *Expr, |
--- |
1428 |
DIExpression *Expr, |
--- |
| 1429 |
DebugLoc DbgLoc, |
--- |
1429 |
DebugLoc DbgLoc, |
--- |
| 1430 |
unsigned Order) { |
--- |
1430 |
unsigned Order) { |
--- |
| 1431 |
Value *Poison = PoisonValue::get(Type::getInt1Ty(*Context)); |
0 |
1431 |
Value *Poison = PoisonValue::get(Type::getInt1Ty(*Context)); |
0 |
| 1432 |
DIExpression *NewExpr = |
--- |
1432 |
DIExpression *NewExpr = |
--- |
| 1433 |
const_cast(DIExpression::convertToUndefExpression(Expr)); |
0 |
1433 |
const_cast(DIExpression::convertToUndefExpression(Expr)); |
0 |
| 1434 |
handleDebugValue(Poison, Var, NewExpr, DbgLoc, Order, |
0 |
1434 |
handleDebugValue(Poison, Var, NewExpr, DbgLoc, Order, |
0 |
| 1435 |
/*IsVariadic*/ false); |
--- |
1435 |
/*IsVariadic*/ false); |
--- |
| 1436 |
} |
0 |
1436 |
} |
0 |
| 1437 |
|
--- |
1437 |
|
--- |
| 1438 |
bool SelectionDAGBuilder::handleDebugValue(ArrayRef Values, |
0 |
1438 |
bool SelectionDAGBuilder::handleDebugValue(ArrayRef Values, |
0 |
| 1439 |
DILocalVariable *Var, |
--- |
1439 |
DILocalVariable *Var, |
--- |
| 1440 |
DIExpression *Expr, DebugLoc DbgLoc, |
--- |
1440 |
DIExpression *Expr, DebugLoc DbgLoc, |
--- |
| 1441 |
unsigned Order, bool IsVariadic) { |
--- |
1441 |
unsigned Order, bool IsVariadic) { |
--- |
| 1442 |
if (Values.empty()) |
0 |
1442 |
if (Values.empty()) |
0 |
| 1443 |
return true; |
0 |
1443 |
return true; |
0 |
| 1444 |
SmallVector LocationOps; |
0 |
1444 |
SmallVector LocationOps; |
0 |
| 1445 |
SmallVector Dependencies; |
0 |
1445 |
SmallVector Dependencies; |
0 |
| 1446 |
for (const Value *V : Values) { |
0 |
1446 |
for (const Value *V : Values) { |
0 |
| 1447 |
// Constant value. |
--- |
1447 |
// Constant value. |
--- |
| 1448 |
if (isa(V) || isa(V) || isa(V) || |
0 |
1448 |
if (isa(V) || isa(V) || isa(V) || |
0 |
| 1449 |
isa(V)) { |
0 |
1449 |
isa(V)) { |
0 |
| 1450 |
LocationOps.emplace_back(SDDbgOperand::fromConst(V)); |
0 |
1450 |
LocationOps.emplace_back(SDDbgOperand::fromConst(V)); |
0 |
| 1451 |
continue; |
0 |
1451 |
continue; |
0 |
| 1452 |
} |
--- |
1452 |
} |
--- |
| 1453 |
|
--- |
1453 |
|
--- |
| 1454 |
// Look through IntToPtr constants. |
--- |
1454 |
// Look through IntToPtr constants. |
--- |
| 1455 |
if (auto *CE = dyn_cast(V)) |
0 |
1455 |
if (auto *CE = dyn_cast(V)) |
0 |
| 1456 |
if (CE->getOpcode() == Instruction::IntToPtr) { |
0 |
1456 |
if (CE->getOpcode() == Instruction::IntToPtr) { |
0 |
| 1457 |
LocationOps.emplace_back(SDDbgOperand::fromConst(CE->getOperand(0))); |
0 |
1457 |
LocationOps.emplace_back(SDDbgOperand::fromConst(CE->getOperand(0))); |
0 |
| 1458 |
continue; |
0 |
1458 |
continue; |
0 |
| 1459 |
} |
--- |
1459 |
} |
--- |
| 1460 |
|
--- |
1460 |
|
--- |
| 1461 |
// If the Value is a frame index, we can create a FrameIndex debug value |
--- |
1461 |
// If the Value is a frame index, we can create a FrameIndex debug value |
--- |
| 1462 |
// without relying on the DAG at all. |
--- |
1462 |
// without relying on the DAG at all. |
--- |
| 1463 |
if (const AllocaInst *AI = dyn_cast(V)) { |
0 |
1463 |
if (const AllocaInst *AI = dyn_cast(V)) { |
0 |
| 1464 |
auto SI = FuncInfo.StaticAllocaMap.find(AI); |
0 |
1464 |
auto SI = FuncInfo.StaticAllocaMap.find(AI); |
0 |
| 1465 |
if (SI != FuncInfo.StaticAllocaMap.end()) { |
0 |
1465 |
if (SI != FuncInfo.StaticAllocaMap.end()) { |
0 |
| 1466 |
LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(SI->second)); |
0 |
1466 |
LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(SI->second)); |
0 |
| 1467 |
continue; |
0 |
1467 |
continue; |
0 |
| 1468 |
} |
--- |
1468 |
} |
--- |
| 1469 |
} |
--- |
1469 |
} |
--- |
| 1470 |
|
--- |
1470 |
|
--- |
| 1471 |
// Do not use getValue() in here; we don't want to generate code at |
--- |
1471 |
// Do not use getValue() in here; we don't want to generate code at |
--- |
| 1472 |
// this point if it hasn't been done yet. |
--- |
1472 |
// this point if it hasn't been done yet. |
--- |
| 1473 |
SDValue N = NodeMap[V]; |
0 |
1473 |
SDValue N = NodeMap[V]; |
0 |
| 1474 |
if (!N.getNode() && isa(V)) // Check unused arguments map. |
0 |
1474 |
if (!N.getNode() && isa(V)) // Check unused arguments map. |
0 |
| 1475 |
N = UnusedArgNodeMap[V]; |
0 |
1475 |
N = UnusedArgNodeMap[V]; |
0 |
| 1476 |
if (N.getNode()) { |
0 |
1476 |
if (N.getNode()) { |
0 |
| 1477 |
// Only emit func arg dbg value for non-variadic dbg.values for now. |
--- |
1477 |
// Only emit func arg dbg value for non-variadic dbg.values for now. |
--- |
| 1478 |
if (!IsVariadic && |
0 |
1478 |
if (!IsVariadic && |
0 |
| 1479 |
EmitFuncArgumentDbgValue(V, Var, Expr, DbgLoc, |
0 |
1479 |
EmitFuncArgumentDbgValue(V, Var, Expr, DbgLoc, |
0 |
| 1480 |
FuncArgumentDbgValueKind::Value, N)) |
--- |
1480 |
FuncArgumentDbgValueKind::Value, N)) |
--- |
| 1481 |
return true; |
0 |
1481 |
return true; |
0 |
| 1482 |
if (auto *FISDN = dyn_cast(N.getNode())) { |
0 |
1482 |
if (auto *FISDN = dyn_cast(N.getNode())) { |
0 |
| 1483 |
// Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can |
--- |
1483 |
// Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can |
--- |
| 1484 |
// describe stack slot locations. |
--- |
1484 |
// describe stack slot locations. |
--- |
| 1485 |
// |
--- |
1485 |
// |
--- |
| 1486 |
// Consider "int x = 0; int *px = &x;". There are two kinds of |
--- |
1486 |
// Consider "int x = 0; int *px = &x;". There are two kinds of |
--- |
| 1487 |
// interesting debug values here after optimization: |
--- |
1487 |
// interesting debug values here after optimization: |
--- |
| 1488 |
// |
--- |
1488 |
// |
--- |
| 1489 |
// dbg.value(i32* %px, !"int *px", !DIExpression()), and |
--- |
1489 |
// dbg.value(i32* %px, !"int *px", !DIExpression()), and |
--- |
| 1490 |
// dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref)) |
--- |
1490 |
// dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref)) |
--- |
| 1491 |
// |
--- |
1491 |
// |
--- |
| 1492 |
// Both describe the direct values of their associated variables. |
--- |
1492 |
// Both describe the direct values of their associated variables. |
--- |
| 1493 |
Dependencies.push_back(N.getNode()); |
0 |
1493 |
Dependencies.push_back(N.getNode()); |
0 |
| 1494 |
LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(FISDN->getIndex())); |
0 |
1494 |
LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(FISDN->getIndex())); |
0 |
| 1495 |
continue; |
0 |
1495 |
continue; |
0 |
| 1496 |
} |
--- |
1496 |
} |
--- |
| 1497 |
LocationOps.emplace_back( |
0 |
1497 |
LocationOps.emplace_back( |
0 |
| 1498 |
SDDbgOperand::fromNode(N.getNode(), N.getResNo())); |
0 |
1498 |
SDDbgOperand::fromNode(N.getNode(), N.getResNo())); |
0 |
| 1499 |
continue; |
0 |
1499 |
continue; |
0 |
| 1500 |
} |
0 |
1500 |
} |
0 |
| 1501 |
|
--- |
1501 |
|
--- |
| 1502 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
1502 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 1503 |
// Special rules apply for the first dbg.values of parameter variables in a |
--- |
1503 |
// Special rules apply for the first dbg.values of parameter variables in a |
--- |
| 1504 |
// function. Identify them by the fact they reference Argument Values, that |
--- |
1504 |
// function. Identify them by the fact they reference Argument Values, that |
--- |
| 1505 |
// they're parameters, and they are parameters of the current function. We |
--- |
1505 |
// they're parameters, and they are parameters of the current function. We |
--- |
| 1506 |
// need to let them dangle until they get an SDNode. |
--- |
1506 |
// need to let them dangle until they get an SDNode. |
--- |
| 1507 |
bool IsParamOfFunc = |
--- |
1507 |
bool IsParamOfFunc = |
--- |
| 1508 |
isa(V) && Var->isParameter() && !DbgLoc.getInlinedAt(); |
0 |
1508 |
isa(V) && Var->isParameter() && !DbgLoc.getInlinedAt(); |
0 |
| 1509 |
if (IsParamOfFunc) |
0 |
1509 |
if (IsParamOfFunc) |
0 |
| 1510 |
return false; |
0 |
1510 |
return false; |
0 |
| 1511 |
|
--- |
1511 |
|
--- |
| 1512 |
// The value is not used in this block yet (or it would have an SDNode). |
--- |
1512 |
// The value is not used in this block yet (or it would have an SDNode). |
--- |
| 1513 |
// We still want the value to appear for the user if possible -- if it has |
--- |
1513 |
// We still want the value to appear for the user if possible -- if it has |
--- |
| 1514 |
// an associated VReg, we can refer to that instead. |
--- |
1514 |
// an associated VReg, we can refer to that instead. |
--- |
| 1515 |
auto VMI = FuncInfo.ValueMap.find(V); |
0 |
1515 |
auto VMI = FuncInfo.ValueMap.find(V); |
0 |
| 1516 |
if (VMI != FuncInfo.ValueMap.end()) { |
0 |
1516 |
if (VMI != FuncInfo.ValueMap.end()) { |
0 |
| 1517 |
unsigned Reg = VMI->second; |
0 |
1517 |
unsigned Reg = VMI->second; |
0 |
| 1518 |
// If this is a PHI node, it may be split up into several MI PHI nodes |
--- |
1518 |
// If this is a PHI node, it may be split up into several MI PHI nodes |
--- |
| 1519 |
// (in FunctionLoweringInfo::set). |
--- |
1519 |
// (in FunctionLoweringInfo::set). |
--- |
| 1520 |
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, |
0 |
1520 |
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, |
0 |
| 1521 |
V->getType(), std::nullopt); |
0 |
1521 |
V->getType(), std::nullopt); |
0 |
| 1522 |
if (RFV.occupiesMultipleRegs()) { |
0 |
1522 |
if (RFV.occupiesMultipleRegs()) { |
0 |
| 1523 |
// FIXME: We could potentially support variadic dbg_values here. |
--- |
1523 |
// FIXME: We could potentially support variadic dbg_values here. |
--- |
| 1524 |
if (IsVariadic) |
0 |
1524 |
if (IsVariadic) |
0 |
| 1525 |
return false; |
0 |
1525 |
return false; |
0 |
| 1526 |
unsigned Offset = 0; |
0 |
1526 |
unsigned Offset = 0; |
0 |
| 1527 |
unsigned BitsToDescribe = 0; |
0 |
1527 |
unsigned BitsToDescribe = 0; |
0 |
| 1528 |
if (auto VarSize = Var->getSizeInBits()) |
0 |
1528 |
if (auto VarSize = Var->getSizeInBits()) |
0 |
| 1529 |
BitsToDescribe = *VarSize; |
0 |
1529 |
BitsToDescribe = *VarSize; |
0 |
| 1530 |
if (auto Fragment = Expr->getFragmentInfo()) |
0 |
1530 |
if (auto Fragment = Expr->getFragmentInfo()) |
0 |
| 1531 |
BitsToDescribe = Fragment->SizeInBits; |
0 |
1531 |
BitsToDescribe = Fragment->SizeInBits; |
0 |
| 1532 |
for (const auto &RegAndSize : RFV.getRegsAndSizes()) { |
0 |
1532 |
for (const auto &RegAndSize : RFV.getRegsAndSizes()) { |
0 |
| 1533 |
// Bail out if all bits are described already. |
--- |
1533 |
// Bail out if all bits are described already. |
--- |
| 1534 |
if (Offset >= BitsToDescribe) |
0 |
1534 |
if (Offset >= BitsToDescribe) |
0 |
| 1535 |
break; |
0 |
1535 |
break; |
0 |
| 1536 |
// TODO: handle scalable vectors. |
--- |
1536 |
// TODO: handle scalable vectors. |
--- |
| 1537 |
unsigned RegisterSize = RegAndSize.second; |
0 |
1537 |
unsigned RegisterSize = RegAndSize.second; |
0 |
| 1538 |
unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe) |
0 |
1538 |
unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe) |
0 |
| 1539 |
? BitsToDescribe - Offset |
0 |
1539 |
? BitsToDescribe - Offset |
0 |
| 1540 |
: RegisterSize; |
--- |
1540 |
: RegisterSize; |
--- |
| 1541 |
auto FragmentExpr = DIExpression::createFragmentExpression( |
0 |
1541 |
auto FragmentExpr = DIExpression::createFragmentExpression( |
0 |
| 1542 |
Expr, Offset, FragmentSize); |
--- |
1542 |
Expr, Offset, FragmentSize); |
--- |
| 1543 |
if (!FragmentExpr) |
0 |
1543 |
if (!FragmentExpr) |
0 |
| 1544 |
continue; |
0 |
1544 |
continue; |
0 |
| 1545 |
SDDbgValue *SDV = DAG.getVRegDbgValue( |
0 |
1545 |
SDDbgValue *SDV = DAG.getVRegDbgValue( |
0 |
| 1546 |
Var, *FragmentExpr, RegAndSize.first, false, DbgLoc, SDNodeOrder); |
0 |
1546 |
Var, *FragmentExpr, RegAndSize.first, false, DbgLoc, SDNodeOrder); |
0 |
| 1547 |
DAG.AddDbgValue(SDV, false); |
0 |
1547 |
DAG.AddDbgValue(SDV, false); |
0 |
| 1548 |
Offset += RegisterSize; |
0 |
1548 |
Offset += RegisterSize; |
0 |
| 1549 |
} |
0 |
1549 |
} |
0 |
| 1550 |
return true; |
0 |
1550 |
return true; |
0 |
| 1551 |
} |
--- |
1551 |
} |
--- |
| 1552 |
// We can use simple vreg locations for variadic dbg_values as well. |
--- |
1552 |
// We can use simple vreg locations for variadic dbg_values as well. |
--- |
| 1553 |
LocationOps.emplace_back(SDDbgOperand::fromVReg(Reg)); |
0 |
1553 |
LocationOps.emplace_back(SDDbgOperand::fromVReg(Reg)); |
0 |
| 1554 |
continue; |
0 |
1554 |
continue; |
0 |
| 1555 |
} |
0 |
1555 |
} |
0 |
| 1556 |
// We failed to create a SDDbgOperand for V. |
--- |
1556 |
// We failed to create a SDDbgOperand for V. |
--- |
| 1557 |
return false; |
0 |
1557 |
return false; |
0 |
| 1558 |
} |
--- |
1558 |
} |
--- |
| 1559 |
|
--- |
1559 |
|
--- |
| 1560 |
// We have created a SDDbgOperand for each Value in Values. |
--- |
1560 |
// We have created a SDDbgOperand for each Value in Values. |
--- |
| 1561 |
// Should use Order instead of SDNodeOrder? |
--- |
1561 |
// Should use Order instead of SDNodeOrder? |
--- |
| 1562 |
assert(!LocationOps.empty()); |
0 |
1562 |
assert(!LocationOps.empty()); |
0 |
| 1563 |
SDDbgValue *SDV = DAG.getDbgValueList(Var, Expr, LocationOps, Dependencies, |
0 |
1563 |
SDDbgValue *SDV = DAG.getDbgValueList(Var, Expr, LocationOps, Dependencies, |
0 |
| 1564 |
/*IsIndirect=*/false, DbgLoc, |
--- |
1564 |
/*IsIndirect=*/false, DbgLoc, |
--- |
| 1565 |
SDNodeOrder, IsVariadic); |
--- |
1565 |
SDNodeOrder, IsVariadic); |
--- |
| 1566 |
DAG.AddDbgValue(SDV, /*isParameter=*/false); |
0 |
1566 |
DAG.AddDbgValue(SDV, /*isParameter=*/false); |
0 |
| 1567 |
return true; |
0 |
1567 |
return true; |
0 |
| 1568 |
} |
0 |
1568 |
} |
0 |
| 1569 |
|
--- |
1569 |
|
--- |
| 1570 |
void SelectionDAGBuilder::resolveOrClearDbgInfo() { |
4 |
1570 |
void SelectionDAGBuilder::resolveOrClearDbgInfo() { |
4 |
| 1571 |
// Try to fixup any remaining dangling debug info -- and drop it if we can't. |
--- |
1571 |
// Try to fixup any remaining dangling debug info -- and drop it if we can't. |
--- |
| 1572 |
for (auto &Pair : DanglingDebugInfoMap) |
4 |
1572 |
for (auto &Pair : DanglingDebugInfoMap) |
4 |
| 1573 |
for (auto &DDI : Pair.second) |
0 |
1573 |
for (auto &DDI : Pair.second) |
0 |
| 1574 |
salvageUnresolvedDbgValue(DDI); |
0 |
1574 |
salvageUnresolvedDbgValue(DDI); |
0 |
| 1575 |
clearDanglingDebugInfo(); |
4 |
1575 |
clearDanglingDebugInfo(); |
4 |
| 1576 |
} |
4 |
1576 |
} |
4 |
| 1577 |
|
--- |
1577 |
|
--- |
| 1578 |
/// getCopyFromRegs - If there was virtual register allocated for the value V |
--- |
1578 |
/// getCopyFromRegs - If there was virtual register allocated for the value V |
--- |
| 1579 |
/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise. |
--- |
1579 |
/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise. |
--- |
| 1580 |
SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) { |
7 |
1580 |
SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) { |
7 |
| 1581 |
DenseMap::iterator It = FuncInfo.ValueMap.find(V); |
7 |
1581 |
DenseMap::iterator It = FuncInfo.ValueMap.find(V); |
7 |
| 1582 |
SDValue Result; |
7 |
1582 |
SDValue Result; |
7 |
| 1583 |
|
--- |
1583 |
|
--- |
| 1584 |
if (It != FuncInfo.ValueMap.end()) { |
7 |
1584 |
if (It != FuncInfo.ValueMap.end()) { |
7 |
| 1585 |
Register InReg = It->second; |
0 |
1585 |
Register InReg = It->second; |
0 |
| 1586 |
|
--- |
1586 |
|
--- |
| 1587 |
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), |
0 |
1587 |
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), |
0 |
| 1588 |
DAG.getDataLayout(), InReg, Ty, |
0 |
1588 |
DAG.getDataLayout(), InReg, Ty, |
0 |
| 1589 |
std::nullopt); // This is not an ABI copy. |
0 |
1589 |
std::nullopt); // This is not an ABI copy. |
0 |
| 1590 |
SDValue Chain = DAG.getEntryNode(); |
0 |
1590 |
SDValue Chain = DAG.getEntryNode(); |
0 |
| 1591 |
Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, |
0 |
1591 |
Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, |
0 |
| 1592 |
V); |
--- |
1592 |
V); |
--- |
| 1593 |
resolveDanglingDebugInfo(V, Result); |
0 |
1593 |
resolveDanglingDebugInfo(V, Result); |
0 |
| 1594 |
} |
0 |
1594 |
} |
0 |
| 1595 |
|
--- |
1595 |
|
--- |
| 1596 |
return Result; |
7 |
1596 |
return Result; |
7 |
| 1597 |
} |
--- |
1597 |
} |
--- |
| 1598 |
|
--- |
1598 |
|
--- |
| 1599 |
/// getValue - Return an SDValue for the given Value. |
--- |
1599 |
/// getValue - Return an SDValue for the given Value. |
--- |
| 1600 |
SDValue SelectionDAGBuilder::getValue(const Value *V) { |
17 |
1600 |
SDValue SelectionDAGBuilder::getValue(const Value *V) { |
17 |
| 1601 |
// If we already have an SDValue for this value, use it. It's important |
--- |
1601 |
// If we already have an SDValue for this value, use it. It's important |
--- |
| 1602 |
// to do this first, so that we don't create a CopyFromReg if we already |
--- |
1602 |
// to do this first, so that we don't create a CopyFromReg if we already |
--- |
| 1603 |
// have a regular SDValue. |
--- |
1603 |
// have a regular SDValue. |
--- |
| 1604 |
SDValue &N = NodeMap[V]; |
17 |
1604 |
SDValue &N = NodeMap[V]; |
17 |
| 1605 |
if (N.getNode()) return N; |
17 |
1605 |
if (N.getNode()) return N; |
17 |
| 1606 |
|
--- |
1606 |
|
--- |
| 1607 |
// If there's a virtual register allocated and initialized for this |
--- |
1607 |
// If there's a virtual register allocated and initialized for this |
--- |
| 1608 |
// value, use it. |
--- |
1608 |
// value, use it. |
--- |
| 1609 |
if (SDValue copyFromReg = getCopyFromRegs(V, V->getType())) |
7 |
1609 |
if (SDValue copyFromReg = getCopyFromRegs(V, V->getType())) |
7 |
| 1610 |
return copyFromReg; |
0 |
1610 |
return copyFromReg; |
0 |
| 1611 |
|
--- |
1611 |
|
--- |
| 1612 |
// Otherwise create a new SDValue and remember it. |
--- |
1612 |
// Otherwise create a new SDValue and remember it. |
--- |
| 1613 |
SDValue Val = getValueImpl(V); |
7 |
1613 |
SDValue Val = getValueImpl(V); |
7 |
| 1614 |
NodeMap[V] = Val; |
7 |
1614 |
NodeMap[V] = Val; |
7 |
| 1615 |
resolveDanglingDebugInfo(V, Val); |
7 |
1615 |
resolveDanglingDebugInfo(V, Val); |
7 |
| 1616 |
return Val; |
7 |
1616 |
return Val; |
7 |
| 1617 |
} |
--- |
1617 |
} |
--- |
| 1618 |
|
--- |
1618 |
|
--- |
| 1619 |
/// getNonRegisterValue - Return an SDValue for the given Value, but |
--- |
1619 |
/// getNonRegisterValue - Return an SDValue for the given Value, but |
--- |
| 1620 |
/// don't look in FuncInfo.ValueMap for a virtual register. |
--- |
1620 |
/// don't look in FuncInfo.ValueMap for a virtual register. |
--- |
| 1621 |
SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { |
0 |
1621 |
SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { |
0 |
| 1622 |
// If we already have an SDValue for this value, use it. |
--- |
1622 |
// If we already have an SDValue for this value, use it. |
--- |
| 1623 |
SDValue &N = NodeMap[V]; |
0 |
1623 |
SDValue &N = NodeMap[V]; |
0 |
| 1624 |
if (N.getNode()) { |
0 |
1624 |
if (N.getNode()) { |
0 |
| 1625 |
if (isIntOrFPConstant(N)) { |
0 |
1625 |
if (isIntOrFPConstant(N)) { |
0 |
| 1626 |
// Remove the debug location from the node as the node is about to be used |
--- |
1626 |
// Remove the debug location from the node as the node is about to be used |
--- |
| 1627 |
// in a location which may differ from the original debug location. This |
--- |
1627 |
// in a location which may differ from the original debug location. This |
--- |
| 1628 |
// is relevant to Constant and ConstantFP nodes because they can appear |
--- |
1628 |
// is relevant to Constant and ConstantFP nodes because they can appear |
--- |
| 1629 |
// as constant expressions inside PHI nodes. |
--- |
1629 |
// as constant expressions inside PHI nodes. |
--- |
| 1630 |
N->setDebugLoc(DebugLoc()); |
0 |
1630 |
N->setDebugLoc(DebugLoc()); |
0 |
| 1631 |
} |
--- |
1631 |
} |
--- |
| 1632 |
return N; |
0 |
1632 |
return N; |
0 |
| 1633 |
} |
--- |
1633 |
} |
--- |
| 1634 |
|
--- |
1634 |
|
--- |
| 1635 |
// Otherwise create a new SDValue and remember it. |
--- |
1635 |
// Otherwise create a new SDValue and remember it. |
--- |
| 1636 |
SDValue Val = getValueImpl(V); |
0 |
1636 |
SDValue Val = getValueImpl(V); |
0 |
| 1637 |
NodeMap[V] = Val; |
0 |
1637 |
NodeMap[V] = Val; |
0 |
| 1638 |
resolveDanglingDebugInfo(V, Val); |
0 |
1638 |
resolveDanglingDebugInfo(V, Val); |
0 |
| 1639 |
return Val; |
0 |
1639 |
return Val; |
0 |
| 1640 |
} |
--- |
1640 |
} |
--- |
| 1641 |
|
--- |
1641 |
|
--- |
| 1642 |
/// getValueImpl - Helper function for getValue and getNonRegisterValue. |
--- |
1642 |
/// getValueImpl - Helper function for getValue and getNonRegisterValue. |
--- |
| 1643 |
/// Create an SDValue for the given value. |
--- |
1643 |
/// Create an SDValue for the given value. |
--- |
| 1644 |
SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { |
7 |
1644 |
SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { |
7 |
| 1645 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
7 |
1645 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
7 |
| 1646 |
|
--- |
1646 |
|
--- |
| 1647 |
if (const Constant *C = dyn_cast(V)) { |
7 |
1647 |
if (const Constant *C = dyn_cast(V)) { |
7 |
| 1648 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true); |
0 |
1648 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true); |
0 |
| 1649 |
|
--- |
1649 |
|
--- |
| 1650 |
if (const ConstantInt *CI = dyn_cast(C)) |
0 |
1650 |
if (const ConstantInt *CI = dyn_cast(C)) |
0 |
| 1651 |
return DAG.getConstant(*CI, getCurSDLoc(), VT); |
0 |
1651 |
return DAG.getConstant(*CI, getCurSDLoc(), VT); |
0 |
| 1652 |
|
--- |
1652 |
|
--- |
| 1653 |
if (const GlobalValue *GV = dyn_cast(C)) |
0 |
1653 |
if (const GlobalValue *GV = dyn_cast(C)) |
0 |
| 1654 |
return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); |
0 |
1654 |
return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); |
0 |
| 1655 |
|
--- |
1655 |
|
--- |
| 1656 |
if (isa(C)) { |
0 |
1656 |
if (isa(C)) { |
0 |
| 1657 |
unsigned AS = V->getType()->getPointerAddressSpace(); |
0 |
1657 |
unsigned AS = V->getType()->getPointerAddressSpace(); |
0 |
| 1658 |
return DAG.getConstant(0, getCurSDLoc(), |
0 |
1658 |
return DAG.getConstant(0, getCurSDLoc(), |
0 |
| 1659 |
TLI.getPointerTy(DAG.getDataLayout(), AS)); |
0 |
1659 |
TLI.getPointerTy(DAG.getDataLayout(), AS)); |
0 |
| 1660 |
} |
--- |
1660 |
} |
--- |
| 1661 |
|
--- |
1661 |
|
--- |
| 1662 |
if (match(C, m_VScale())) |
0 |
1662 |
if (match(C, m_VScale())) |
0 |
| 1663 |
return DAG.getVScale(getCurSDLoc(), VT, APInt(VT.getSizeInBits(), 1)); |
0 |
1663 |
return DAG.getVScale(getCurSDLoc(), VT, APInt(VT.getSizeInBits(), 1)); |
0 |
| 1664 |
|
--- |
1664 |
|
--- |
| 1665 |
if (const ConstantFP *CFP = dyn_cast(C)) |
0 |
1665 |
if (const ConstantFP *CFP = dyn_cast(C)) |
0 |
| 1666 |
return DAG.getConstantFP(*CFP, getCurSDLoc(), VT); |
0 |
1666 |
return DAG.getConstantFP(*CFP, getCurSDLoc(), VT); |
0 |
| 1667 |
|
--- |
1667 |
|
--- |
| 1668 |
if (isa(C) && !V->getType()->isAggregateType()) |
0 |
1668 |
if (isa(C) && !V->getType()->isAggregateType()) |
0 |
| 1669 |
return DAG.getUNDEF(VT); |
0 |
1669 |
return DAG.getUNDEF(VT); |
0 |
| 1670 |
|
--- |
1670 |
|
--- |
| 1671 |
if (const ConstantExpr *CE = dyn_cast(C)) { |
0 |
1671 |
if (const ConstantExpr *CE = dyn_cast(C)) { |
0 |
| 1672 |
visit(CE->getOpcode(), *CE); |
0 |
1672 |
visit(CE->getOpcode(), *CE); |
0 |
| 1673 |
SDValue N1 = NodeMap[V]; |
0 |
1673 |
SDValue N1 = NodeMap[V]; |
0 |
| 1674 |
assert(N1.getNode() && "visit didn't populate the NodeMap!"); |
0 |
1674 |
assert(N1.getNode() && "visit didn't populate the NodeMap!"); |
0 |
| 1675 |
return N1; |
0 |
1675 |
return N1; |
0 |
| 1676 |
} |
--- |
1676 |
} |
--- |
| 1677 |
|
--- |
1677 |
|
--- |
| 1678 |
if (isa(C) || isa(C)) { |
0 |
1678 |
if (isa(C) || isa(C)) { |
0 |
| 1679 |
SmallVector Constants; |
0 |
1679 |
SmallVector Constants; |
0 |
| 1680 |
for (const Use &U : C->operands()) { |
0 |
1680 |
for (const Use &U : C->operands()) { |
0 |
| 1681 |
SDNode *Val = getValue(U).getNode(); |
0 |
1681 |
SDNode *Val = getValue(U).getNode(); |
0 |
| 1682 |
// If the operand is an empty aggregate, there are no values. |
--- |
1682 |
// If the operand is an empty aggregate, there are no values. |
--- |
| 1683 |
if (!Val) continue; |
0 |
1683 |
if (!Val) continue; |
0 |
| 1684 |
// Add each leaf value from the operand to the Constants list |
--- |
1684 |
// Add each leaf value from the operand to the Constants list |
--- |
| 1685 |
// to form a flattened list of all the values. |
--- |
1685 |
// to form a flattened list of all the values. |
--- |
| 1686 |
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) |
0 |
1686 |
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) |
0 |
| 1687 |
Constants.push_back(SDValue(Val, i)); |
0 |
1687 |
Constants.push_back(SDValue(Val, i)); |
0 |
| 1688 |
} |
--- |
1688 |
} |
--- |
| 1689 |
|
--- |
1689 |
|
--- |
| 1690 |
return DAG.getMergeValues(Constants, getCurSDLoc()); |
0 |
1690 |
return DAG.getMergeValues(Constants, getCurSDLoc()); |
0 |
| 1691 |
} |
0 |
1691 |
} |
0 |
| 1692 |
|
--- |
1692 |
|
--- |
| 1693 |
if (const ConstantDataSequential *CDS = |
0 |
1693 |
if (const ConstantDataSequential *CDS = |
0 |
| 1694 |
dyn_cast(C)) { |
0 |
1694 |
dyn_cast(C)) { |
0 |
| 1695 |
SmallVector Ops; |
0 |
1695 |
SmallVector Ops; |
0 |
| 1696 |
for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { |
0 |
1696 |
for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { |
0 |
| 1697 |
SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); |
0 |
1697 |
SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); |
0 |
| 1698 |
// Add each leaf value from the operand to the Constants list |
--- |
1698 |
// Add each leaf value from the operand to the Constants list |
--- |
| 1699 |
// to form a flattened list of all the values. |
--- |
1699 |
// to form a flattened list of all the values. |
--- |
| 1700 |
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) |
0 |
1700 |
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) |
0 |
| 1701 |
Ops.push_back(SDValue(Val, i)); |
0 |
1701 |
Ops.push_back(SDValue(Val, i)); |
0 |
| 1702 |
} |
--- |
1702 |
} |
--- |
| 1703 |
|
--- |
1703 |
|
--- |
| 1704 |
if (isa(CDS->getType())) |
0 |
1704 |
if (isa(CDS->getType())) |
0 |
| 1705 |
return DAG.getMergeValues(Ops, getCurSDLoc()); |
0 |
1705 |
return DAG.getMergeValues(Ops, getCurSDLoc()); |
0 |
| 1706 |
return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); |
0 |
1706 |
return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); |
0 |
| 1707 |
} |
0 |
1707 |
} |
0 |
| 1708 |
|
--- |
1708 |
|
--- |
| 1709 |
if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { |
0 |
1709 |
if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { |
0 |
| 1710 |
assert((isa(C) || isa(C)) && |
0 |
1710 |
assert((isa(C) || isa(C)) && |
0 |
| 1711 |
"Unknown struct or array constant!"); |
--- |
1711 |
"Unknown struct or array constant!"); |
--- |
| 1712 |
|
--- |
1712 |
|
--- |
| 1713 |
SmallVector ValueVTs; |
0 |
1713 |
SmallVector ValueVTs; |
0 |
| 1714 |
ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs); |
0 |
1714 |
ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs); |
0 |
| 1715 |
unsigned NumElts = ValueVTs.size(); |
0 |
1715 |
unsigned NumElts = ValueVTs.size(); |
0 |
| 1716 |
if (NumElts == 0) |
0 |
1716 |
if (NumElts == 0) |
0 |
| 1717 |
return SDValue(); // empty struct |
0 |
1717 |
return SDValue(); // empty struct |
0 |
| 1718 |
SmallVector Constants(NumElts); |
0 |
1718 |
SmallVector Constants(NumElts); |
0 |
| 1719 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
1719 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 1720 |
EVT EltVT = ValueVTs[i]; |
0 |
1720 |
EVT EltVT = ValueVTs[i]; |
0 |
| 1721 |
if (isa(C)) |
0 |
1721 |
if (isa(C)) |
0 |
| 1722 |
Constants[i] = DAG.getUNDEF(EltVT); |
0 |
1722 |
Constants[i] = DAG.getUNDEF(EltVT); |
0 |
| 1723 |
else if (EltVT.isFloatingPoint()) |
0 |
1723 |
else if (EltVT.isFloatingPoint()) |
0 |
| 1724 |
Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT); |
0 |
1724 |
Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT); |
0 |
| 1725 |
else |
--- |
1725 |
else |
--- |
| 1726 |
Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT); |
0 |
1726 |
Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT); |
0 |
| 1727 |
} |
--- |
1727 |
} |
--- |
| 1728 |
|
--- |
1728 |
|
--- |
| 1729 |
return DAG.getMergeValues(Constants, getCurSDLoc()); |
0 |
1729 |
return DAG.getMergeValues(Constants, getCurSDLoc()); |
0 |
| 1730 |
} |
0 |
1730 |
} |
0 |
| 1731 |
|
--- |
1731 |
|
--- |
| 1732 |
if (const BlockAddress *BA = dyn_cast(C)) |
0 |
1732 |
if (const BlockAddress *BA = dyn_cast(C)) |
0 |
| 1733 |
return DAG.getBlockAddress(BA, VT); |
0 |
1733 |
return DAG.getBlockAddress(BA, VT); |
0 |
| 1734 |
|
--- |
1734 |
|
--- |
| 1735 |
if (const auto *Equiv = dyn_cast(C)) |
0 |
1735 |
if (const auto *Equiv = dyn_cast(C)) |
0 |
| 1736 |
return getValue(Equiv->getGlobalValue()); |
0 |
1736 |
return getValue(Equiv->getGlobalValue()); |
0 |
| 1737 |
|
--- |
1737 |
|
--- |
| 1738 |
if (const auto *NC = dyn_cast(C)) |
0 |
1738 |
if (const auto *NC = dyn_cast(C)) |
0 |
| 1739 |
return getValue(NC->getGlobalValue()); |
0 |
1739 |
return getValue(NC->getGlobalValue()); |
0 |
| 1740 |
|
--- |
1740 |
|
--- |
| 1741 |
VectorType *VecTy = cast(V->getType()); |
0 |
1741 |
VectorType *VecTy = cast(V->getType()); |
0 |
| 1742 |
|
--- |
1742 |
|
--- |
| 1743 |
// Now that we know the number and type of the elements, get that number of |
--- |
1743 |
// Now that we know the number and type of the elements, get that number of |
--- |
| 1744 |
// elements into the Ops array based on what kind of constant it is. |
--- |
1744 |
// elements into the Ops array based on what kind of constant it is. |
--- |
| 1745 |
if (const ConstantVector *CV = dyn_cast(C)) { |
0 |
1745 |
if (const ConstantVector *CV = dyn_cast(C)) { |
0 |
| 1746 |
SmallVector Ops; |
0 |
1746 |
SmallVector Ops; |
0 |
| 1747 |
unsigned NumElements = cast(VecTy)->getNumElements(); |
0 |
1747 |
unsigned NumElements = cast(VecTy)->getNumElements(); |
0 |
| 1748 |
for (unsigned i = 0; i != NumElements; ++i) |
0 |
1748 |
for (unsigned i = 0; i != NumElements; ++i) |
0 |
| 1749 |
Ops.push_back(getValue(CV->getOperand(i))); |
0 |
1749 |
Ops.push_back(getValue(CV->getOperand(i))); |
0 |
| 1750 |
|
--- |
1750 |
|
--- |
| 1751 |
return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); |
0 |
1751 |
return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); |
0 |
| 1752 |
} |
0 |
1752 |
} |
0 |
| 1753 |
|
--- |
1753 |
|
--- |
| 1754 |
if (isa(C)) { |
0 |
1754 |
if (isa(C)) { |
0 |
| 1755 |
EVT EltVT = |
--- |
1755 |
EVT EltVT = |
--- |
| 1756 |
TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType()); |
0 |
1756 |
TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType()); |
0 |
| 1757 |
|
--- |
1757 |
|
--- |
| 1758 |
SDValue Op; |
0 |
1758 |
SDValue Op; |
0 |
| 1759 |
if (EltVT.isFloatingPoint()) |
0 |
1759 |
if (EltVT.isFloatingPoint()) |
0 |
| 1760 |
Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT); |
0 |
1760 |
Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT); |
0 |
| 1761 |
else |
--- |
1761 |
else |
--- |
| 1762 |
Op = DAG.getConstant(0, getCurSDLoc(), EltVT); |
0 |
1762 |
Op = DAG.getConstant(0, getCurSDLoc(), EltVT); |
0 |
| 1763 |
|
--- |
1763 |
|
--- |
| 1764 |
return NodeMap[V] = DAG.getSplat(VT, getCurSDLoc(), Op); |
0 |
1764 |
return NodeMap[V] = DAG.getSplat(VT, getCurSDLoc(), Op); |
0 |
| 1765 |
} |
--- |
1765 |
} |
--- |
| 1766 |
|
--- |
1766 |
|
--- |
| 1767 |
llvm_unreachable("Unknown vector constant"); |
0 |
1767 |
llvm_unreachable("Unknown vector constant"); |
0 |
| 1768 |
} |
--- |
1768 |
} |
--- |
| 1769 |
|
--- |
1769 |
|
--- |
| 1770 |
// If this is a static alloca, generate it as the frameindex instead of |
--- |
1770 |
// If this is a static alloca, generate it as the frameindex instead of |
--- |
| 1771 |
// computation. |
--- |
1771 |
// computation. |
--- |
| 1772 |
if (const AllocaInst *AI = dyn_cast(V)) { |
7 |
1772 |
if (const AllocaInst *AI = dyn_cast(V)) { |
7 |
| 1773 |
DenseMap::iterator SI = |
--- |
1773 |
DenseMap::iterator SI = |
--- |
| 1774 |
FuncInfo.StaticAllocaMap.find(AI); |
7 |
1774 |
FuncInfo.StaticAllocaMap.find(AI); |
7 |
| 1775 |
if (SI != FuncInfo.StaticAllocaMap.end()) |
7 |
1775 |
if (SI != FuncInfo.StaticAllocaMap.end()) |
7 |
| 1776 |
return DAG.getFrameIndex( |
14 |
1776 |
return DAG.getFrameIndex( |
14 |
| 1777 |
SI->second, TLI.getValueType(DAG.getDataLayout(), AI->getType())); |
21 |
1777 |
SI->second, TLI.getValueType(DAG.getDataLayout(), AI->getType())); |
21 |
| 1778 |
} |
--- |
1778 |
} |
--- |
| 1779 |
|
--- |
1779 |
|
--- |
| 1780 |
// If this is an instruction which fast-isel has deferred, select it now. |
--- |
1780 |
// If this is an instruction which fast-isel has deferred, select it now. |
--- |
| 1781 |
if (const Instruction *Inst = dyn_cast(V)) { |
0 |
1781 |
if (const Instruction *Inst = dyn_cast(V)) { |
0 |
| 1782 |
Register InReg = FuncInfo.InitializeRegForValue(Inst); |
0 |
1782 |
Register InReg = FuncInfo.InitializeRegForValue(Inst); |
0 |
| 1783 |
|
--- |
1783 |
|
--- |
| 1784 |
RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, |
0 |
1784 |
RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, |
0 |
| 1785 |
Inst->getType(), std::nullopt); |
0 |
1785 |
Inst->getType(), std::nullopt); |
0 |
| 1786 |
SDValue Chain = DAG.getEntryNode(); |
0 |
1786 |
SDValue Chain = DAG.getEntryNode(); |
0 |
| 1787 |
return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V); |
0 |
1787 |
return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V); |
0 |
| 1788 |
} |
0 |
1788 |
} |
0 |
| 1789 |
|
--- |
1789 |
|
--- |
| 1790 |
if (const MetadataAsValue *MD = dyn_cast(V)) |
0 |
1790 |
if (const MetadataAsValue *MD = dyn_cast(V)) |
0 |
| 1791 |
return DAG.getMDNode(cast(MD->getMetadata())); |
0 |
1791 |
return DAG.getMDNode(cast(MD->getMetadata())); |
0 |
| 1792 |
|
--- |
1792 |
|
--- |
| 1793 |
if (const auto *BB = dyn_cast(V)) |
0 |
1793 |
if (const auto *BB = dyn_cast(V)) |
0 |
| 1794 |
return DAG.getBasicBlock(FuncInfo.MBBMap[BB]); |
0 |
1794 |
return DAG.getBasicBlock(FuncInfo.MBBMap[BB]); |
0 |
| 1795 |
|
--- |
1795 |
|
--- |
| 1796 |
llvm_unreachable("Can't get register for value!"); |
0 |
1796 |
llvm_unreachable("Can't get register for value!"); |
0 |
| 1797 |
} |
--- |
1797 |
} |
--- |
| 1798 |
|
--- |
1798 |
|
--- |
| 1799 |
void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) { |
0 |
1799 |
void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) { |
0 |
| 1800 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
1800 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
| 1801 |
bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX; |
0 |
1801 |
bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX; |
0 |
| 1802 |
bool IsCoreCLR = Pers == EHPersonality::CoreCLR; |
0 |
1802 |
bool IsCoreCLR = Pers == EHPersonality::CoreCLR; |
0 |
| 1803 |
bool IsSEH = isAsynchronousEHPersonality(Pers); |
0 |
1803 |
bool IsSEH = isAsynchronousEHPersonality(Pers); |
0 |
| 1804 |
MachineBasicBlock *CatchPadMBB = FuncInfo.MBB; |
0 |
1804 |
MachineBasicBlock *CatchPadMBB = FuncInfo.MBB; |
0 |
| 1805 |
if (!IsSEH) |
0 |
1805 |
if (!IsSEH) |
0 |
| 1806 |
CatchPadMBB->setIsEHScopeEntry(); |
0 |
1806 |
CatchPadMBB->setIsEHScopeEntry(); |
0 |
| 1807 |
// In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues. |
--- |
1807 |
// In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues. |
--- |
| 1808 |
if (IsMSVCCXX || IsCoreCLR) |
0 |
1808 |
if (IsMSVCCXX || IsCoreCLR) |
0 |
| 1809 |
CatchPadMBB->setIsEHFuncletEntry(); |
0 |
1809 |
CatchPadMBB->setIsEHFuncletEntry(); |
0 |
| 1810 |
} |
0 |
1810 |
} |
0 |
| 1811 |
|
--- |
1811 |
|
--- |
| 1812 |
void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) { |
0 |
1812 |
void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) { |
0 |
| 1813 |
// Update machine-CFG edge. |
--- |
1813 |
// Update machine-CFG edge. |
--- |
| 1814 |
MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()]; |
0 |
1814 |
MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()]; |
0 |
| 1815 |
FuncInfo.MBB->addSuccessor(TargetMBB); |
0 |
1815 |
FuncInfo.MBB->addSuccessor(TargetMBB); |
0 |
| 1816 |
TargetMBB->setIsEHCatchretTarget(true); |
0 |
1816 |
TargetMBB->setIsEHCatchretTarget(true); |
0 |
| 1817 |
DAG.getMachineFunction().setHasEHCatchret(true); |
0 |
1817 |
DAG.getMachineFunction().setHasEHCatchret(true); |
0 |
| 1818 |
|
--- |
1818 |
|
--- |
| 1819 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
1819 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
| 1820 |
bool IsSEH = isAsynchronousEHPersonality(Pers); |
0 |
1820 |
bool IsSEH = isAsynchronousEHPersonality(Pers); |
0 |
| 1821 |
if (IsSEH) { |
0 |
1821 |
if (IsSEH) { |
0 |
| 1822 |
// If this is not a fall-through branch or optimizations are switched off, |
--- |
1822 |
// If this is not a fall-through branch or optimizations are switched off, |
--- |
| 1823 |
// emit the branch. |
--- |
1823 |
// emit the branch. |
--- |
| 1824 |
if (TargetMBB != NextBlock(FuncInfo.MBB) || |
0 |
1824 |
if (TargetMBB != NextBlock(FuncInfo.MBB) || |
0 |
| 1825 |
TM.getOptLevel() == CodeGenOpt::None) |
0 |
1825 |
TM.getOptLevel() == CodeGenOpt::None) |
0 |
| 1826 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, |
0 |
1826 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, |
0 |
| 1827 |
getControlRoot(), DAG.getBasicBlock(TargetMBB))); |
0 |
1827 |
getControlRoot(), DAG.getBasicBlock(TargetMBB))); |
0 |
| 1828 |
return; |
0 |
1828 |
return; |
0 |
| 1829 |
} |
--- |
1829 |
} |
--- |
| 1830 |
|
--- |
1830 |
|
--- |
| 1831 |
// Figure out the funclet membership for the catchret's successor. |
--- |
1831 |
// Figure out the funclet membership for the catchret's successor. |
--- |
| 1832 |
// This will be used by the FuncletLayout pass to determine how to order the |
--- |
1832 |
// This will be used by the FuncletLayout pass to determine how to order the |
--- |
| 1833 |
// BB's. |
--- |
1833 |
// BB's. |
--- |
| 1834 |
// A 'catchret' returns to the outer scope's color. |
--- |
1834 |
// A 'catchret' returns to the outer scope's color. |
--- |
| 1835 |
Value *ParentPad = I.getCatchSwitchParentPad(); |
0 |
1835 |
Value *ParentPad = I.getCatchSwitchParentPad(); |
0 |
| 1836 |
const BasicBlock *SuccessorColor; |
--- |
1836 |
const BasicBlock *SuccessorColor; |
--- |
| 1837 |
if (isa(ParentPad)) |
0 |
1837 |
if (isa(ParentPad)) |
0 |
| 1838 |
SuccessorColor = &FuncInfo.Fn->getEntryBlock(); |
0 |
1838 |
SuccessorColor = &FuncInfo.Fn->getEntryBlock(); |
0 |
| 1839 |
else |
--- |
1839 |
else |
--- |
| 1840 |
SuccessorColor = cast(ParentPad)->getParent(); |
0 |
1840 |
SuccessorColor = cast(ParentPad)->getParent(); |
0 |
| 1841 |
assert(SuccessorColor && "No parent funclet for catchret!"); |
0 |
1841 |
assert(SuccessorColor && "No parent funclet for catchret!"); |
0 |
| 1842 |
MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor]; |
0 |
1842 |
MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor]; |
0 |
| 1843 |
assert(SuccessorColorMBB && "No MBB for SuccessorColor!"); |
0 |
1843 |
assert(SuccessorColorMBB && "No MBB for SuccessorColor!"); |
0 |
| 1844 |
|
--- |
1844 |
|
--- |
| 1845 |
// Create the terminator node. |
--- |
1845 |
// Create the terminator node. |
--- |
| 1846 |
SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other, |
0 |
1846 |
SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other, |
0 |
| 1847 |
getControlRoot(), DAG.getBasicBlock(TargetMBB), |
0 |
1847 |
getControlRoot(), DAG.getBasicBlock(TargetMBB), |
0 |
| 1848 |
DAG.getBasicBlock(SuccessorColorMBB)); |
0 |
1848 |
DAG.getBasicBlock(SuccessorColorMBB)); |
0 |
| 1849 |
DAG.setRoot(Ret); |
0 |
1849 |
DAG.setRoot(Ret); |
0 |
| 1850 |
} |
--- |
1850 |
} |
--- |
| 1851 |
|
--- |
1851 |
|
--- |
| 1852 |
void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) { |
0 |
1852 |
void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) { |
0 |
| 1853 |
// Don't emit any special code for the cleanuppad instruction. It just marks |
--- |
1853 |
// Don't emit any special code for the cleanuppad instruction. It just marks |
--- |
| 1854 |
// the start of an EH scope/funclet. |
--- |
1854 |
// the start of an EH scope/funclet. |
--- |
| 1855 |
FuncInfo.MBB->setIsEHScopeEntry(); |
0 |
1855 |
FuncInfo.MBB->setIsEHScopeEntry(); |
0 |
| 1856 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
1856 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
| 1857 |
if (Pers != EHPersonality::Wasm_CXX) { |
0 |
1857 |
if (Pers != EHPersonality::Wasm_CXX) { |
0 |
| 1858 |
FuncInfo.MBB->setIsEHFuncletEntry(); |
0 |
1858 |
FuncInfo.MBB->setIsEHFuncletEntry(); |
0 |
| 1859 |
FuncInfo.MBB->setIsCleanupFuncletEntry(); |
0 |
1859 |
FuncInfo.MBB->setIsCleanupFuncletEntry(); |
0 |
| 1860 |
} |
--- |
1860 |
} |
--- |
| 1861 |
} |
0 |
1861 |
} |
0 |
| 1862 |
|
--- |
1862 |
|
--- |
| 1863 |
// In wasm EH, even though a catchpad may not catch an exception if a tag does |
--- |
1863 |
// In wasm EH, even though a catchpad may not catch an exception if a tag does |
--- |
| 1864 |
// not match, it is OK to add only the first unwind destination catchpad to the |
--- |
1864 |
// not match, it is OK to add only the first unwind destination catchpad to the |
--- |
| 1865 |
// successors, because there will be at least one invoke instruction within the |
--- |
1865 |
// successors, because there will be at least one invoke instruction within the |
--- |
| 1866 |
// catch scope that points to the next unwind destination, if one exists, so |
--- |
1866 |
// catch scope that points to the next unwind destination, if one exists, so |
--- |
| 1867 |
// CFGSort cannot mess up with BB sorting order. |
--- |
1867 |
// CFGSort cannot mess up with BB sorting order. |
--- |
| 1868 |
// (All catchpads with 'catch (type)' clauses have a 'llvm.rethrow' intrinsic |
--- |
1868 |
// (All catchpads with 'catch (type)' clauses have a 'llvm.rethrow' intrinsic |
--- |
| 1869 |
// call within them, and catchpads only consisting of 'catch (...)' have a |
--- |
1869 |
// call within them, and catchpads only consisting of 'catch (...)' have a |
--- |
| 1870 |
// '__cxa_end_catch' call within them, both of which generate invokes in case |
--- |
1870 |
// '__cxa_end_catch' call within them, both of which generate invokes in case |
--- |
| 1871 |
// the next unwind destination exists, i.e., the next unwind destination is not |
--- |
1871 |
// the next unwind destination exists, i.e., the next unwind destination is not |
--- |
| 1872 |
// the caller.) |
--- |
1872 |
// the caller.) |
--- |
| 1873 |
// |
--- |
1873 |
// |
--- |
| 1874 |
// Having at most one EH pad successor is also simpler and helps later |
--- |
1874 |
// Having at most one EH pad successor is also simpler and helps later |
--- |
| 1875 |
// transformations. |
--- |
1875 |
// transformations. |
--- |
| 1876 |
// |
--- |
1876 |
// |
--- |
| 1877 |
// For example, |
--- |
1877 |
// For example, |
--- |
| 1878 |
// current: |
--- |
1878 |
// current: |
--- |
| 1879 |
// invoke void @foo to ... unwind label %catch.dispatch |
--- |
1879 |
// invoke void @foo to ... unwind label %catch.dispatch |
--- |
| 1880 |
// catch.dispatch: |
--- |
1880 |
// catch.dispatch: |
--- |
| 1881 |
// %0 = catchswitch within ... [label %catch.start] unwind label %next |
--- |
1881 |
// %0 = catchswitch within ... [label %catch.start] unwind label %next |
--- |
| 1882 |
// catch.start: |
--- |
1882 |
// catch.start: |
--- |
| 1883 |
// ... |
--- |
1883 |
// ... |
--- |
| 1884 |
// ... in this BB or some other child BB dominated by this BB there will be an |
--- |
1884 |
// ... in this BB or some other child BB dominated by this BB there will be an |
--- |
| 1885 |
// invoke that points to 'next' BB as an unwind destination |
--- |
1885 |
// invoke that points to 'next' BB as an unwind destination |
--- |
| 1886 |
// |
--- |
1886 |
// |
--- |
| 1887 |
// next: ; We don't need to add this to 'current' BB's successor |
--- |
1887 |
// next: ; We don't need to add this to 'current' BB's successor |
--- |
| 1888 |
// ... |
--- |
1888 |
// ... |
--- |
| 1889 |
static void findWasmUnwindDestinations( |
0 |
1889 |
static void findWasmUnwindDestinations( |
0 |
| 1890 |
FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, |
--- |
1890 |
FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, |
--- |
| 1891 |
BranchProbability Prob, |
--- |
1891 |
BranchProbability Prob, |
--- |
| 1892 |
SmallVectorImpl> |
--- |
1892 |
SmallVectorImpl> |
--- |
| 1893 |
&UnwindDests) { |
--- |
1893 |
&UnwindDests) { |
--- |
| 1894 |
while (EHPadBB) { |
0 |
1894 |
while (EHPadBB) { |
0 |
| 1895 |
const Instruction *Pad = EHPadBB->getFirstNonPHI(); |
0 |
1895 |
const Instruction *Pad = EHPadBB->getFirstNonPHI(); |
0 |
| 1896 |
if (isa(Pad)) { |
0 |
1896 |
if (isa(Pad)) { |
0 |
| 1897 |
// Stop on cleanup pads. |
--- |
1897 |
// Stop on cleanup pads. |
--- |
| 1898 |
UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); |
0 |
1898 |
UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); |
0 |
| 1899 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
1899 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
| 1900 |
break; |
0 |
1900 |
break; |
0 |
| 1901 |
} else if (const auto *CatchSwitch = dyn_cast(Pad)) { |
0 |
1901 |
} else if (const auto *CatchSwitch = dyn_cast(Pad)) { |
0 |
| 1902 |
// Add the catchpad handlers to the possible destinations. We don't |
--- |
1902 |
// Add the catchpad handlers to the possible destinations. We don't |
--- |
| 1903 |
// continue to the unwind destination of the catchswitch for wasm. |
--- |
1903 |
// continue to the unwind destination of the catchswitch for wasm. |
--- |
| 1904 |
for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { |
0 |
1904 |
for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { |
0 |
| 1905 |
UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); |
0 |
1905 |
UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); |
0 |
| 1906 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
1906 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
| 1907 |
} |
--- |
1907 |
} |
--- |
| 1908 |
break; |
0 |
1908 |
break; |
0 |
| 1909 |
} else { |
--- |
1909 |
} else { |
--- |
| 1910 |
continue; |
0 |
1910 |
continue; |
0 |
| 1911 |
} |
--- |
1911 |
} |
--- |
| 1912 |
} |
--- |
1912 |
} |
--- |
| 1913 |
} |
0 |
1913 |
} |
0 |
| 1914 |
|
--- |
1914 |
|
--- |
| 1915 |
/// When an invoke or a cleanupret unwinds to the next EH pad, there are |
--- |
1915 |
/// When an invoke or a cleanupret unwinds to the next EH pad, there are |
--- |
| 1916 |
/// many places it could ultimately go. In the IR, we have a single unwind |
--- |
1916 |
/// many places it could ultimately go. In the IR, we have a single unwind |
--- |
| 1917 |
/// destination, but in the machine CFG, we enumerate all the possible blocks. |
--- |
1917 |
/// destination, but in the machine CFG, we enumerate all the possible blocks. |
--- |
| 1918 |
/// This function skips over imaginary basic blocks that hold catchswitch |
--- |
1918 |
/// This function skips over imaginary basic blocks that hold catchswitch |
--- |
| 1919 |
/// instructions, and finds all the "real" machine |
--- |
1919 |
/// instructions, and finds all the "real" machine |
--- |
| 1920 |
/// basic block destinations. As those destinations may not be successors of |
--- |
1920 |
/// basic block destinations. As those destinations may not be successors of |
--- |
| 1921 |
/// EHPadBB, here we also calculate the edge probability to those destinations. |
--- |
1921 |
/// EHPadBB, here we also calculate the edge probability to those destinations. |
--- |
| 1922 |
/// The passed-in Prob is the edge probability to EHPadBB. |
--- |
1922 |
/// The passed-in Prob is the edge probability to EHPadBB. |
--- |
| 1923 |
static void findUnwindDestinations( |
0 |
1923 |
static void findUnwindDestinations( |
0 |
| 1924 |
FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, |
--- |
1924 |
FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, |
--- |
| 1925 |
BranchProbability Prob, |
--- |
1925 |
BranchProbability Prob, |
--- |
| 1926 |
SmallVectorImpl> |
--- |
1926 |
SmallVectorImpl> |
--- |
| 1927 |
&UnwindDests) { |
--- |
1927 |
&UnwindDests) { |
--- |
| 1928 |
EHPersonality Personality = |
--- |
1928 |
EHPersonality Personality = |
--- |
| 1929 |
classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
1929 |
classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
| 1930 |
bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX; |
0 |
1930 |
bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX; |
0 |
| 1931 |
bool IsCoreCLR = Personality == EHPersonality::CoreCLR; |
0 |
1931 |
bool IsCoreCLR = Personality == EHPersonality::CoreCLR; |
0 |
| 1932 |
bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX; |
0 |
1932 |
bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX; |
0 |
| 1933 |
bool IsSEH = isAsynchronousEHPersonality(Personality); |
0 |
1933 |
bool IsSEH = isAsynchronousEHPersonality(Personality); |
0 |
| 1934 |
|
--- |
1934 |
|
--- |
| 1935 |
if (IsWasmCXX) { |
0 |
1935 |
if (IsWasmCXX) { |
0 |
| 1936 |
findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests); |
0 |
1936 |
findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests); |
0 |
| 1937 |
assert(UnwindDests.size() <= 1 && |
0 |
1937 |
assert(UnwindDests.size() <= 1 && |
0 |
| 1938 |
"There should be at most one unwind destination for wasm"); |
--- |
1938 |
"There should be at most one unwind destination for wasm"); |
--- |
| 1939 |
return; |
0 |
1939 |
return; |
0 |
| 1940 |
} |
--- |
1940 |
} |
--- |
| 1941 |
|
--- |
1941 |
|
--- |
| 1942 |
while (EHPadBB) { |
0 |
1942 |
while (EHPadBB) { |
0 |
| 1943 |
const Instruction *Pad = EHPadBB->getFirstNonPHI(); |
0 |
1943 |
const Instruction *Pad = EHPadBB->getFirstNonPHI(); |
0 |
| 1944 |
BasicBlock *NewEHPadBB = nullptr; |
0 |
1944 |
BasicBlock *NewEHPadBB = nullptr; |
0 |
| 1945 |
if (isa(Pad)) { |
0 |
1945 |
if (isa(Pad)) { |
0 |
| 1946 |
// Stop on landingpads. They are not funclets. |
--- |
1946 |
// Stop on landingpads. They are not funclets. |
--- |
| 1947 |
UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); |
0 |
1947 |
UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); |
0 |
| 1948 |
break; |
0 |
1948 |
break; |
0 |
| 1949 |
} else if (isa(Pad)) { |
0 |
1949 |
} else if (isa(Pad)) { |
0 |
| 1950 |
// Stop on cleanup pads. Cleanups are always funclet entries for all known |
--- |
1950 |
// Stop on cleanup pads. Cleanups are always funclet entries for all known |
--- |
| 1951 |
// personalities. |
--- |
1951 |
// personalities. |
--- |
| 1952 |
UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); |
0 |
1952 |
UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); |
0 |
| 1953 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
1953 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
| 1954 |
UnwindDests.back().first->setIsEHFuncletEntry(); |
0 |
1954 |
UnwindDests.back().first->setIsEHFuncletEntry(); |
0 |
| 1955 |
break; |
0 |
1955 |
break; |
0 |
| 1956 |
} else if (const auto *CatchSwitch = dyn_cast(Pad)) { |
0 |
1956 |
} else if (const auto *CatchSwitch = dyn_cast(Pad)) { |
0 |
| 1957 |
// Add the catchpad handlers to the possible destinations. |
--- |
1957 |
// Add the catchpad handlers to the possible destinations. |
--- |
| 1958 |
for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { |
0 |
1958 |
for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { |
0 |
| 1959 |
UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); |
0 |
1959 |
UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); |
0 |
| 1960 |
// For MSVC++ and the CLR, catchblocks are funclets and need prologues. |
--- |
1960 |
// For MSVC++ and the CLR, catchblocks are funclets and need prologues. |
--- |
| 1961 |
if (IsMSVCCXX || IsCoreCLR) |
0 |
1961 |
if (IsMSVCCXX || IsCoreCLR) |
0 |
| 1962 |
UnwindDests.back().first->setIsEHFuncletEntry(); |
0 |
1962 |
UnwindDests.back().first->setIsEHFuncletEntry(); |
0 |
| 1963 |
if (!IsSEH) |
0 |
1963 |
if (!IsSEH) |
0 |
| 1964 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
1964 |
UnwindDests.back().first->setIsEHScopeEntry(); |
0 |
| 1965 |
} |
--- |
1965 |
} |
--- |
| 1966 |
NewEHPadBB = CatchSwitch->getUnwindDest(); |
0 |
1966 |
NewEHPadBB = CatchSwitch->getUnwindDest(); |
0 |
| 1967 |
} else { |
--- |
1967 |
} else { |
--- |
| 1968 |
continue; |
0 |
1968 |
continue; |
0 |
| 1969 |
} |
--- |
1969 |
} |
--- |
| 1970 |
|
--- |
1970 |
|
--- |
| 1971 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
1971 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
| 1972 |
if (BPI && NewEHPadBB) |
0 |
1972 |
if (BPI && NewEHPadBB) |
0 |
| 1973 |
Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB); |
0 |
1973 |
Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB); |
0 |
| 1974 |
EHPadBB = NewEHPadBB; |
0 |
1974 |
EHPadBB = NewEHPadBB; |
0 |
| 1975 |
} |
--- |
1975 |
} |
--- |
| 1976 |
} |
--- |
1976 |
} |
--- |
| 1977 |
|
--- |
1977 |
|
--- |
| 1978 |
void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) { |
0 |
1978 |
void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) { |
0 |
| 1979 |
// Update successor info. |
--- |
1979 |
// Update successor info. |
--- |
| 1980 |
SmallVector, 1> UnwindDests; |
0 |
1980 |
SmallVector, 1> UnwindDests; |
0 |
| 1981 |
auto UnwindDest = I.getUnwindDest(); |
0 |
1981 |
auto UnwindDest = I.getUnwindDest(); |
0 |
| 1982 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
1982 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
| 1983 |
BranchProbability UnwindDestProb = |
--- |
1983 |
BranchProbability UnwindDestProb = |
--- |
| 1984 |
(BPI && UnwindDest) |
0 |
1984 |
(BPI && UnwindDest) |
0 |
| 1985 |
? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest) |
0 |
1985 |
? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest) |
0 |
| 1986 |
: BranchProbability::getZero(); |
0 |
1986 |
: BranchProbability::getZero(); |
0 |
| 1987 |
findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests); |
0 |
1987 |
findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests); |
0 |
| 1988 |
for (auto &UnwindDest : UnwindDests) { |
0 |
1988 |
for (auto &UnwindDest : UnwindDests) { |
0 |
| 1989 |
UnwindDest.first->setIsEHPad(); |
0 |
1989 |
UnwindDest.first->setIsEHPad(); |
0 |
| 1990 |
addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second); |
0 |
1990 |
addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second); |
0 |
| 1991 |
} |
--- |
1991 |
} |
--- |
| 1992 |
FuncInfo.MBB->normalizeSuccProbs(); |
0 |
1992 |
FuncInfo.MBB->normalizeSuccProbs(); |
0 |
| 1993 |
|
--- |
1993 |
|
--- |
| 1994 |
// Create the terminator node. |
--- |
1994 |
// Create the terminator node. |
--- |
| 1995 |
SDValue Ret = |
--- |
1995 |
SDValue Ret = |
--- |
| 1996 |
DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot()); |
0 |
1996 |
DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot()); |
0 |
| 1997 |
DAG.setRoot(Ret); |
0 |
1997 |
DAG.setRoot(Ret); |
0 |
| 1998 |
} |
0 |
1998 |
} |
0 |
| 1999 |
|
--- |
1999 |
|
--- |
| 2000 |
void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) { |
0 |
2000 |
void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) { |
0 |
| 2001 |
report_fatal_error("visitCatchSwitch not yet implemented!"); |
0 |
2001 |
report_fatal_error("visitCatchSwitch not yet implemented!"); |
0 |
| 2002 |
} |
--- |
2002 |
} |
--- |
| 2003 |
|
--- |
2003 |
|
--- |
| 2004 |
void SelectionDAGBuilder::visitRet(const ReturnInst &I) { |
1 |
2004 |
void SelectionDAGBuilder::visitRet(const ReturnInst &I) { |
1 |
| 2005 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
1 |
2005 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
1 |
| 2006 |
auto &DL = DAG.getDataLayout(); |
1 |
2006 |
auto &DL = DAG.getDataLayout(); |
1 |
| 2007 |
SDValue Chain = getControlRoot(); |
1 |
2007 |
SDValue Chain = getControlRoot(); |
1 |
| 2008 |
SmallVector Outs; |
1 |
2008 |
SmallVector Outs; |
1 |
| 2009 |
SmallVector OutVals; |
1 |
2009 |
SmallVector OutVals; |
1 |
| 2010 |
|
--- |
2010 |
|
--- |
| 2011 |
// Calls to @llvm.experimental.deoptimize don't generate a return value, so |
--- |
2011 |
// Calls to @llvm.experimental.deoptimize don't generate a return value, so |
--- |
| 2012 |
// lower |
--- |
2012 |
// lower |
--- |
| 2013 |
// |
--- |
2013 |
// |
--- |
| 2014 |
// %val = call @llvm.experimental.deoptimize() |
--- |
2014 |
// %val = call @llvm.experimental.deoptimize() |
--- |
| 2015 |
// ret %val |
--- |
2015 |
// ret %val |
--- |
| 2016 |
// |
--- |
2016 |
// |
--- |
| 2017 |
// differently. |
--- |
2017 |
// differently. |
--- |
| 2018 |
if (I.getParent()->getTerminatingDeoptimizeCall()) { |
1 |
2018 |
if (I.getParent()->getTerminatingDeoptimizeCall()) { |
1 |
| 2019 |
LowerDeoptimizingReturn(); |
0 |
2019 |
LowerDeoptimizingReturn(); |
0 |
| 2020 |
return; |
0 |
2020 |
return; |
0 |
| 2021 |
} |
--- |
2021 |
} |
--- |
| 2022 |
|
--- |
2022 |
|
--- |
| 2023 |
if (!FuncInfo.CanLowerReturn) { |
1 |
2023 |
if (!FuncInfo.CanLowerReturn) { |
1 |
| 2024 |
unsigned DemoteReg = FuncInfo.DemoteRegister; |
0 |
2024 |
unsigned DemoteReg = FuncInfo.DemoteRegister; |
0 |
| 2025 |
const Function *F = I.getParent()->getParent(); |
0 |
2025 |
const Function *F = I.getParent()->getParent(); |
0 |
| 2026 |
|
--- |
2026 |
|
--- |
| 2027 |
// Emit a store of the return value through the virtual register. |
--- |
2027 |
// Emit a store of the return value through the virtual register. |
--- |
| 2028 |
// Leave Outs empty so that LowerReturn won't try to load return |
--- |
2028 |
// Leave Outs empty so that LowerReturn won't try to load return |
--- |
| 2029 |
// registers the usual way. |
--- |
2029 |
// registers the usual way. |
--- |
| 2030 |
SmallVector PtrValueVTs; |
0 |
2030 |
SmallVector PtrValueVTs; |
0 |
| 2031 |
ComputeValueVTs(TLI, DL, |
0 |
2031 |
ComputeValueVTs(TLI, DL, |
0 |
| 2032 |
PointerType::get(F->getContext(), |
0 |
2032 |
PointerType::get(F->getContext(), |
0 |
| 2033 |
DAG.getDataLayout().getAllocaAddrSpace()), |
0 |
2033 |
DAG.getDataLayout().getAllocaAddrSpace()), |
0 |
| 2034 |
PtrValueVTs); |
--- |
2034 |
PtrValueVTs); |
--- |
| 2035 |
|
--- |
2035 |
|
--- |
| 2036 |
SDValue RetPtr = |
--- |
2036 |
SDValue RetPtr = |
--- |
| 2037 |
DAG.getCopyFromReg(Chain, getCurSDLoc(), DemoteReg, PtrValueVTs[0]); |
0 |
2037 |
DAG.getCopyFromReg(Chain, getCurSDLoc(), DemoteReg, PtrValueVTs[0]); |
0 |
| 2038 |
SDValue RetOp = getValue(I.getOperand(0)); |
0 |
2038 |
SDValue RetOp = getValue(I.getOperand(0)); |
0 |
| 2039 |
|
--- |
2039 |
|
--- |
| 2040 |
SmallVector ValueVTs, MemVTs; |
0 |
2040 |
SmallVector ValueVTs, MemVTs; |
0 |
| 2041 |
SmallVector Offsets; |
0 |
2041 |
SmallVector Offsets; |
0 |
| 2042 |
ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs, |
0 |
2042 |
ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs, |
0 |
| 2043 |
&Offsets, 0); |
--- |
2043 |
&Offsets, 0); |
--- |
| 2044 |
unsigned NumValues = ValueVTs.size(); |
0 |
2044 |
unsigned NumValues = ValueVTs.size(); |
0 |
| 2045 |
|
--- |
2045 |
|
--- |
| 2046 |
SmallVector Chains(NumValues); |
0 |
2046 |
SmallVector Chains(NumValues); |
0 |
| 2047 |
Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType()); |
0 |
2047 |
Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType()); |
0 |
| 2048 |
for (unsigned i = 0; i != NumValues; ++i) { |
0 |
2048 |
for (unsigned i = 0; i != NumValues; ++i) { |
0 |
| 2049 |
// An aggregate return value cannot wrap around the address space, so |
--- |
2049 |
// An aggregate return value cannot wrap around the address space, so |
--- |
| 2050 |
// offsets to its parts don't wrap either. |
--- |
2050 |
// offsets to its parts don't wrap either. |
--- |
| 2051 |
SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, |
0 |
2051 |
SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, |
0 |
| 2052 |
TypeSize::Fixed(Offsets[i])); |
0 |
2052 |
TypeSize::Fixed(Offsets[i])); |
0 |
| 2053 |
|
--- |
2053 |
|
--- |
| 2054 |
SDValue Val = RetOp.getValue(RetOp.getResNo() + i); |
0 |
2054 |
SDValue Val = RetOp.getValue(RetOp.getResNo() + i); |
0 |
| 2055 |
if (MemVTs[i] != ValueVTs[i]) |
0 |
2055 |
if (MemVTs[i] != ValueVTs[i]) |
0 |
| 2056 |
Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]); |
0 |
2056 |
Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]); |
0 |
| 2057 |
Chains[i] = DAG.getStore( |
0 |
2057 |
Chains[i] = DAG.getStore( |
0 |
| 2058 |
Chain, getCurSDLoc(), Val, |
0 |
2058 |
Chain, getCurSDLoc(), Val, |
0 |
| 2059 |
// FIXME: better loc info would be nice. |
--- |
2059 |
// FIXME: better loc info would be nice. |
--- |
| 2060 |
Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), |
0 |
2060 |
Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), |
0 |
| 2061 |
commonAlignment(BaseAlign, Offsets[i])); |
0 |
2061 |
commonAlignment(BaseAlign, Offsets[i])); |
0 |
| 2062 |
} |
--- |
2062 |
} |
--- |
| 2063 |
|
--- |
2063 |
|
--- |
| 2064 |
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), |
0 |
2064 |
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), |
0 |
| 2065 |
MVT::Other, Chains); |
--- |
2065 |
MVT::Other, Chains); |
--- |
| 2066 |
} else if (I.getNumOperands() != 0) { |
1 |
2066 |
} else if (I.getNumOperands() != 0) { |
1 |
| 2067 |
SmallVector ValueVTs; |
1 |
2067 |
SmallVector ValueVTs; |
1 |
| 2068 |
ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs); |
1 |
2068 |
ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs); |
1 |
| 2069 |
unsigned NumValues = ValueVTs.size(); |
1 |
2069 |
unsigned NumValues = ValueVTs.size(); |
1 |
| 2070 |
if (NumValues) { |
1 |
2070 |
if (NumValues) { |
1 |
| 2071 |
SDValue RetOp = getValue(I.getOperand(0)); |
1 |
2071 |
SDValue RetOp = getValue(I.getOperand(0)); |
1 |
| 2072 |
|
--- |
2072 |
|
--- |
| 2073 |
const Function *F = I.getParent()->getParent(); |
1 |
2073 |
const Function *F = I.getParent()->getParent(); |
1 |
| 2074 |
|
--- |
2074 |
|
--- |
| 2075 |
bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters( |
1 |
2075 |
bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters( |
1 |
| 2076 |
I.getOperand(0)->getType(), F->getCallingConv(), |
--- |
2076 |
I.getOperand(0)->getType(), F->getCallingConv(), |
--- |
| 2077 |
/*IsVarArg*/ false, DL); |
--- |
2077 |
/*IsVarArg*/ false, DL); |
--- |
| 2078 |
|
--- |
2078 |
|
--- |
| 2079 |
ISD::NodeType ExtendKind = ISD::ANY_EXTEND; |
1 |
2079 |
ISD::NodeType ExtendKind = ISD::ANY_EXTEND; |
1 |
| 2080 |
if (F->getAttributes().hasRetAttr(Attribute::SExt)) |
1 |
2080 |
if (F->getAttributes().hasRetAttr(Attribute::SExt)) |
1 |
| 2081 |
ExtendKind = ISD::SIGN_EXTEND; |
0 |
2081 |
ExtendKind = ISD::SIGN_EXTEND; |
0 |
| 2082 |
else if (F->getAttributes().hasRetAttr(Attribute::ZExt)) |
1 |
2082 |
else if (F->getAttributes().hasRetAttr(Attribute::ZExt)) |
1 |
| 2083 |
ExtendKind = ISD::ZERO_EXTEND; |
0 |
2083 |
ExtendKind = ISD::ZERO_EXTEND; |
0 |
| 2084 |
|
--- |
2084 |
|
--- |
| 2085 |
LLVMContext &Context = F->getContext(); |
1 |
2085 |
LLVMContext &Context = F->getContext(); |
1 |
| 2086 |
bool RetInReg = F->getAttributes().hasRetAttr(Attribute::InReg); |
1 |
2086 |
bool RetInReg = F->getAttributes().hasRetAttr(Attribute::InReg); |
1 |
| 2087 |
|
--- |
2087 |
|
--- |
| 2088 |
for (unsigned j = 0; j != NumValues; ++j) { |
2 |
2088 |
for (unsigned j = 0; j != NumValues; ++j) { |
2 |
| 2089 |
EVT VT = ValueVTs[j]; |
1 |
2089 |
EVT VT = ValueVTs[j]; |
1 |
| 2090 |
|
--- |
2090 |
|
--- |
| 2091 |
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) |
1 |
2091 |
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) |
1 |
| 2092 |
VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind); |
0 |
2092 |
VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind); |
0 |
| 2093 |
|
--- |
2093 |
|
--- |
| 2094 |
CallingConv::ID CC = F->getCallingConv(); |
1 |
2094 |
CallingConv::ID CC = F->getCallingConv(); |
1 |
| 2095 |
|
--- |
2095 |
|
--- |
| 2096 |
unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT); |
1 |
2096 |
unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT); |
1 |
| 2097 |
MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT); |
1 |
2097 |
MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT); |
1 |
| 2098 |
SmallVector Parts(NumParts); |
1 |
2098 |
SmallVector Parts(NumParts); |
1 |
| 2099 |
getCopyToParts(DAG, getCurSDLoc(), |
2 |
2099 |
getCopyToParts(DAG, getCurSDLoc(), |
2 |
| 2100 |
SDValue(RetOp.getNode(), RetOp.getResNo() + j), |
1 |
2100 |
SDValue(RetOp.getNode(), RetOp.getResNo() + j), |
1 |
| 2101 |
&Parts[0], NumParts, PartVT, &I, CC, ExtendKind); |
1 |
2101 |
&Parts[0], NumParts, PartVT, &I, CC, ExtendKind); |
1 |
| 2102 |
|
--- |
2102 |
|
--- |
| 2103 |
// 'inreg' on function refers to return value |
--- |
2103 |
// 'inreg' on function refers to return value |
--- |
| 2104 |
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); |
1 |
2104 |
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); |
1 |
| 2105 |
if (RetInReg) |
1 |
2105 |
if (RetInReg) |
1 |
| 2106 |
Flags.setInReg(); |
0 |
2106 |
Flags.setInReg(); |
0 |
| 2107 |
|
--- |
2107 |
|
--- |
| 2108 |
if (I.getOperand(0)->getType()->isPointerTy()) { |
1 |
2108 |
if (I.getOperand(0)->getType()->isPointerTy()) { |
1 |
| 2109 |
Flags.setPointer(); |
0 |
2109 |
Flags.setPointer(); |
0 |
| 2110 |
Flags.setPointerAddrSpace( |
0 |
2110 |
Flags.setPointerAddrSpace( |
0 |
| 2111 |
cast(I.getOperand(0)->getType())->getAddressSpace()); |
--- |
2111 |
cast(I.getOperand(0)->getType())->getAddressSpace()); |
--- |
| 2112 |
} |
--- |
2112 |
} |
--- |
| 2113 |
|
--- |
2113 |
|
--- |
| 2114 |
if (NeedsRegBlock) { |
1 |
2114 |
if (NeedsRegBlock) { |
1 |
| 2115 |
Flags.setInConsecutiveRegs(); |
0 |
2115 |
Flags.setInConsecutiveRegs(); |
0 |
| 2116 |
if (j == NumValues - 1) |
0 |
2116 |
if (j == NumValues - 1) |
0 |
| 2117 |
Flags.setInConsecutiveRegsLast(); |
0 |
2117 |
Flags.setInConsecutiveRegsLast(); |
0 |
| 2118 |
} |
--- |
2118 |
} |
--- |
| 2119 |
|
--- |
2119 |
|
--- |
| 2120 |
// Propagate extension type if any |
--- |
2120 |
// Propagate extension type if any |
--- |
| 2121 |
if (ExtendKind == ISD::SIGN_EXTEND) |
1 |
2121 |
if (ExtendKind == ISD::SIGN_EXTEND) |
1 |
| 2122 |
Flags.setSExt(); |
0 |
2122 |
Flags.setSExt(); |
0 |
| 2123 |
else if (ExtendKind == ISD::ZERO_EXTEND) |
1 |
2123 |
else if (ExtendKind == ISD::ZERO_EXTEND) |
1 |
| 2124 |
Flags.setZExt(); |
0 |
2124 |
Flags.setZExt(); |
0 |
| 2125 |
|
--- |
2125 |
|
--- |
| 2126 |
for (unsigned i = 0; i < NumParts; ++i) { |
2 |
2126 |
for (unsigned i = 0; i < NumParts; ++i) { |
2 |
| 2127 |
Outs.push_back(ISD::OutputArg(Flags, |
1 |
2127 |
Outs.push_back(ISD::OutputArg(Flags, |
1 |
| 2128 |
Parts[i].getValueType().getSimpleVT(), |
1 |
2128 |
Parts[i].getValueType().getSimpleVT(), |
1 |
| 2129 |
VT, /*isfixed=*/true, 0, 0)); |
--- |
2129 |
VT, /*isfixed=*/true, 0, 0)); |
--- |
| 2130 |
OutVals.push_back(Parts[i]); |
1 |
2130 |
OutVals.push_back(Parts[i]); |
1 |
| 2131 |
} |
--- |
2131 |
} |
--- |
| 2132 |
} |
1 |
2132 |
} |
1 |
| 2133 |
} |
--- |
2133 |
} |
--- |
| 2134 |
} |
1 |
2134 |
} |
1 |
| 2135 |
|
--- |
2135 |
|
--- |
| 2136 |
// Push in swifterror virtual register as the last element of Outs. This makes |
--- |
2136 |
// Push in swifterror virtual register as the last element of Outs. This makes |
--- |
| 2137 |
// sure swifterror virtual register will be returned in the swifterror |
--- |
2137 |
// sure swifterror virtual register will be returned in the swifterror |
--- |
| 2138 |
// physical register. |
--- |
2138 |
// physical register. |
--- |
| 2139 |
const Function *F = I.getParent()->getParent(); |
1 |
2139 |
const Function *F = I.getParent()->getParent(); |
1 |
| 2140 |
if (TLI.supportSwiftError() && |
1 |
2140 |
if (TLI.supportSwiftError() && |
1 |
| 2141 |
F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) { |
1 |
2141 |
F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) { |
1 |
| 2142 |
assert(SwiftError.getFunctionArg() && "Need a swift error argument"); |
0 |
2142 |
assert(SwiftError.getFunctionArg() && "Need a swift error argument"); |
0 |
| 2143 |
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); |
0 |
2143 |
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); |
0 |
| 2144 |
Flags.setSwiftError(); |
0 |
2144 |
Flags.setSwiftError(); |
0 |
| 2145 |
Outs.push_back(ISD::OutputArg( |
0 |
2145 |
Outs.push_back(ISD::OutputArg( |
0 |
| 2146 |
Flags, /*vt=*/TLI.getPointerTy(DL), /*argvt=*/EVT(TLI.getPointerTy(DL)), |
0 |
2146 |
Flags, /*vt=*/TLI.getPointerTy(DL), /*argvt=*/EVT(TLI.getPointerTy(DL)), |
0 |
| 2147 |
/*isfixed=*/true, /*origidx=*/1, /*partOffs=*/0)); |
--- |
2147 |
/*isfixed=*/true, /*origidx=*/1, /*partOffs=*/0)); |
--- |
| 2148 |
// Create SDNode for the swifterror virtual register. |
--- |
2148 |
// Create SDNode for the swifterror virtual register. |
--- |
| 2149 |
OutVals.push_back( |
0 |
2149 |
OutVals.push_back( |
0 |
| 2150 |
DAG.getRegister(SwiftError.getOrCreateVRegUseAt( |
0 |
2150 |
DAG.getRegister(SwiftError.getOrCreateVRegUseAt( |
0 |
| 2151 |
&I, FuncInfo.MBB, SwiftError.getFunctionArg()), |
0 |
2151 |
&I, FuncInfo.MBB, SwiftError.getFunctionArg()), |
0 |
| 2152 |
EVT(TLI.getPointerTy(DL)))); |
0 |
2152 |
EVT(TLI.getPointerTy(DL)))); |
0 |
| 2153 |
} |
--- |
2153 |
} |
--- |
| 2154 |
|
--- |
2154 |
|
--- |
| 2155 |
bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg(); |
1 |
2155 |
bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg(); |
1 |
| 2156 |
CallingConv::ID CallConv = |
--- |
2156 |
CallingConv::ID CallConv = |
--- |
| 2157 |
DAG.getMachineFunction().getFunction().getCallingConv(); |
1 |
2157 |
DAG.getMachineFunction().getFunction().getCallingConv(); |
1 |
| 2158 |
Chain = DAG.getTargetLoweringInfo().LowerReturn( |
2 |
2158 |
Chain = DAG.getTargetLoweringInfo().LowerReturn( |
2 |
| 2159 |
Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG); |
2 |
2159 |
Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG); |
2 |
| 2160 |
|
--- |
2160 |
|
--- |
| 2161 |
// Verify that the target's LowerReturn behaved as expected. |
--- |
2161 |
// Verify that the target's LowerReturn behaved as expected. |
--- |
| 2162 |
assert(Chain.getNode() && Chain.getValueType() == MVT::Other && |
1 |
2162 |
assert(Chain.getNode() && Chain.getValueType() == MVT::Other && |
1 |
| 2163 |
"LowerReturn didn't return a valid chain!"); |
--- |
2163 |
"LowerReturn didn't return a valid chain!"); |
--- |
| 2164 |
|
--- |
2164 |
|
--- |
| 2165 |
// Update the DAG with the new chain value resulting from return lowering. |
--- |
2165 |
// Update the DAG with the new chain value resulting from return lowering. |
--- |
| 2166 |
DAG.setRoot(Chain); |
1 |
2166 |
DAG.setRoot(Chain); |
1 |
| 2167 |
} |
1 |
2167 |
} |
1 |
| 2168 |
|
--- |
2168 |
|
--- |
| 2169 |
/// CopyToExportRegsIfNeeded - If the given value has virtual registers |
--- |
2169 |
/// CopyToExportRegsIfNeeded - If the given value has virtual registers |
--- |
| 2170 |
/// created for it, emit nodes to copy the value into the virtual |
--- |
2170 |
/// created for it, emit nodes to copy the value into the virtual |
--- |
| 2171 |
/// registers. |
--- |
2171 |
/// registers. |
--- |
| 2172 |
void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { |
16 |
2172 |
void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { |
13 |
| 2173 |
// Skip empty types |
--- |
2173 |
// Skip empty types |
--- |
| 2174 |
if (V->getType()->isEmptyTy()) |
16 |
2174 |
if (V->getType()->isEmptyTy()) |
13 |
| 2175 |
return; |
0 |
2175 |
return; |
0 |
| 2176 |
|
--- |
2176 |
|
--- |
| 2177 |
DenseMap::iterator VMI = FuncInfo.ValueMap.find(V); |
16 |
2177 |
DenseMap::iterator VMI = FuncInfo.ValueMap.find(V); |
13 |
| 2178 |
if (VMI != FuncInfo.ValueMap.end()) { |
16 |
2178 |
if (VMI != FuncInfo.ValueMap.end()) { |
13 |
| 2179 |
assert((!V->use_empty() || isa(V)) && |
0 |
2179 |
assert((!V->use_empty() || isa(V)) && |
0 |
| 2180 |
"Unused value assigned virtual registers!"); |
--- |
2180 |
"Unused value assigned virtual registers!"); |
--- |
| 2181 |
CopyValueToVirtualRegister(V, VMI->second); |
0 |
2181 |
CopyValueToVirtualRegister(V, VMI->second); |
0 |
| 2182 |
} |
--- |
2182 |
} |
--- |
| 2183 |
} |
--- |
2183 |
} |
--- |
| 2184 |
|
--- |
2184 |
|
--- |
| 2185 |
/// ExportFromCurrentBlock - If this condition isn't known to be exported from |
--- |
2185 |
/// ExportFromCurrentBlock - If this condition isn't known to be exported from |
--- |
| 2186 |
/// the current basic block, add it to ValueMap now so that we'll get a |
--- |
2186 |
/// the current basic block, add it to ValueMap now so that we'll get a |
--- |
| 2187 |
/// CopyTo/FromReg. |
--- |
2187 |
/// CopyTo/FromReg. |
--- |
| 2188 |
void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { |
0 |
2188 |
void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { |
0 |
| 2189 |
// No need to export constants. |
--- |
2189 |
// No need to export constants. |
--- |
| 2190 |
if (!isa(V) && !isa(V)) return; |
0 |
2190 |
if (!isa(V) && !isa(V)) return; |
0 |
| 2191 |
|
--- |
2191 |
|
--- |
| 2192 |
// Already exported? |
--- |
2192 |
// Already exported? |
--- |
| 2193 |
if (FuncInfo.isExportedInst(V)) return; |
0 |
2193 |
if (FuncInfo.isExportedInst(V)) return; |
0 |
| 2194 |
|
--- |
2194 |
|
--- |
| 2195 |
Register Reg = FuncInfo.InitializeRegForValue(V); |
0 |
2195 |
Register Reg = FuncInfo.InitializeRegForValue(V); |
0 |
| 2196 |
CopyValueToVirtualRegister(V, Reg); |
0 |
2196 |
CopyValueToVirtualRegister(V, Reg); |
0 |
| 2197 |
} |
--- |
2197 |
} |
--- |
| 2198 |
|
--- |
2198 |
|
--- |
| 2199 |
bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, |
0 |
2199 |
bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, |
0 |
| 2200 |
const BasicBlock *FromBB) { |
--- |
2200 |
const BasicBlock *FromBB) { |
--- |
| 2201 |
// The operands of the setcc have to be in this block. We don't know |
--- |
2201 |
// The operands of the setcc have to be in this block. We don't know |
--- |
| 2202 |
// how to export them from some other block. |
--- |
2202 |
// how to export them from some other block. |
--- |
| 2203 |
if (const Instruction *VI = dyn_cast(V)) { |
0 |
2203 |
if (const Instruction *VI = dyn_cast(V)) { |
0 |
| 2204 |
// Can export from current BB. |
--- |
2204 |
// Can export from current BB. |
--- |
| 2205 |
if (VI->getParent() == FromBB) |
0 |
2205 |
if (VI->getParent() == FromBB) |
0 |
| 2206 |
return true; |
0 |
2206 |
return true; |
0 |
| 2207 |
|
--- |
2207 |
|
--- |
| 2208 |
// Is already exported, noop. |
--- |
2208 |
// Is already exported, noop. |
--- |
| 2209 |
return FuncInfo.isExportedInst(V); |
0 |
2209 |
return FuncInfo.isExportedInst(V); |
0 |
| 2210 |
} |
--- |
2210 |
} |
--- |
| 2211 |
|
--- |
2211 |
|
--- |
| 2212 |
// If this is an argument, we can export it if the BB is the entry block or |
--- |
2212 |
// If this is an argument, we can export it if the BB is the entry block or |
--- |
| 2213 |
// if it is already exported. |
--- |
2213 |
// if it is already exported. |
--- |
| 2214 |
if (isa(V)) { |
0 |
2214 |
if (isa(V)) { |
0 |
| 2215 |
if (FromBB->isEntryBlock()) |
0 |
2215 |
if (FromBB->isEntryBlock()) |
0 |
| 2216 |
return true; |
0 |
2216 |
return true; |
0 |
| 2217 |
|
--- |
2217 |
|
--- |
| 2218 |
// Otherwise, can only export this if it is already exported. |
--- |
2218 |
// Otherwise, can only export this if it is already exported. |
--- |
| 2219 |
return FuncInfo.isExportedInst(V); |
0 |
2219 |
return FuncInfo.isExportedInst(V); |
0 |
| 2220 |
} |
--- |
2220 |
} |
--- |
| 2221 |
|
--- |
2221 |
|
--- |
| 2222 |
// Otherwise, constants can always be exported. |
--- |
2222 |
// Otherwise, constants can always be exported. |
--- |
| 2223 |
return true; |
0 |
2223 |
return true; |
0 |
| 2224 |
} |
--- |
2224 |
} |
--- |
| 2225 |
|
--- |
2225 |
|
--- |
| 2226 |
/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. |
--- |
2226 |
/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. |
--- |
| 2227 |
BranchProbability |
--- |
2227 |
BranchProbability |
--- |
| 2228 |
SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src, |
0 |
2228 |
SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src, |
0 |
| 2229 |
const MachineBasicBlock *Dst) const { |
--- |
2229 |
const MachineBasicBlock *Dst) const { |
--- |
| 2230 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
2230 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
| 2231 |
const BasicBlock *SrcBB = Src->getBasicBlock(); |
0 |
2231 |
const BasicBlock *SrcBB = Src->getBasicBlock(); |
0 |
| 2232 |
const BasicBlock *DstBB = Dst->getBasicBlock(); |
0 |
2232 |
const BasicBlock *DstBB = Dst->getBasicBlock(); |
0 |
| 2233 |
if (!BPI) { |
0 |
2233 |
if (!BPI) { |
0 |
| 2234 |
// If BPI is not available, set the default probability as 1 / N, where N is |
--- |
2234 |
// If BPI is not available, set the default probability as 1 / N, where N is |
--- |
| 2235 |
// the number of successors. |
--- |
2235 |
// the number of successors. |
--- |
| 2236 |
auto SuccSize = std::max(succ_size(SrcBB), 1); |
0 |
2236 |
auto SuccSize = std::max(succ_size(SrcBB), 1); |
0 |
| 2237 |
return BranchProbability(1, SuccSize); |
0 |
2237 |
return BranchProbability(1, SuccSize); |
0 |
| 2238 |
} |
--- |
2238 |
} |
--- |
| 2239 |
return BPI->getEdgeProbability(SrcBB, DstBB); |
0 |
2239 |
return BPI->getEdgeProbability(SrcBB, DstBB); |
0 |
| 2240 |
} |
--- |
2240 |
} |
--- |
| 2241 |
|
--- |
2241 |
|
--- |
| 2242 |
void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src, |
2 |
2242 |
void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src, |
2 |
| 2243 |
MachineBasicBlock *Dst, |
--- |
2243 |
MachineBasicBlock *Dst, |
--- |
| 2244 |
BranchProbability Prob) { |
--- |
2244 |
BranchProbability Prob) { |
--- |
| 2245 |
if (!FuncInfo.BPI) |
2 |
2245 |
if (!FuncInfo.BPI) |
2 |
| 2246 |
Src->addSuccessorWithoutProb(Dst); |
2 |
2246 |
Src->addSuccessorWithoutProb(Dst); |
2 |
| 2247 |
else { |
--- |
2247 |
else { |
--- |
| 2248 |
if (Prob.isUnknown()) |
0 |
2248 |
if (Prob.isUnknown()) |
0 |
| 2249 |
Prob = getEdgeProbability(Src, Dst); |
0 |
2249 |
Prob = getEdgeProbability(Src, Dst); |
0 |
| 2250 |
Src->addSuccessor(Dst, Prob); |
0 |
2250 |
Src->addSuccessor(Dst, Prob); |
0 |
| 2251 |
} |
--- |
2251 |
} |
--- |
| 2252 |
} |
2 |
2252 |
} |
2 |
| 2253 |
|
--- |
2253 |
|
--- |
| 2254 |
static bool InBlock(const Value *V, const BasicBlock *BB) { |
0 |
2254 |
static bool InBlock(const Value *V, const BasicBlock *BB) { |
0 |
| 2255 |
if (const Instruction *I = dyn_cast(V)) |
0 |
2255 |
if (const Instruction *I = dyn_cast(V)) |
0 |
| 2256 |
return I->getParent() == BB; |
0 |
2256 |
return I->getParent() == BB; |
0 |
| 2257 |
return true; |
0 |
2257 |
return true; |
0 |
| 2258 |
} |
--- |
2258 |
} |
--- |
| 2259 |
|
--- |
2259 |
|
--- |
| 2260 |
/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. |
--- |
2260 |
/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. |
--- |
| 2261 |
/// This function emits a branch and is used at the leaves of an OR or an |
--- |
2261 |
/// This function emits a branch and is used at the leaves of an OR or an |
--- |
| 2262 |
/// AND operator tree. |
--- |
2262 |
/// AND operator tree. |
--- |
| 2263 |
void |
--- |
2263 |
void |
--- |
| 2264 |
SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, |
0 |
2264 |
SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, |
0 |
| 2265 |
MachineBasicBlock *TBB, |
--- |
2265 |
MachineBasicBlock *TBB, |
--- |
| 2266 |
MachineBasicBlock *FBB, |
--- |
2266 |
MachineBasicBlock *FBB, |
--- |
| 2267 |
MachineBasicBlock *CurBB, |
--- |
2267 |
MachineBasicBlock *CurBB, |
--- |
| 2268 |
MachineBasicBlock *SwitchBB, |
--- |
2268 |
MachineBasicBlock *SwitchBB, |
--- |
| 2269 |
BranchProbability TProb, |
--- |
2269 |
BranchProbability TProb, |
--- |
| 2270 |
BranchProbability FProb, |
--- |
2270 |
BranchProbability FProb, |
--- |
| 2271 |
bool InvertCond) { |
--- |
2271 |
bool InvertCond) { |
--- |
| 2272 |
const BasicBlock *BB = CurBB->getBasicBlock(); |
0 |
2272 |
const BasicBlock *BB = CurBB->getBasicBlock(); |
0 |
| 2273 |
|
--- |
2273 |
|
--- |
| 2274 |
// If the leaf of the tree is a comparison, merge the condition into |
--- |
2274 |
// If the leaf of the tree is a comparison, merge the condition into |
--- |
| 2275 |
// the caseblock. |
--- |
2275 |
// the caseblock. |
--- |
| 2276 |
if (const CmpInst *BOp = dyn_cast(Cond)) { |
0 |
2276 |
if (const CmpInst *BOp = dyn_cast(Cond)) { |
0 |
| 2277 |
// The operands of the cmp have to be in this block. We don't know |
--- |
2277 |
// The operands of the cmp have to be in this block. We don't know |
--- |
| 2278 |
// how to export them from some other block. If this is the first block |
--- |
2278 |
// how to export them from some other block. If this is the first block |
--- |
| 2279 |
// of the sequence, no exporting is needed. |
--- |
2279 |
// of the sequence, no exporting is needed. |
--- |
| 2280 |
if (CurBB == SwitchBB || |
0 |
2280 |
if (CurBB == SwitchBB || |
0 |
| 2281 |
(isExportableFromCurrentBlock(BOp->getOperand(0), BB) && |
0 |
2281 |
(isExportableFromCurrentBlock(BOp->getOperand(0), BB) && |
0 |
| 2282 |
isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { |
0 |
2282 |
isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { |
0 |
| 2283 |
ISD::CondCode Condition; |
--- |
2283 |
ISD::CondCode Condition; |
--- |
| 2284 |
if (const ICmpInst *IC = dyn_cast(Cond)) { |
0 |
2284 |
if (const ICmpInst *IC = dyn_cast(Cond)) { |
0 |
| 2285 |
ICmpInst::Predicate Pred = |
--- |
2285 |
ICmpInst::Predicate Pred = |
--- |
| 2286 |
InvertCond ? IC->getInversePredicate() : IC->getPredicate(); |
0 |
2286 |
InvertCond ? IC->getInversePredicate() : IC->getPredicate(); |
0 |
| 2287 |
Condition = getICmpCondCode(Pred); |
0 |
2287 |
Condition = getICmpCondCode(Pred); |
0 |
| 2288 |
} else { |
--- |
2288 |
} else { |
--- |
| 2289 |
const FCmpInst *FC = cast(Cond); |
0 |
2289 |
const FCmpInst *FC = cast(Cond); |
0 |
| 2290 |
FCmpInst::Predicate Pred = |
--- |
2290 |
FCmpInst::Predicate Pred = |
--- |
| 2291 |
InvertCond ? FC->getInversePredicate() : FC->getPredicate(); |
0 |
2291 |
InvertCond ? FC->getInversePredicate() : FC->getPredicate(); |
0 |
| 2292 |
Condition = getFCmpCondCode(Pred); |
0 |
2292 |
Condition = getFCmpCondCode(Pred); |
0 |
| 2293 |
if (TM.Options.NoNaNsFPMath) |
0 |
2293 |
if (TM.Options.NoNaNsFPMath) |
0 |
| 2294 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
2294 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
| 2295 |
} |
--- |
2295 |
} |
--- |
| 2296 |
|
--- |
2296 |
|
--- |
| 2297 |
CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr, |
0 |
2297 |
CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr, |
0 |
| 2298 |
TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); |
0 |
2298 |
TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); |
0 |
| 2299 |
SL->SwitchCases.push_back(CB); |
0 |
2299 |
SL->SwitchCases.push_back(CB); |
0 |
| 2300 |
return; |
0 |
2300 |
return; |
0 |
| 2301 |
} |
0 |
2301 |
} |
0 |
| 2302 |
} |
--- |
2302 |
} |
--- |
| 2303 |
|
--- |
2303 |
|
--- |
| 2304 |
// Create a CaseBlock record representing this branch. |
--- |
2304 |
// Create a CaseBlock record representing this branch. |
--- |
| 2305 |
ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ; |
0 |
2305 |
ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ; |
0 |
| 2306 |
CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()), |
0 |
2306 |
CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()), |
0 |
| 2307 |
nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); |
0 |
2307 |
nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); |
0 |
| 2308 |
SL->SwitchCases.push_back(CB); |
0 |
2308 |
SL->SwitchCases.push_back(CB); |
0 |
| 2309 |
} |
0 |
2309 |
} |
0 |
| 2310 |
|
--- |
2310 |
|
--- |
| 2311 |
void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, |
0 |
2311 |
void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, |
0 |
| 2312 |
MachineBasicBlock *TBB, |
--- |
2312 |
MachineBasicBlock *TBB, |
--- |
| 2313 |
MachineBasicBlock *FBB, |
--- |
2313 |
MachineBasicBlock *FBB, |
--- |
| 2314 |
MachineBasicBlock *CurBB, |
--- |
2314 |
MachineBasicBlock *CurBB, |
--- |
| 2315 |
MachineBasicBlock *SwitchBB, |
--- |
2315 |
MachineBasicBlock *SwitchBB, |
--- |
| 2316 |
Instruction::BinaryOps Opc, |
--- |
2316 |
Instruction::BinaryOps Opc, |
--- |
| 2317 |
BranchProbability TProb, |
--- |
2317 |
BranchProbability TProb, |
--- |
| 2318 |
BranchProbability FProb, |
--- |
2318 |
BranchProbability FProb, |
--- |
| 2319 |
bool InvertCond) { |
--- |
2319 |
bool InvertCond) { |
--- |
| 2320 |
// Skip over not part of the tree and remember to invert op and operands at |
--- |
2320 |
// Skip over not part of the tree and remember to invert op and operands at |
--- |
| 2321 |
// next level. |
--- |
2321 |
// next level. |
--- |
| 2322 |
Value *NotCond; |
--- |
2322 |
Value *NotCond; |
--- |
| 2323 |
if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) && |
0 |
2323 |
if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) && |
0 |
| 2324 |
InBlock(NotCond, CurBB->getBasicBlock())) { |
0 |
2324 |
InBlock(NotCond, CurBB->getBasicBlock())) { |
0 |
| 2325 |
FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb, |
0 |
2325 |
FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb, |
0 |
| 2326 |
!InvertCond); |
0 |
2326 |
!InvertCond); |
0 |
| 2327 |
return; |
0 |
2327 |
return; |
0 |
| 2328 |
} |
--- |
2328 |
} |
--- |
| 2329 |
|
--- |
2329 |
|
--- |
| 2330 |
const Instruction *BOp = dyn_cast(Cond); |
0 |
2330 |
const Instruction *BOp = dyn_cast(Cond); |
0 |
| 2331 |
const Value *BOpOp0, *BOpOp1; |
--- |
2331 |
const Value *BOpOp0, *BOpOp1; |
--- |
| 2332 |
// Compute the effective opcode for Cond, taking into account whether it needs |
--- |
2332 |
// Compute the effective opcode for Cond, taking into account whether it needs |
--- |
| 2333 |
// to be inverted, e.g. |
--- |
2333 |
// to be inverted, e.g. |
--- |
| 2334 |
// and (not (or A, B)), C |
--- |
2334 |
// and (not (or A, B)), C |
--- |
| 2335 |
// gets lowered as |
--- |
2335 |
// gets lowered as |
--- |
| 2336 |
// and (and (not A, not B), C) |
--- |
2336 |
// and (and (not A, not B), C) |
--- |
| 2337 |
Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0; |
0 |
2337 |
Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0; |
0 |
| 2338 |
if (BOp) { |
0 |
2338 |
if (BOp) { |
0 |
| 2339 |
BOpc = match(BOp, m_LogicalAnd(m_Value(BOpOp0), m_Value(BOpOp1))) |
0 |
2339 |
BOpc = match(BOp, m_LogicalAnd(m_Value(BOpOp0), m_Value(BOpOp1))) |
0 |
| 2340 |
? Instruction::And |
0 |
2340 |
? Instruction::And |
0 |
| 2341 |
: (match(BOp, m_LogicalOr(m_Value(BOpOp0), m_Value(BOpOp1))) |
0 |
2341 |
: (match(BOp, m_LogicalOr(m_Value(BOpOp0), m_Value(BOpOp1))) |
0 |
| 2342 |
? Instruction::Or |
0 |
2342 |
? Instruction::Or |
0 |
| 2343 |
: (Instruction::BinaryOps)0); |
--- |
2343 |
: (Instruction::BinaryOps)0); |
--- |
| 2344 |
if (InvertCond) { |
0 |
2344 |
if (InvertCond) { |
0 |
| 2345 |
if (BOpc == Instruction::And) |
0 |
2345 |
if (BOpc == Instruction::And) |
0 |
| 2346 |
BOpc = Instruction::Or; |
0 |
2346 |
BOpc = Instruction::Or; |
0 |
| 2347 |
else if (BOpc == Instruction::Or) |
0 |
2347 |
else if (BOpc == Instruction::Or) |
0 |
| 2348 |
BOpc = Instruction::And; |
0 |
2348 |
BOpc = Instruction::And; |
0 |
| 2349 |
} |
--- |
2349 |
} |
--- |
| 2350 |
} |
--- |
2350 |
} |
--- |
| 2351 |
|
--- |
2351 |
|
--- |
| 2352 |
// If this node is not part of the or/and tree, emit it as a branch. |
--- |
2352 |
// If this node is not part of the or/and tree, emit it as a branch. |
--- |
| 2353 |
// Note that all nodes in the tree should have same opcode. |
--- |
2353 |
// Note that all nodes in the tree should have same opcode. |
--- |
| 2354 |
bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse(); |
0 |
2354 |
bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse(); |
0 |
| 2355 |
if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() || |
0 |
2355 |
if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() || |
0 |
| 2356 |
!InBlock(BOpOp0, CurBB->getBasicBlock()) || |
0 |
2356 |
!InBlock(BOpOp0, CurBB->getBasicBlock()) || |
0 |
| 2357 |
!InBlock(BOpOp1, CurBB->getBasicBlock())) { |
0 |
2357 |
!InBlock(BOpOp1, CurBB->getBasicBlock())) { |
0 |
| 2358 |
EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, |
0 |
2358 |
EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, |
0 |
| 2359 |
TProb, FProb, InvertCond); |
--- |
2359 |
TProb, FProb, InvertCond); |
--- |
| 2360 |
return; |
0 |
2360 |
return; |
0 |
| 2361 |
} |
--- |
2361 |
} |
--- |
| 2362 |
|
--- |
2362 |
|
--- |
| 2363 |
// Create TmpBB after CurBB. |
--- |
2363 |
// Create TmpBB after CurBB. |
--- |
| 2364 |
MachineFunction::iterator BBI(CurBB); |
0 |
2364 |
MachineFunction::iterator BBI(CurBB); |
0 |
| 2365 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
2365 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 2366 |
MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); |
0 |
2366 |
MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); |
0 |
| 2367 |
CurBB->getParent()->insert(++BBI, TmpBB); |
0 |
2367 |
CurBB->getParent()->insert(++BBI, TmpBB); |
0 |
| 2368 |
|
--- |
2368 |
|
--- |
| 2369 |
if (Opc == Instruction::Or) { |
0 |
2369 |
if (Opc == Instruction::Or) { |
0 |
| 2370 |
// Codegen X | Y as: |
--- |
2370 |
// Codegen X | Y as: |
--- |
| 2371 |
// BB1: |
--- |
2371 |
// BB1: |
--- |
| 2372 |
// jmp_if_X TBB |
--- |
2372 |
// jmp_if_X TBB |
--- |
| 2373 |
// jmp TmpBB |
--- |
2373 |
// jmp TmpBB |
--- |
| 2374 |
// TmpBB: |
--- |
2374 |
// TmpBB: |
--- |
| 2375 |
// jmp_if_Y TBB |
--- |
2375 |
// jmp_if_Y TBB |
--- |
| 2376 |
// jmp FBB |
--- |
2376 |
// jmp FBB |
--- |
| 2377 |
// |
--- |
2377 |
// |
--- |
| 2378 |
|
--- |
2378 |
|
--- |
| 2379 |
// We have flexibility in setting Prob for BB1 and Prob for TmpBB. |
--- |
2379 |
// We have flexibility in setting Prob for BB1 and Prob for TmpBB. |
--- |
| 2380 |
// The requirement is that |
--- |
2380 |
// The requirement is that |
--- |
| 2381 |
// TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB) |
--- |
2381 |
// TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB) |
--- |
| 2382 |
// = TrueProb for original BB. |
--- |
2382 |
// = TrueProb for original BB. |
--- |
| 2383 |
// Assuming the original probabilities are A and B, one choice is to set |
--- |
2383 |
// Assuming the original probabilities are A and B, one choice is to set |
--- |
| 2384 |
// BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to |
--- |
2384 |
// BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to |
--- |
| 2385 |
// A/(1+B) and 2B/(1+B). This choice assumes that |
--- |
2385 |
// A/(1+B) and 2B/(1+B). This choice assumes that |
--- |
| 2386 |
// TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB. |
--- |
2386 |
// TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB. |
--- |
| 2387 |
// Another choice is to assume TrueProb for BB1 equals to TrueProb for |
--- |
2387 |
// Another choice is to assume TrueProb for BB1 equals to TrueProb for |
--- |
| 2388 |
// TmpBB, but the math is more complicated. |
--- |
2388 |
// TmpBB, but the math is more complicated. |
--- |
| 2389 |
|
--- |
2389 |
|
--- |
| 2390 |
auto NewTrueProb = TProb / 2; |
0 |
2390 |
auto NewTrueProb = TProb / 2; |
0 |
| 2391 |
auto NewFalseProb = TProb / 2 + FProb; |
0 |
2391 |
auto NewFalseProb = TProb / 2 + FProb; |
0 |
| 2392 |
// Emit the LHS condition. |
--- |
2392 |
// Emit the LHS condition. |
--- |
| 2393 |
FindMergedConditions(BOpOp0, TBB, TmpBB, CurBB, SwitchBB, Opc, NewTrueProb, |
0 |
2393 |
FindMergedConditions(BOpOp0, TBB, TmpBB, CurBB, SwitchBB, Opc, NewTrueProb, |
0 |
| 2394 |
NewFalseProb, InvertCond); |
--- |
2394 |
NewFalseProb, InvertCond); |
--- |
| 2395 |
|
--- |
2395 |
|
--- |
| 2396 |
// Normalize A/2 and B to get A/(1+B) and 2B/(1+B). |
--- |
2396 |
// Normalize A/2 and B to get A/(1+B) and 2B/(1+B). |
--- |
| 2397 |
SmallVector Probs{TProb / 2, FProb}; |
0 |
2397 |
SmallVector Probs{TProb / 2, FProb}; |
0 |
| 2398 |
BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); |
0 |
2398 |
BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); |
0 |
| 2399 |
// Emit the RHS condition into TmpBB. |
--- |
2399 |
// Emit the RHS condition into TmpBB. |
--- |
| 2400 |
FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0], |
0 |
2400 |
FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0], |
0 |
| 2401 |
Probs[1], InvertCond); |
0 |
2401 |
Probs[1], InvertCond); |
0 |
| 2402 |
} else { |
0 |
2402 |
} else { |
0 |
| 2403 |
assert(Opc == Instruction::And && "Unknown merge op!"); |
0 |
2403 |
assert(Opc == Instruction::And && "Unknown merge op!"); |
0 |
| 2404 |
// Codegen X & Y as: |
--- |
2404 |
// Codegen X & Y as: |
--- |
| 2405 |
// BB1: |
--- |
2405 |
// BB1: |
--- |
| 2406 |
// jmp_if_X TmpBB |
--- |
2406 |
// jmp_if_X TmpBB |
--- |
| 2407 |
// jmp FBB |
--- |
2407 |
// jmp FBB |
--- |
| 2408 |
// TmpBB: |
--- |
2408 |
// TmpBB: |
--- |
| 2409 |
// jmp_if_Y TBB |
--- |
2409 |
// jmp_if_Y TBB |
--- |
| 2410 |
// jmp FBB |
--- |
2410 |
// jmp FBB |
--- |
| 2411 |
// |
--- |
2411 |
// |
--- |
| 2412 |
// This requires creation of TmpBB after CurBB. |
--- |
2412 |
// This requires creation of TmpBB after CurBB. |
--- |
| 2413 |
|
--- |
2413 |
|
--- |
| 2414 |
// We have flexibility in setting Prob for BB1 and Prob for TmpBB. |
--- |
2414 |
// We have flexibility in setting Prob for BB1 and Prob for TmpBB. |
--- |
| 2415 |
// The requirement is that |
--- |
2415 |
// The requirement is that |
--- |
| 2416 |
// FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB) |
--- |
2416 |
// FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB) |
--- |
| 2417 |
// = FalseProb for original BB. |
--- |
2417 |
// = FalseProb for original BB. |
--- |
| 2418 |
// Assuming the original probabilities are A and B, one choice is to set |
--- |
2418 |
// Assuming the original probabilities are A and B, one choice is to set |
--- |
| 2419 |
// BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to |
--- |
2419 |
// BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to |
--- |
| 2420 |
// 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 == |
--- |
2420 |
// 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 == |
--- |
| 2421 |
// TrueProb for BB1 * FalseProb for TmpBB. |
--- |
2421 |
// TrueProb for BB1 * FalseProb for TmpBB. |
--- |
| 2422 |
|
--- |
2422 |
|
--- |
| 2423 |
auto NewTrueProb = TProb + FProb / 2; |
0 |
2423 |
auto NewTrueProb = TProb + FProb / 2; |
0 |
| 2424 |
auto NewFalseProb = FProb / 2; |
0 |
2424 |
auto NewFalseProb = FProb / 2; |
0 |
| 2425 |
// Emit the LHS condition. |
--- |
2425 |
// Emit the LHS condition. |
--- |
| 2426 |
FindMergedConditions(BOpOp0, TmpBB, FBB, CurBB, SwitchBB, Opc, NewTrueProb, |
0 |
2426 |
FindMergedConditions(BOpOp0, TmpBB, FBB, CurBB, SwitchBB, Opc, NewTrueProb, |
0 |
| 2427 |
NewFalseProb, InvertCond); |
--- |
2427 |
NewFalseProb, InvertCond); |
--- |
| 2428 |
|
--- |
2428 |
|
--- |
| 2429 |
// Normalize A and B/2 to get 2A/(1+A) and B/(1+A). |
--- |
2429 |
// Normalize A and B/2 to get 2A/(1+A) and B/(1+A). |
--- |
| 2430 |
SmallVector Probs{TProb, FProb / 2}; |
0 |
2430 |
SmallVector Probs{TProb, FProb / 2}; |
0 |
| 2431 |
BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); |
0 |
2431 |
BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); |
0 |
| 2432 |
// Emit the RHS condition into TmpBB. |
--- |
2432 |
// Emit the RHS condition into TmpBB. |
--- |
| 2433 |
FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0], |
0 |
2433 |
FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0], |
0 |
| 2434 |
Probs[1], InvertCond); |
0 |
2434 |
Probs[1], InvertCond); |
0 |
| 2435 |
} |
0 |
2435 |
} |
0 |
| 2436 |
} |
--- |
2436 |
} |
--- |
| 2437 |
|
--- |
2437 |
|
--- |
| 2438 |
/// If the set of cases should be emitted as a series of branches, return true. |
--- |
2438 |
/// If the set of cases should be emitted as a series of branches, return true. |
--- |
| 2439 |
/// If we should emit this as a bunch of and/or'd together conditions, return |
--- |
2439 |
/// If we should emit this as a bunch of and/or'd together conditions, return |
--- |
| 2440 |
/// false. |
--- |
2440 |
/// false. |
--- |
| 2441 |
bool |
--- |
2441 |
bool |
--- |
| 2442 |
SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector &Cases) { |
0 |
2442 |
SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector &Cases) { |
0 |
| 2443 |
if (Cases.size() != 2) return true; |
0 |
2443 |
if (Cases.size() != 2) return true; |
0 |
| 2444 |
|
--- |
2444 |
|
--- |
| 2445 |
// If this is two comparisons of the same values or'd or and'd together, they |
--- |
2445 |
// If this is two comparisons of the same values or'd or and'd together, they |
--- |
| 2446 |
// will get folded into a single comparison, so don't emit two blocks. |
--- |
2446 |
// will get folded into a single comparison, so don't emit two blocks. |
--- |
| 2447 |
if ((Cases[0].CmpLHS == Cases[1].CmpLHS && |
0 |
2447 |
if ((Cases[0].CmpLHS == Cases[1].CmpLHS && |
0 |
| 2448 |
Cases[0].CmpRHS == Cases[1].CmpRHS) || |
0 |
2448 |
Cases[0].CmpRHS == Cases[1].CmpRHS) || |
0 |
| 2449 |
(Cases[0].CmpRHS == Cases[1].CmpLHS && |
0 |
2449 |
(Cases[0].CmpRHS == Cases[1].CmpLHS && |
0 |
| 2450 |
Cases[0].CmpLHS == Cases[1].CmpRHS)) { |
0 |
2450 |
Cases[0].CmpLHS == Cases[1].CmpRHS)) { |
0 |
| 2451 |
return false; |
0 |
2451 |
return false; |
0 |
| 2452 |
} |
--- |
2452 |
} |
--- |
| 2453 |
|
--- |
2453 |
|
--- |
| 2454 |
// Handle: (X != null) | (Y != null) --> (X|Y) != 0 |
--- |
2454 |
// Handle: (X != null) | (Y != null) --> (X|Y) != 0 |
--- |
| 2455 |
// Handle: (X == null) & (Y == null) --> (X|Y) == 0 |
--- |
2455 |
// Handle: (X == null) & (Y == null) --> (X|Y) == 0 |
--- |
| 2456 |
if (Cases[0].CmpRHS == Cases[1].CmpRHS && |
0 |
2456 |
if (Cases[0].CmpRHS == Cases[1].CmpRHS && |
0 |
| 2457 |
Cases[0].CC == Cases[1].CC && |
0 |
2457 |
Cases[0].CC == Cases[1].CC && |
0 |
| 2458 |
isa(Cases[0].CmpRHS) && |
0 |
2458 |
isa(Cases[0].CmpRHS) && |
0 |
| 2459 |
cast(Cases[0].CmpRHS)->isNullValue()) { |
0 |
2459 |
cast(Cases[0].CmpRHS)->isNullValue()) { |
0 |
| 2460 |
if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) |
0 |
2460 |
if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) |
0 |
| 2461 |
return false; |
0 |
2461 |
return false; |
0 |
| 2462 |
if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) |
0 |
2462 |
if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) |
0 |
| 2463 |
return false; |
0 |
2463 |
return false; |
0 |
| 2464 |
} |
--- |
2464 |
} |
--- |
| 2465 |
|
--- |
2465 |
|
--- |
| 2466 |
return true; |
0 |
2466 |
return true; |
0 |
| 2467 |
} |
--- |
2467 |
} |
--- |
| 2468 |
|
--- |
2468 |
|
--- |
| 2469 |
void SelectionDAGBuilder::visitBr(const BranchInst &I) { |
3 |
2469 |
void SelectionDAGBuilder::visitBr(const BranchInst &I) { |
3 |
| 2470 |
MachineBasicBlock *BrMBB = FuncInfo.MBB; |
3 |
2470 |
MachineBasicBlock *BrMBB = FuncInfo.MBB; |
3 |
| 2471 |
|
--- |
2471 |
|
--- |
| 2472 |
// Update machine-CFG edges. |
--- |
2472 |
// Update machine-CFG edges. |
--- |
| 2473 |
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; |
3 |
2473 |
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; |
3 |
| 2474 |
|
--- |
2474 |
|
--- |
| 2475 |
if (I.isUnconditional()) { |
3 |
2475 |
if (I.isUnconditional()) { |
3 |
| 2476 |
// Update machine-CFG edges. |
--- |
2476 |
// Update machine-CFG edges. |
--- |
| 2477 |
BrMBB->addSuccessor(Succ0MBB); |
2 |
2477 |
BrMBB->addSuccessor(Succ0MBB); |
2 |
| 2478 |
|
--- |
2478 |
|
--- |
| 2479 |
// If this is not a fall-through branch or optimizations are switched off, |
--- |
2479 |
// If this is not a fall-through branch or optimizations are switched off, |
--- |
| 2480 |
// emit the branch. |
--- |
2480 |
// emit the branch. |
--- |
| 2481 |
if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None) { |
2 |
2481 |
if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None) { |
2 |
| 2482 |
auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, |
2 |
2482 |
auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, |
2 |
| 2483 |
getControlRoot(), DAG.getBasicBlock(Succ0MBB)); |
2 |
2483 |
getControlRoot(), DAG.getBasicBlock(Succ0MBB)); |
2 |
| 2484 |
setValue(&I, Br); |
2 |
2484 |
setValue(&I, Br); |
2 |
| 2485 |
DAG.setRoot(Br); |
2 |
2485 |
DAG.setRoot(Br); |
2 |
| 2486 |
} |
--- |
2486 |
} |
--- |
| 2487 |
|
--- |
2487 |
|
--- |
| 2488 |
return; |
2 |
2488 |
return; |
2 |
| 2489 |
} |
--- |
2489 |
} |
--- |
| 2490 |
|
--- |
2490 |
|
--- |
| 2491 |
// If this condition is one of the special cases we handle, do special stuff |
--- |
2491 |
// If this condition is one of the special cases we handle, do special stuff |
--- |
| 2492 |
// now. |
--- |
2492 |
// now. |
--- |
| 2493 |
const Value *CondVal = I.getCondition(); |
1 |
2493 |
const Value *CondVal = I.getCondition(); |
1 |
| 2494 |
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; |
1 |
2494 |
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; |
1 |
| 2495 |
|
--- |
2495 |
|
--- |
| 2496 |
// If this is a series of conditions that are or'd or and'd together, emit |
--- |
2496 |
// If this is a series of conditions that are or'd or and'd together, emit |
--- |
| 2497 |
// this as a sequence of branches instead of setcc's with and/or operations. |
--- |
2497 |
// this as a sequence of branches instead of setcc's with and/or operations. |
--- |
| 2498 |
// As long as jumps are not expensive (exceptions for multi-use logic ops, |
--- |
2498 |
// As long as jumps are not expensive (exceptions for multi-use logic ops, |
--- |
| 2499 |
// unpredictable branches, and vector extracts because those jumps are likely |
--- |
2499 |
// unpredictable branches, and vector extracts because those jumps are likely |
--- |
| 2500 |
// expensive for any target), this should improve performance. |
--- |
2500 |
// expensive for any target), this should improve performance. |
--- |
| 2501 |
// For example, instead of something like: |
--- |
2501 |
// For example, instead of something like: |
--- |
| 2502 |
// cmp A, B |
--- |
2502 |
// cmp A, B |
--- |
| 2503 |
// C = seteq |
--- |
2503 |
// C = seteq |
--- |
| 2504 |
// cmp D, E |
--- |
2504 |
// cmp D, E |
--- |
| 2505 |
// F = setle |
--- |
2505 |
// F = setle |
--- |
| 2506 |
// or C, F |
--- |
2506 |
// or C, F |
--- |
| 2507 |
// jnz foo |
--- |
2507 |
// jnz foo |
--- |
| 2508 |
// Emit: |
--- |
2508 |
// Emit: |
--- |
| 2509 |
// cmp A, B |
--- |
2509 |
// cmp A, B |
--- |
| 2510 |
// je foo |
--- |
2510 |
// je foo |
--- |
| 2511 |
// cmp D, E |
--- |
2511 |
// cmp D, E |
--- |
| 2512 |
// jle foo |
--- |
2512 |
// jle foo |
--- |
| 2513 |
const Instruction *BOp = dyn_cast(CondVal); |
1 |
2513 |
const Instruction *BOp = dyn_cast(CondVal); |
1 |
| 2514 |
if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp && |
3 |
2514 |
if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp && |
3 |
| 2515 |
BOp->hasOneUse() && !I.hasMetadata(LLVMContext::MD_unpredictable)) { |
3 |
2515 |
BOp->hasOneUse() && !I.hasMetadata(LLVMContext::MD_unpredictable)) { |
3 |
| 2516 |
Value *Vec; |
--- |
2516 |
Value *Vec; |
--- |
| 2517 |
const Value *BOp0, *BOp1; |
--- |
2517 |
const Value *BOp0, *BOp1; |
--- |
| 2518 |
Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0; |
1 |
2518 |
Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0; |
1 |
| 2519 |
if (match(BOp, m_LogicalAnd(m_Value(BOp0), m_Value(BOp1)))) |
1 |
2519 |
if (match(BOp, m_LogicalAnd(m_Value(BOp0), m_Value(BOp1)))) |
1 |
| 2520 |
Opcode = Instruction::And; |
0 |
2520 |
Opcode = Instruction::And; |
0 |
| 2521 |
else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1)))) |
1 |
2521 |
else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1)))) |
1 |
| 2522 |
Opcode = Instruction::Or; |
0 |
2522 |
Opcode = Instruction::Or; |
0 |
| 2523 |
|
--- |
2523 |
|
--- |
| 2524 |
if (Opcode && !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) && |
1 |
2524 |
if (Opcode && !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) && |
1 |
| 2525 |
match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value())))) { |
1 |
2525 |
match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value())))) { |
1 |
| 2526 |
FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, Opcode, |
0 |
2526 |
FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, Opcode, |
0 |
| 2527 |
getEdgeProbability(BrMBB, Succ0MBB), |
--- |
2527 |
getEdgeProbability(BrMBB, Succ0MBB), |
--- |
| 2528 |
getEdgeProbability(BrMBB, Succ1MBB), |
--- |
2528 |
getEdgeProbability(BrMBB, Succ1MBB), |
--- |
| 2529 |
/*InvertCond=*/false); |
--- |
2529 |
/*InvertCond=*/false); |
--- |
| 2530 |
// If the compares in later blocks need to use values not currently |
--- |
2530 |
// If the compares in later blocks need to use values not currently |
--- |
| 2531 |
// exported from this block, export them now. This block should always |
--- |
2531 |
// exported from this block, export them now. This block should always |
--- |
| 2532 |
// be the first entry. |
--- |
2532 |
// be the first entry. |
--- |
| 2533 |
assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); |
0 |
2533 |
assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); |
0 |
| 2534 |
|
--- |
2534 |
|
--- |
| 2535 |
// Allow some cases to be rejected. |
--- |
2535 |
// Allow some cases to be rejected. |
--- |
| 2536 |
if (ShouldEmitAsBranches(SL->SwitchCases)) { |
0 |
2536 |
if (ShouldEmitAsBranches(SL->SwitchCases)) { |
0 |
| 2537 |
for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) { |
0 |
2537 |
for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) { |
0 |
| 2538 |
ExportFromCurrentBlock(SL->SwitchCases[i].CmpLHS); |
0 |
2538 |
ExportFromCurrentBlock(SL->SwitchCases[i].CmpLHS); |
0 |
| 2539 |
ExportFromCurrentBlock(SL->SwitchCases[i].CmpRHS); |
0 |
2539 |
ExportFromCurrentBlock(SL->SwitchCases[i].CmpRHS); |
0 |
| 2540 |
} |
--- |
2540 |
} |
--- |
| 2541 |
|
--- |
2541 |
|
--- |
| 2542 |
// Emit the branch for this block. |
--- |
2542 |
// Emit the branch for this block. |
--- |
| 2543 |
visitSwitchCase(SL->SwitchCases[0], BrMBB); |
0 |
2543 |
visitSwitchCase(SL->SwitchCases[0], BrMBB); |
0 |
| 2544 |
SL->SwitchCases.erase(SL->SwitchCases.begin()); |
0 |
2544 |
SL->SwitchCases.erase(SL->SwitchCases.begin()); |
0 |
| 2545 |
return; |
0 |
2545 |
return; |
0 |
| 2546 |
} |
--- |
2546 |
} |
--- |
| 2547 |
|
--- |
2547 |
|
--- |
| 2548 |
// Okay, we decided not to do this, remove any inserted MBB's and clear |
--- |
2548 |
// Okay, we decided not to do this, remove any inserted MBB's and clear |
--- |
| 2549 |
// SwitchCases. |
--- |
2549 |
// SwitchCases. |
--- |
| 2550 |
for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) |
0 |
2550 |
for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) |
0 |
| 2551 |
FuncInfo.MF->erase(SL->SwitchCases[i].ThisBB); |
0 |
2551 |
FuncInfo.MF->erase(SL->SwitchCases[i].ThisBB); |
0 |
| 2552 |
|
--- |
2552 |
|
--- |
| 2553 |
SL->SwitchCases.clear(); |
0 |
2553 |
SL->SwitchCases.clear(); |
0 |
| 2554 |
} |
--- |
2554 |
} |
--- |
| 2555 |
} |
--- |
2555 |
} |
--- |
| 2556 |
|
--- |
2556 |
|
--- |
| 2557 |
// Create a CaseBlock record representing this branch. |
--- |
2557 |
// Create a CaseBlock record representing this branch. |
--- |
| 2558 |
CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), |
1 |
2558 |
CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), |
1 |
| 2559 |
nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc()); |
2 |
2559 |
nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc()); |
2 |
| 2560 |
|
--- |
2560 |
|
--- |
| 2561 |
// Use visitSwitchCase to actually insert the fast branch sequence for this |
--- |
2561 |
// Use visitSwitchCase to actually insert the fast branch sequence for this |
--- |
| 2562 |
// cond branch. |
--- |
2562 |
// cond branch. |
--- |
| 2563 |
visitSwitchCase(CB, BrMBB); |
1 |
2563 |
visitSwitchCase(CB, BrMBB); |
1 |
| 2564 |
} |
1 |
2564 |
} |
1 |
| 2565 |
|
--- |
2565 |
|
--- |
| 2566 |
/// visitSwitchCase - Emits the necessary code to represent a single node in |
--- |
2566 |
/// visitSwitchCase - Emits the necessary code to represent a single node in |
--- |
| 2567 |
/// the binary search tree resulting from lowering a switch instruction. |
--- |
2567 |
/// the binary search tree resulting from lowering a switch instruction. |
--- |
| 2568 |
void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, |
1 |
2568 |
void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, |
1 |
| 2569 |
MachineBasicBlock *SwitchBB) { |
--- |
2569 |
MachineBasicBlock *SwitchBB) { |
--- |
| 2570 |
SDValue Cond; |
1 |
2570 |
SDValue Cond; |
1 |
| 2571 |
SDValue CondLHS = getValue(CB.CmpLHS); |
1 |
2571 |
SDValue CondLHS = getValue(CB.CmpLHS); |
1 |
| 2572 |
SDLoc dl = CB.DL; |
1 |
2572 |
SDLoc dl = CB.DL; |
1 |
| 2573 |
|
--- |
2573 |
|
--- |
| 2574 |
if (CB.CC == ISD::SETTRUE) { |
1 |
2574 |
if (CB.CC == ISD::SETTRUE) { |
1 |
| 2575 |
// Branch or fall through to TrueBB. |
--- |
2575 |
// Branch or fall through to TrueBB. |
--- |
| 2576 |
addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); |
0 |
2576 |
addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); |
0 |
| 2577 |
SwitchBB->normalizeSuccProbs(); |
0 |
2577 |
SwitchBB->normalizeSuccProbs(); |
0 |
| 2578 |
if (CB.TrueBB != NextBlock(SwitchBB)) { |
0 |
2578 |
if (CB.TrueBB != NextBlock(SwitchBB)) { |
0 |
| 2579 |
DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(), |
0 |
2579 |
DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(), |
0 |
| 2580 |
DAG.getBasicBlock(CB.TrueBB))); |
0 |
2580 |
DAG.getBasicBlock(CB.TrueBB))); |
0 |
| 2581 |
} |
--- |
2581 |
} |
--- |
| 2582 |
return; |
0 |
2582 |
return; |
0 |
| 2583 |
} |
--- |
2583 |
} |
--- |
| 2584 |
|
--- |
2584 |
|
--- |
| 2585 |
auto &TLI = DAG.getTargetLoweringInfo(); |
1 |
2585 |
auto &TLI = DAG.getTargetLoweringInfo(); |
1 |
| 2586 |
EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType()); |
1 |
2586 |
EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType()); |
1 |
| 2587 |
|
--- |
2587 |
|
--- |
| 2588 |
// Build the setcc now. |
--- |
2588 |
// Build the setcc now. |
--- |
| 2589 |
if (!CB.CmpMHS) { |
1 |
2589 |
if (!CB.CmpMHS) { |
1 |
| 2590 |
// Fold "(X == true)" to X and "(X == false)" to !X to |
--- |
2590 |
// Fold "(X == true)" to X and "(X == false)" to !X to |
--- |
| 2591 |
// handle common cases produced by branch lowering. |
--- |
2591 |
// handle common cases produced by branch lowering. |
--- |
| 2592 |
if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && |
2 |
2592 |
if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && |
2 |
| 2593 |
CB.CC == ISD::SETEQ) |
1 |
2593 |
CB.CC == ISD::SETEQ) |
1 |
| 2594 |
Cond = CondLHS; |
1 |
2594 |
Cond = CondLHS; |
1 |
| 2595 |
else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && |
0 |
2595 |
else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && |
0 |
| 2596 |
CB.CC == ISD::SETEQ) { |
0 |
2596 |
CB.CC == ISD::SETEQ) { |
0 |
| 2597 |
SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType()); |
0 |
2597 |
SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType()); |
0 |
| 2598 |
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); |
0 |
2598 |
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); |
0 |
| 2599 |
} else { |
--- |
2599 |
} else { |
--- |
| 2600 |
SDValue CondRHS = getValue(CB.CmpRHS); |
0 |
2600 |
SDValue CondRHS = getValue(CB.CmpRHS); |
0 |
| 2601 |
|
--- |
2601 |
|
--- |
| 2602 |
// If a pointer's DAG type is larger than its memory type then the DAG |
--- |
2602 |
// If a pointer's DAG type is larger than its memory type then the DAG |
--- |
| 2603 |
// values are zero-extended. This breaks signed comparisons so truncate |
--- |
2603 |
// values are zero-extended. This breaks signed comparisons so truncate |
--- |
| 2604 |
// back to the underlying type before doing the compare. |
--- |
2604 |
// back to the underlying type before doing the compare. |
--- |
| 2605 |
if (CondLHS.getValueType() != MemVT) { |
0 |
2605 |
if (CondLHS.getValueType() != MemVT) { |
0 |
| 2606 |
CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT); |
0 |
2606 |
CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT); |
0 |
| 2607 |
CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT); |
0 |
2607 |
CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT); |
0 |
| 2608 |
} |
--- |
2608 |
} |
--- |
| 2609 |
Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC); |
0 |
2609 |
Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC); |
0 |
| 2610 |
} |
--- |
2610 |
} |
--- |
| 2611 |
} else { |
--- |
2611 |
} else { |
--- |
| 2612 |
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); |
0 |
2612 |
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); |
0 |
| 2613 |
|
--- |
2613 |
|
--- |
| 2614 |
const APInt& Low = cast(CB.CmpLHS)->getValue(); |
0 |
2614 |
const APInt& Low = cast(CB.CmpLHS)->getValue(); |
0 |
| 2615 |
const APInt& High = cast(CB.CmpRHS)->getValue(); |
0 |
2615 |
const APInt& High = cast(CB.CmpRHS)->getValue(); |
0 |
| 2616 |
|
--- |
2616 |
|
--- |
| 2617 |
SDValue CmpOp = getValue(CB.CmpMHS); |
0 |
2617 |
SDValue CmpOp = getValue(CB.CmpMHS); |
0 |
| 2618 |
EVT VT = CmpOp.getValueType(); |
0 |
2618 |
EVT VT = CmpOp.getValueType(); |
0 |
| 2619 |
|
--- |
2619 |
|
--- |
| 2620 |
if (cast(CB.CmpLHS)->isMinValue(true)) { |
0 |
2620 |
if (cast(CB.CmpLHS)->isMinValue(true)) { |
0 |
| 2621 |
Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT), |
0 |
2621 |
Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT), |
0 |
| 2622 |
ISD::SETLE); |
--- |
2622 |
ISD::SETLE); |
--- |
| 2623 |
} else { |
--- |
2623 |
} else { |
--- |
| 2624 |
SDValue SUB = DAG.getNode(ISD::SUB, dl, |
0 |
2624 |
SDValue SUB = DAG.getNode(ISD::SUB, dl, |
0 |
| 2625 |
VT, CmpOp, DAG.getConstant(Low, dl, VT)); |
0 |
2625 |
VT, CmpOp, DAG.getConstant(Low, dl, VT)); |
0 |
| 2626 |
Cond = DAG.getSetCC(dl, MVT::i1, SUB, |
0 |
2626 |
Cond = DAG.getSetCC(dl, MVT::i1, SUB, |
0 |
| 2627 |
DAG.getConstant(High-Low, dl, VT), ISD::SETULE); |
0 |
2627 |
DAG.getConstant(High-Low, dl, VT), ISD::SETULE); |
0 |
| 2628 |
} |
--- |
2628 |
} |
--- |
| 2629 |
} |
--- |
2629 |
} |
--- |
| 2630 |
|
--- |
2630 |
|
--- |
| 2631 |
// Update successor info |
--- |
2631 |
// Update successor info |
--- |
| 2632 |
addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); |
1 |
2632 |
addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); |
1 |
| 2633 |
// TrueBB and FalseBB are always different unless the incoming IR is |
--- |
2633 |
// TrueBB and FalseBB are always different unless the incoming IR is |
--- |
| 2634 |
// degenerate. This only happens when running llc on weird IR. |
--- |
2634 |
// degenerate. This only happens when running llc on weird IR. |
--- |
| 2635 |
if (CB.TrueBB != CB.FalseBB) |
1 |
2635 |
if (CB.TrueBB != CB.FalseBB) |
1 |
| 2636 |
addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb); |
1 |
2636 |
addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb); |
1 |
| 2637 |
SwitchBB->normalizeSuccProbs(); |
1 |
2637 |
SwitchBB->normalizeSuccProbs(); |
1 |
| 2638 |
|
--- |
2638 |
|
--- |
| 2639 |
// If the lhs block is the next block, invert the condition so that we can |
--- |
2639 |
// If the lhs block is the next block, invert the condition so that we can |
--- |
| 2640 |
// fall through to the lhs instead of the rhs block. |
--- |
2640 |
// fall through to the lhs instead of the rhs block. |
--- |
| 2641 |
if (CB.TrueBB == NextBlock(SwitchBB)) { |
1 |
2641 |
if (CB.TrueBB == NextBlock(SwitchBB)) { |
1 |
| 2642 |
std::swap(CB.TrueBB, CB.FalseBB); |
1 |
2642 |
std::swap(CB.TrueBB, CB.FalseBB); |
1 |
| 2643 |
SDValue True = DAG.getConstant(1, dl, Cond.getValueType()); |
1 |
2643 |
SDValue True = DAG.getConstant(1, dl, Cond.getValueType()); |
1 |
| 2644 |
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); |
1 |
2644 |
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); |
1 |
| 2645 |
} |
--- |
2645 |
} |
--- |
| 2646 |
|
--- |
2646 |
|
--- |
| 2647 |
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, |
1 |
2647 |
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, |
1 |
| 2648 |
MVT::Other, getControlRoot(), Cond, |
--- |
2648 |
MVT::Other, getControlRoot(), Cond, |
--- |
| 2649 |
DAG.getBasicBlock(CB.TrueBB)); |
1 |
2649 |
DAG.getBasicBlock(CB.TrueBB)); |
1 |
| 2650 |
|
--- |
2650 |
|
--- |
| 2651 |
setValue(CurInst, BrCond); |
1 |
2651 |
setValue(CurInst, BrCond); |
1 |
| 2652 |
|
--- |
2652 |
|
--- |
| 2653 |
// Insert the false branch. Do this even if it's a fall through branch, |
--- |
2653 |
// Insert the false branch. Do this even if it's a fall through branch, |
--- |
| 2654 |
// this makes it easier to do DAG optimizations which require inverting |
--- |
2654 |
// this makes it easier to do DAG optimizations which require inverting |
--- |
| 2655 |
// the branch condition. |
--- |
2655 |
// the branch condition. |
--- |
| 2656 |
BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, |
1 |
2656 |
BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, |
1 |
| 2657 |
DAG.getBasicBlock(CB.FalseBB)); |
1 |
2657 |
DAG.getBasicBlock(CB.FalseBB)); |
1 |
| 2658 |
|
--- |
2658 |
|
--- |
| 2659 |
DAG.setRoot(BrCond); |
1 |
2659 |
DAG.setRoot(BrCond); |
1 |
| 2660 |
} |
1 |
2660 |
} |
1 |
| 2661 |
|
--- |
2661 |
|
--- |
| 2662 |
/// visitJumpTable - Emit JumpTable node in the current MBB |
--- |
2662 |
/// visitJumpTable - Emit JumpTable node in the current MBB |
--- |
| 2663 |
void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) { |
0 |
2663 |
void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) { |
0 |
| 2664 |
// Emit the code for the jump table |
--- |
2664 |
// Emit the code for the jump table |
--- |
| 2665 |
assert(JT.Reg != -1U && "Should lower JT Header first!"); |
0 |
2665 |
assert(JT.Reg != -1U && "Should lower JT Header first!"); |
0 |
| 2666 |
EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); |
0 |
2666 |
EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); |
0 |
| 2667 |
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), |
0 |
2667 |
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), |
0 |
| 2668 |
JT.Reg, PTy); |
--- |
2668 |
JT.Reg, PTy); |
--- |
| 2669 |
SDValue Table = DAG.getJumpTable(JT.JTI, PTy); |
0 |
2669 |
SDValue Table = DAG.getJumpTable(JT.JTI, PTy); |
0 |
| 2670 |
SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), |
0 |
2670 |
SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), |
0 |
| 2671 |
MVT::Other, Index.getValue(1), |
--- |
2671 |
MVT::Other, Index.getValue(1), |
--- |
| 2672 |
Table, Index); |
--- |
2672 |
Table, Index); |
--- |
| 2673 |
DAG.setRoot(BrJumpTable); |
0 |
2673 |
DAG.setRoot(BrJumpTable); |
0 |
| 2674 |
} |
0 |
2674 |
} |
0 |
| 2675 |
|
--- |
2675 |
|
--- |
| 2676 |
/// visitJumpTableHeader - This function emits necessary code to produce index |
--- |
2676 |
/// visitJumpTableHeader - This function emits necessary code to produce index |
--- |
| 2677 |
/// in the JumpTable from switch case. |
--- |
2677 |
/// in the JumpTable from switch case. |
--- |
| 2678 |
void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT, |
0 |
2678 |
void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT, |
0 |
| 2679 |
JumpTableHeader &JTH, |
--- |
2679 |
JumpTableHeader &JTH, |
--- |
| 2680 |
MachineBasicBlock *SwitchBB) { |
--- |
2680 |
MachineBasicBlock *SwitchBB) { |
--- |
| 2681 |
SDLoc dl = getCurSDLoc(); |
0 |
2681 |
SDLoc dl = getCurSDLoc(); |
0 |
| 2682 |
|
--- |
2682 |
|
--- |
| 2683 |
// Subtract the lowest switch case value from the value being switched on. |
--- |
2683 |
// Subtract the lowest switch case value from the value being switched on. |
--- |
| 2684 |
SDValue SwitchOp = getValue(JTH.SValue); |
0 |
2684 |
SDValue SwitchOp = getValue(JTH.SValue); |
0 |
| 2685 |
EVT VT = SwitchOp.getValueType(); |
0 |
2685 |
EVT VT = SwitchOp.getValueType(); |
0 |
| 2686 |
SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp, |
0 |
2686 |
SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp, |
0 |
| 2687 |
DAG.getConstant(JTH.First, dl, VT)); |
0 |
2687 |
DAG.getConstant(JTH.First, dl, VT)); |
0 |
| 2688 |
|
--- |
2688 |
|
--- |
| 2689 |
// The SDNode we just created, which holds the value being switched on minus |
--- |
2689 |
// The SDNode we just created, which holds the value being switched on minus |
--- |
| 2690 |
// the smallest case value, needs to be copied to a virtual register so it |
--- |
2690 |
// the smallest case value, needs to be copied to a virtual register so it |
--- |
| 2691 |
// can be used as an index into the jump table in a subsequent basic block. |
--- |
2691 |
// can be used as an index into the jump table in a subsequent basic block. |
--- |
| 2692 |
// This value may be smaller or larger than the target's pointer type, and |
--- |
2692 |
// This value may be smaller or larger than the target's pointer type, and |
--- |
| 2693 |
// therefore require extension or truncating. |
--- |
2693 |
// therefore require extension or truncating. |
--- |
| 2694 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
2694 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 2695 |
SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
2695 |
SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 2696 |
|
--- |
2696 |
|
--- |
| 2697 |
unsigned JumpTableReg = |
--- |
2697 |
unsigned JumpTableReg = |
--- |
| 2698 |
FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout())); |
0 |
2698 |
FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 2699 |
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, |
0 |
2699 |
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, |
0 |
| 2700 |
JumpTableReg, SwitchOp); |
--- |
2700 |
JumpTableReg, SwitchOp); |
--- |
| 2701 |
JT.Reg = JumpTableReg; |
0 |
2701 |
JT.Reg = JumpTableReg; |
0 |
| 2702 |
|
--- |
2702 |
|
--- |
| 2703 |
if (!JTH.FallthroughUnreachable) { |
0 |
2703 |
if (!JTH.FallthroughUnreachable) { |
0 |
| 2704 |
// Emit the range check for the jump table, and branch to the default block |
--- |
2704 |
// Emit the range check for the jump table, and branch to the default block |
--- |
| 2705 |
// for the switch statement if the value being switched on exceeds the |
--- |
2705 |
// for the switch statement if the value being switched on exceeds the |
--- |
| 2706 |
// largest case in the switch. |
--- |
2706 |
// largest case in the switch. |
--- |
| 2707 |
SDValue CMP = DAG.getSetCC( |
0 |
2707 |
SDValue CMP = DAG.getSetCC( |
0 |
| 2708 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), |
0 |
2708 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), |
0 |
| 2709 |
Sub.getValueType()), |
--- |
2709 |
Sub.getValueType()), |
--- |
| 2710 |
Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT); |
0 |
2710 |
Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT); |
0 |
| 2711 |
|
--- |
2711 |
|
--- |
| 2712 |
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, |
0 |
2712 |
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, |
0 |
| 2713 |
MVT::Other, CopyTo, CMP, |
--- |
2713 |
MVT::Other, CopyTo, CMP, |
--- |
| 2714 |
DAG.getBasicBlock(JT.Default)); |
0 |
2714 |
DAG.getBasicBlock(JT.Default)); |
0 |
| 2715 |
|
--- |
2715 |
|
--- |
| 2716 |
// Avoid emitting unnecessary branches to the next block. |
--- |
2716 |
// Avoid emitting unnecessary branches to the next block. |
--- |
| 2717 |
if (JT.MBB != NextBlock(SwitchBB)) |
0 |
2717 |
if (JT.MBB != NextBlock(SwitchBB)) |
0 |
| 2718 |
BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, |
0 |
2718 |
BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, |
0 |
| 2719 |
DAG.getBasicBlock(JT.MBB)); |
0 |
2719 |
DAG.getBasicBlock(JT.MBB)); |
0 |
| 2720 |
|
--- |
2720 |
|
--- |
| 2721 |
DAG.setRoot(BrCond); |
0 |
2721 |
DAG.setRoot(BrCond); |
0 |
| 2722 |
} else { |
--- |
2722 |
} else { |
--- |
| 2723 |
// Avoid emitting unnecessary branches to the next block. |
--- |
2723 |
// Avoid emitting unnecessary branches to the next block. |
--- |
| 2724 |
if (JT.MBB != NextBlock(SwitchBB)) |
0 |
2724 |
if (JT.MBB != NextBlock(SwitchBB)) |
0 |
| 2725 |
DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo, |
0 |
2725 |
DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo, |
0 |
| 2726 |
DAG.getBasicBlock(JT.MBB))); |
0 |
2726 |
DAG.getBasicBlock(JT.MBB))); |
0 |
| 2727 |
else |
--- |
2727 |
else |
--- |
| 2728 |
DAG.setRoot(CopyTo); |
0 |
2728 |
DAG.setRoot(CopyTo); |
0 |
| 2729 |
} |
--- |
2729 |
} |
--- |
| 2730 |
} |
0 |
2730 |
} |
0 |
| 2731 |
|
--- |
2731 |
|
--- |
| 2732 |
/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global |
--- |
2732 |
/// Create a LOAD_STACK_GUARD node, and let it carry the target specific global |
--- |
| 2733 |
/// variable if there exists one. |
--- |
2733 |
/// variable if there exists one. |
--- |
| 2734 |
static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, |
0 |
2734 |
static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, |
0 |
| 2735 |
SDValue &Chain) { |
--- |
2735 |
SDValue &Chain) { |
--- |
| 2736 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
2736 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 2737 |
EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
2737 |
EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
| 2738 |
EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout()); |
0 |
2738 |
EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout()); |
0 |
| 2739 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
2739 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 2740 |
Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent()); |
0 |
2740 |
Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent()); |
0 |
| 2741 |
MachineSDNode *Node = |
--- |
2741 |
MachineSDNode *Node = |
--- |
| 2742 |
DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain); |
0 |
2742 |
DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain); |
0 |
| 2743 |
if (Global) { |
0 |
2743 |
if (Global) { |
0 |
| 2744 |
MachinePointerInfo MPInfo(Global); |
0 |
2744 |
MachinePointerInfo MPInfo(Global); |
0 |
| 2745 |
auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | |
0 |
2745 |
auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | |
0 |
| 2746 |
MachineMemOperand::MODereferenceable; |
--- |
2746 |
MachineMemOperand::MODereferenceable; |
--- |
| 2747 |
MachineMemOperand *MemRef = MF.getMachineMemOperand( |
0 |
2747 |
MachineMemOperand *MemRef = MF.getMachineMemOperand( |
0 |
| 2748 |
MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlign(PtrTy)); |
0 |
2748 |
MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlign(PtrTy)); |
0 |
| 2749 |
DAG.setNodeMemRefs(Node, {MemRef}); |
0 |
2749 |
DAG.setNodeMemRefs(Node, {MemRef}); |
0 |
| 2750 |
} |
--- |
2750 |
} |
--- |
| 2751 |
if (PtrTy != PtrMemTy) |
0 |
2751 |
if (PtrTy != PtrMemTy) |
0 |
| 2752 |
return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy); |
0 |
2752 |
return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy); |
0 |
| 2753 |
return SDValue(Node, 0); |
0 |
2753 |
return SDValue(Node, 0); |
0 |
| 2754 |
} |
--- |
2754 |
} |
--- |
| 2755 |
|
--- |
2755 |
|
--- |
| 2756 |
/// Codegen a new tail for a stack protector check ParentMBB which has had its |
--- |
2756 |
/// Codegen a new tail for a stack protector check ParentMBB which has had its |
--- |
| 2757 |
/// tail spliced into a stack protector check success bb. |
--- |
2757 |
/// tail spliced into a stack protector check success bb. |
--- |
| 2758 |
/// |
--- |
2758 |
/// |
--- |
| 2759 |
/// For a high level explanation of how this fits into the stack protector |
--- |
2759 |
/// For a high level explanation of how this fits into the stack protector |
--- |
| 2760 |
/// generation see the comment on the declaration of class |
--- |
2760 |
/// generation see the comment on the declaration of class |
--- |
| 2761 |
/// StackProtectorDescriptor. |
--- |
2761 |
/// StackProtectorDescriptor. |
--- |
| 2762 |
void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD, |
0 |
2762 |
void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD, |
0 |
| 2763 |
MachineBasicBlock *ParentBB) { |
--- |
2763 |
MachineBasicBlock *ParentBB) { |
--- |
| 2764 |
|
--- |
2764 |
|
--- |
| 2765 |
// First create the loads to the guard/stack slot for the comparison. |
--- |
2765 |
// First create the loads to the guard/stack slot for the comparison. |
--- |
| 2766 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
2766 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 2767 |
EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
2767 |
EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
| 2768 |
EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout()); |
0 |
2768 |
EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout()); |
0 |
| 2769 |
|
--- |
2769 |
|
--- |
| 2770 |
MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo(); |
0 |
2770 |
MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo(); |
0 |
| 2771 |
int FI = MFI.getStackProtectorIndex(); |
0 |
2771 |
int FI = MFI.getStackProtectorIndex(); |
0 |
| 2772 |
|
--- |
2772 |
|
--- |
| 2773 |
SDValue Guard; |
0 |
2773 |
SDValue Guard; |
0 |
| 2774 |
SDLoc dl = getCurSDLoc(); |
0 |
2774 |
SDLoc dl = getCurSDLoc(); |
0 |
| 2775 |
SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy); |
0 |
2775 |
SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy); |
0 |
| 2776 |
const Module &M = *ParentBB->getParent()->getFunction().getParent(); |
0 |
2776 |
const Module &M = *ParentBB->getParent()->getFunction().getParent(); |
0 |
| 2777 |
Align Align = |
--- |
2777 |
Align Align = |
--- |
| 2778 |
DAG.getDataLayout().getPrefTypeAlign(Type::getInt8PtrTy(M.getContext())); |
0 |
2778 |
DAG.getDataLayout().getPrefTypeAlign(Type::getInt8PtrTy(M.getContext())); |
0 |
| 2779 |
|
--- |
2779 |
|
--- |
| 2780 |
// Generate code to load the content of the guard slot. |
--- |
2780 |
// Generate code to load the content of the guard slot. |
--- |
| 2781 |
SDValue GuardVal = DAG.getLoad( |
0 |
2781 |
SDValue GuardVal = DAG.getLoad( |
0 |
| 2782 |
PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr, |
0 |
2782 |
PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr, |
0 |
| 2783 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align, |
0 |
2783 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align, |
0 |
| 2784 |
MachineMemOperand::MOVolatile); |
--- |
2784 |
MachineMemOperand::MOVolatile); |
--- |
| 2785 |
|
--- |
2785 |
|
--- |
| 2786 |
if (TLI.useStackGuardXorFP()) |
0 |
2786 |
if (TLI.useStackGuardXorFP()) |
0 |
| 2787 |
GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl); |
0 |
2787 |
GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl); |
0 |
| 2788 |
|
--- |
2788 |
|
--- |
| 2789 |
// Retrieve guard check function, nullptr if instrumentation is inlined. |
--- |
2789 |
// Retrieve guard check function, nullptr if instrumentation is inlined. |
--- |
| 2790 |
if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) { |
0 |
2790 |
if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) { |
0 |
| 2791 |
// The target provides a guard check function to validate the guard value. |
--- |
2791 |
// The target provides a guard check function to validate the guard value. |
--- |
| 2792 |
// Generate a call to that function with the content of the guard slot as |
--- |
2792 |
// Generate a call to that function with the content of the guard slot as |
--- |
| 2793 |
// argument. |
--- |
2793 |
// argument. |
--- |
| 2794 |
FunctionType *FnTy = GuardCheckFn->getFunctionType(); |
0 |
2794 |
FunctionType *FnTy = GuardCheckFn->getFunctionType(); |
0 |
| 2795 |
assert(FnTy->getNumParams() == 1 && "Invalid function signature"); |
0 |
2795 |
assert(FnTy->getNumParams() == 1 && "Invalid function signature"); |
0 |
| 2796 |
|
--- |
2796 |
|
--- |
| 2797 |
TargetLowering::ArgListTy Args; |
0 |
2797 |
TargetLowering::ArgListTy Args; |
0 |
| 2798 |
TargetLowering::ArgListEntry Entry; |
0 |
2798 |
TargetLowering::ArgListEntry Entry; |
0 |
| 2799 |
Entry.Node = GuardVal; |
0 |
2799 |
Entry.Node = GuardVal; |
0 |
| 2800 |
Entry.Ty = FnTy->getParamType(0); |
0 |
2800 |
Entry.Ty = FnTy->getParamType(0); |
0 |
| 2801 |
if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg)) |
0 |
2801 |
if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg)) |
0 |
| 2802 |
Entry.IsInReg = true; |
0 |
2802 |
Entry.IsInReg = true; |
0 |
| 2803 |
Args.push_back(Entry); |
0 |
2803 |
Args.push_back(Entry); |
0 |
| 2804 |
|
--- |
2804 |
|
--- |
| 2805 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
2805 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
| 2806 |
CLI.setDebugLoc(getCurSDLoc()) |
0 |
2806 |
CLI.setDebugLoc(getCurSDLoc()) |
0 |
| 2807 |
.setChain(DAG.getEntryNode()) |
0 |
2807 |
.setChain(DAG.getEntryNode()) |
0 |
| 2808 |
.setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(), |
0 |
2808 |
.setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(), |
0 |
| 2809 |
getValue(GuardCheckFn), std::move(Args)); |
0 |
2809 |
getValue(GuardCheckFn), std::move(Args)); |
0 |
| 2810 |
|
--- |
2810 |
|
--- |
| 2811 |
std::pair Result = TLI.LowerCallTo(CLI); |
0 |
2811 |
std::pair Result = TLI.LowerCallTo(CLI); |
0 |
| 2812 |
DAG.setRoot(Result.second); |
0 |
2812 |
DAG.setRoot(Result.second); |
0 |
| 2813 |
return; |
0 |
2813 |
return; |
0 |
| 2814 |
} |
0 |
2814 |
} |
0 |
| 2815 |
|
--- |
2815 |
|
--- |
| 2816 |
// If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD. |
--- |
2816 |
// If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD. |
--- |
| 2817 |
// Otherwise, emit a volatile load to retrieve the stack guard value. |
--- |
2817 |
// Otherwise, emit a volatile load to retrieve the stack guard value. |
--- |
| 2818 |
SDValue Chain = DAG.getEntryNode(); |
0 |
2818 |
SDValue Chain = DAG.getEntryNode(); |
0 |
| 2819 |
if (TLI.useLoadStackGuardNode()) { |
0 |
2819 |
if (TLI.useLoadStackGuardNode()) { |
0 |
| 2820 |
Guard = getLoadStackGuard(DAG, dl, Chain); |
0 |
2820 |
Guard = getLoadStackGuard(DAG, dl, Chain); |
0 |
| 2821 |
} else { |
--- |
2821 |
} else { |
--- |
| 2822 |
const Value *IRGuard = TLI.getSDagStackGuard(M); |
0 |
2822 |
const Value *IRGuard = TLI.getSDagStackGuard(M); |
0 |
| 2823 |
SDValue GuardPtr = getValue(IRGuard); |
0 |
2823 |
SDValue GuardPtr = getValue(IRGuard); |
0 |
| 2824 |
|
--- |
2824 |
|
--- |
| 2825 |
Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr, |
0 |
2825 |
Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr, |
0 |
| 2826 |
MachinePointerInfo(IRGuard, 0), Align, |
--- |
2826 |
MachinePointerInfo(IRGuard, 0), Align, |
--- |
| 2827 |
MachineMemOperand::MOVolatile); |
--- |
2827 |
MachineMemOperand::MOVolatile); |
--- |
| 2828 |
} |
--- |
2828 |
} |
--- |
| 2829 |
|
--- |
2829 |
|
--- |
| 2830 |
// Perform the comparison via a getsetcc. |
--- |
2830 |
// Perform the comparison via a getsetcc. |
--- |
| 2831 |
SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(), |
0 |
2831 |
SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(), |
0 |
| 2832 |
*DAG.getContext(), |
0 |
2832 |
*DAG.getContext(), |
0 |
| 2833 |
Guard.getValueType()), |
--- |
2833 |
Guard.getValueType()), |
--- |
| 2834 |
Guard, GuardVal, ISD::SETNE); |
--- |
2834 |
Guard, GuardVal, ISD::SETNE); |
--- |
| 2835 |
|
--- |
2835 |
|
--- |
| 2836 |
// If the guard/stackslot do not equal, branch to failure MBB. |
--- |
2836 |
// If the guard/stackslot do not equal, branch to failure MBB. |
--- |
| 2837 |
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, |
0 |
2837 |
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, |
0 |
| 2838 |
MVT::Other, GuardVal.getOperand(0), |
0 |
2838 |
MVT::Other, GuardVal.getOperand(0), |
0 |
| 2839 |
Cmp, DAG.getBasicBlock(SPD.getFailureMBB())); |
0 |
2839 |
Cmp, DAG.getBasicBlock(SPD.getFailureMBB())); |
0 |
| 2840 |
// Otherwise branch to success MBB. |
--- |
2840 |
// Otherwise branch to success MBB. |
--- |
| 2841 |
SDValue Br = DAG.getNode(ISD::BR, dl, |
0 |
2841 |
SDValue Br = DAG.getNode(ISD::BR, dl, |
0 |
| 2842 |
MVT::Other, BrCond, |
--- |
2842 |
MVT::Other, BrCond, |
--- |
| 2843 |
DAG.getBasicBlock(SPD.getSuccessMBB())); |
0 |
2843 |
DAG.getBasicBlock(SPD.getSuccessMBB())); |
0 |
| 2844 |
|
--- |
2844 |
|
--- |
| 2845 |
DAG.setRoot(Br); |
0 |
2845 |
DAG.setRoot(Br); |
0 |
| 2846 |
} |
0 |
2846 |
} |
0 |
| 2847 |
|
--- |
2847 |
|
--- |
| 2848 |
/// Codegen the failure basic block for a stack protector check. |
--- |
2848 |
/// Codegen the failure basic block for a stack protector check. |
--- |
| 2849 |
/// |
--- |
2849 |
/// |
--- |
| 2850 |
/// A failure stack protector machine basic block consists simply of a call to |
--- |
2850 |
/// A failure stack protector machine basic block consists simply of a call to |
--- |
| 2851 |
/// __stack_chk_fail(). |
--- |
2851 |
/// __stack_chk_fail(). |
--- |
| 2852 |
/// |
--- |
2852 |
/// |
--- |
| 2853 |
/// For a high level explanation of how this fits into the stack protector |
--- |
2853 |
/// For a high level explanation of how this fits into the stack protector |
--- |
| 2854 |
/// generation see the comment on the declaration of class |
--- |
2854 |
/// generation see the comment on the declaration of class |
--- |
| 2855 |
/// StackProtectorDescriptor. |
--- |
2855 |
/// StackProtectorDescriptor. |
--- |
| 2856 |
void |
--- |
2856 |
void |
--- |
| 2857 |
SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) { |
0 |
2857 |
SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) { |
0 |
| 2858 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
2858 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 2859 |
TargetLowering::MakeLibCallOptions CallOptions; |
0 |
2859 |
TargetLowering::MakeLibCallOptions CallOptions; |
0 |
| 2860 |
CallOptions.setDiscardResult(true); |
0 |
2860 |
CallOptions.setDiscardResult(true); |
0 |
| 2861 |
SDValue Chain = |
--- |
2861 |
SDValue Chain = |
--- |
| 2862 |
TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid, |
0 |
2862 |
TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid, |
0 |
| 2863 |
std::nullopt, CallOptions, getCurSDLoc()) |
0 |
2863 |
std::nullopt, CallOptions, getCurSDLoc()) |
0 |
| 2864 |
.second; |
0 |
2864 |
.second; |
0 |
| 2865 |
// On PS4/PS5, the "return address" must still be within the calling |
--- |
2865 |
// On PS4/PS5, the "return address" must still be within the calling |
--- |
| 2866 |
// function, even if it's at the very end, so emit an explicit TRAP here. |
--- |
2866 |
// function, even if it's at the very end, so emit an explicit TRAP here. |
--- |
| 2867 |
// Passing 'true' for doesNotReturn above won't generate the trap for us. |
--- |
2867 |
// Passing 'true' for doesNotReturn above won't generate the trap for us. |
--- |
| 2868 |
if (TM.getTargetTriple().isPS()) |
0 |
2868 |
if (TM.getTargetTriple().isPS()) |
0 |
| 2869 |
Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain); |
0 |
2869 |
Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain); |
0 |
| 2870 |
// WebAssembly needs an unreachable instruction after a non-returning call, |
--- |
2870 |
// WebAssembly needs an unreachable instruction after a non-returning call, |
--- |
| 2871 |
// because the function return type can be different from __stack_chk_fail's |
--- |
2871 |
// because the function return type can be different from __stack_chk_fail's |
--- |
| 2872 |
// return type (void). |
--- |
2872 |
// return type (void). |
--- |
| 2873 |
if (TM.getTargetTriple().isWasm()) |
0 |
2873 |
if (TM.getTargetTriple().isWasm()) |
0 |
| 2874 |
Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain); |
0 |
2874 |
Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain); |
0 |
| 2875 |
|
--- |
2875 |
|
--- |
| 2876 |
DAG.setRoot(Chain); |
0 |
2876 |
DAG.setRoot(Chain); |
0 |
| 2877 |
} |
0 |
2877 |
} |
0 |
| 2878 |
|
--- |
2878 |
|
--- |
| 2879 |
/// visitBitTestHeader - This function emits necessary code to produce value |
--- |
2879 |
/// visitBitTestHeader - This function emits necessary code to produce value |
--- |
| 2880 |
/// suitable for "bit tests" |
--- |
2880 |
/// suitable for "bit tests" |
--- |
| 2881 |
void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, |
0 |
2881 |
void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, |
0 |
| 2882 |
MachineBasicBlock *SwitchBB) { |
--- |
2882 |
MachineBasicBlock *SwitchBB) { |
--- |
| 2883 |
SDLoc dl = getCurSDLoc(); |
0 |
2883 |
SDLoc dl = getCurSDLoc(); |
0 |
| 2884 |
|
--- |
2884 |
|
--- |
| 2885 |
// Subtract the minimum value. |
--- |
2885 |
// Subtract the minimum value. |
--- |
| 2886 |
SDValue SwitchOp = getValue(B.SValue); |
0 |
2886 |
SDValue SwitchOp = getValue(B.SValue); |
0 |
| 2887 |
EVT VT = SwitchOp.getValueType(); |
0 |
2887 |
EVT VT = SwitchOp.getValueType(); |
0 |
| 2888 |
SDValue RangeSub = |
--- |
2888 |
SDValue RangeSub = |
--- |
| 2889 |
DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT)); |
0 |
2889 |
DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT)); |
0 |
| 2890 |
|
--- |
2890 |
|
--- |
| 2891 |
// Determine the type of the test operands. |
--- |
2891 |
// Determine the type of the test operands. |
--- |
| 2892 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
2892 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 2893 |
bool UsePtrType = false; |
0 |
2893 |
bool UsePtrType = false; |
0 |
| 2894 |
if (!TLI.isTypeLegal(VT)) { |
0 |
2894 |
if (!TLI.isTypeLegal(VT)) { |
0 |
| 2895 |
UsePtrType = true; |
0 |
2895 |
UsePtrType = true; |
0 |
| 2896 |
} else { |
--- |
2896 |
} else { |
--- |
| 2897 |
for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) |
0 |
2897 |
for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) |
0 |
| 2898 |
if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { |
0 |
2898 |
if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { |
0 |
| 2899 |
// Switch table case range are encoded into series of masks. |
--- |
2899 |
// Switch table case range are encoded into series of masks. |
--- |
| 2900 |
// Just use pointer type, it's guaranteed to fit. |
--- |
2900 |
// Just use pointer type, it's guaranteed to fit. |
--- |
| 2901 |
UsePtrType = true; |
0 |
2901 |
UsePtrType = true; |
0 |
| 2902 |
break; |
0 |
2902 |
break; |
0 |
| 2903 |
} |
--- |
2903 |
} |
--- |
| 2904 |
} |
--- |
2904 |
} |
--- |
| 2905 |
SDValue Sub = RangeSub; |
0 |
2905 |
SDValue Sub = RangeSub; |
0 |
| 2906 |
if (UsePtrType) { |
0 |
2906 |
if (UsePtrType) { |
0 |
| 2907 |
VT = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
2907 |
VT = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
| 2908 |
Sub = DAG.getZExtOrTrunc(Sub, dl, VT); |
0 |
2908 |
Sub = DAG.getZExtOrTrunc(Sub, dl, VT); |
0 |
| 2909 |
} |
--- |
2909 |
} |
--- |
| 2910 |
|
--- |
2910 |
|
--- |
| 2911 |
B.RegVT = VT.getSimpleVT(); |
0 |
2911 |
B.RegVT = VT.getSimpleVT(); |
0 |
| 2912 |
B.Reg = FuncInfo.CreateReg(B.RegVT); |
0 |
2912 |
B.Reg = FuncInfo.CreateReg(B.RegVT); |
0 |
| 2913 |
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub); |
0 |
2913 |
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub); |
0 |
| 2914 |
|
--- |
2914 |
|
--- |
| 2915 |
MachineBasicBlock* MBB = B.Cases[0].ThisBB; |
0 |
2915 |
MachineBasicBlock* MBB = B.Cases[0].ThisBB; |
0 |
| 2916 |
|
--- |
2916 |
|
--- |
| 2917 |
if (!B.FallthroughUnreachable) |
0 |
2917 |
if (!B.FallthroughUnreachable) |
0 |
| 2918 |
addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb); |
0 |
2918 |
addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb); |
0 |
| 2919 |
addSuccessorWithProb(SwitchBB, MBB, B.Prob); |
0 |
2919 |
addSuccessorWithProb(SwitchBB, MBB, B.Prob); |
0 |
| 2920 |
SwitchBB->normalizeSuccProbs(); |
0 |
2920 |
SwitchBB->normalizeSuccProbs(); |
0 |
| 2921 |
|
--- |
2921 |
|
--- |
| 2922 |
SDValue Root = CopyTo; |
0 |
2922 |
SDValue Root = CopyTo; |
0 |
| 2923 |
if (!B.FallthroughUnreachable) { |
0 |
2923 |
if (!B.FallthroughUnreachable) { |
0 |
| 2924 |
// Conditional branch to the default block. |
--- |
2924 |
// Conditional branch to the default block. |
--- |
| 2925 |
SDValue RangeCmp = DAG.getSetCC(dl, |
0 |
2925 |
SDValue RangeCmp = DAG.getSetCC(dl, |
0 |
| 2926 |
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), |
0 |
2926 |
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), |
0 |
| 2927 |
RangeSub.getValueType()), |
--- |
2927 |
RangeSub.getValueType()), |
--- |
| 2928 |
RangeSub, DAG.getConstant(B.Range, dl, RangeSub.getValueType()), |
0 |
2928 |
RangeSub, DAG.getConstant(B.Range, dl, RangeSub.getValueType()), |
0 |
| 2929 |
ISD::SETUGT); |
--- |
2929 |
ISD::SETUGT); |
--- |
| 2930 |
|
--- |
2930 |
|
--- |
| 2931 |
Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp, |
0 |
2931 |
Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp, |
0 |
| 2932 |
DAG.getBasicBlock(B.Default)); |
0 |
2932 |
DAG.getBasicBlock(B.Default)); |
0 |
| 2933 |
} |
--- |
2933 |
} |
--- |
| 2934 |
|
--- |
2934 |
|
--- |
| 2935 |
// Avoid emitting unnecessary branches to the next block. |
--- |
2935 |
// Avoid emitting unnecessary branches to the next block. |
--- |
| 2936 |
if (MBB != NextBlock(SwitchBB)) |
0 |
2936 |
if (MBB != NextBlock(SwitchBB)) |
0 |
| 2937 |
Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB)); |
0 |
2937 |
Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB)); |
0 |
| 2938 |
|
--- |
2938 |
|
--- |
| 2939 |
DAG.setRoot(Root); |
0 |
2939 |
DAG.setRoot(Root); |
0 |
| 2940 |
} |
0 |
2940 |
} |
0 |
| 2941 |
|
--- |
2941 |
|
--- |
| 2942 |
/// visitBitTestCase - this function produces one "bit test" |
--- |
2942 |
/// visitBitTestCase - this function produces one "bit test" |
--- |
| 2943 |
void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, |
0 |
2943 |
void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, |
0 |
| 2944 |
MachineBasicBlock* NextMBB, |
--- |
2944 |
MachineBasicBlock* NextMBB, |
--- |
| 2945 |
BranchProbability BranchProbToNext, |
--- |
2945 |
BranchProbability BranchProbToNext, |
--- |
| 2946 |
unsigned Reg, |
--- |
2946 |
unsigned Reg, |
--- |
| 2947 |
BitTestCase &B, |
--- |
2947 |
BitTestCase &B, |
--- |
| 2948 |
MachineBasicBlock *SwitchBB) { |
--- |
2948 |
MachineBasicBlock *SwitchBB) { |
--- |
| 2949 |
SDLoc dl = getCurSDLoc(); |
0 |
2949 |
SDLoc dl = getCurSDLoc(); |
0 |
| 2950 |
MVT VT = BB.RegVT; |
0 |
2950 |
MVT VT = BB.RegVT; |
0 |
| 2951 |
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); |
0 |
2951 |
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); |
0 |
| 2952 |
SDValue Cmp; |
0 |
2952 |
SDValue Cmp; |
0 |
| 2953 |
unsigned PopCount = llvm::popcount(B.Mask); |
0 |
2953 |
unsigned PopCount = llvm::popcount(B.Mask); |
0 |
| 2954 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
2954 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 2955 |
if (PopCount == 1) { |
0 |
2955 |
if (PopCount == 1) { |
0 |
| 2956 |
// Testing for a single bit; just compare the shift count with what it |
--- |
2956 |
// Testing for a single bit; just compare the shift count with what it |
--- |
| 2957 |
// would need to be to shift a 1 bit in that position. |
--- |
2957 |
// would need to be to shift a 1 bit in that position. |
--- |
| 2958 |
Cmp = DAG.getSetCC( |
0 |
2958 |
Cmp = DAG.getSetCC( |
0 |
| 2959 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), |
0 |
2959 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), |
0 |
| 2960 |
ShiftOp, DAG.getConstant(llvm::countr_zero(B.Mask), dl, VT), |
0 |
2960 |
ShiftOp, DAG.getConstant(llvm::countr_zero(B.Mask), dl, VT), |
0 |
| 2961 |
ISD::SETEQ); |
--- |
2961 |
ISD::SETEQ); |
--- |
| 2962 |
} else if (PopCount == BB.Range) { |
0 |
2962 |
} else if (PopCount == BB.Range) { |
0 |
| 2963 |
// There is only one zero bit in the range, test for it directly. |
--- |
2963 |
// There is only one zero bit in the range, test for it directly. |
--- |
| 2964 |
Cmp = DAG.getSetCC( |
0 |
2964 |
Cmp = DAG.getSetCC( |
0 |
| 2965 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), |
0 |
2965 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), |
0 |
| 2966 |
ShiftOp, DAG.getConstant(llvm::countr_one(B.Mask), dl, VT), ISD::SETNE); |
0 |
2966 |
ShiftOp, DAG.getConstant(llvm::countr_one(B.Mask), dl, VT), ISD::SETNE); |
0 |
| 2967 |
} else { |
--- |
2967 |
} else { |
--- |
| 2968 |
// Make desired shift |
--- |
2968 |
// Make desired shift |
--- |
| 2969 |
SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT, |
0 |
2969 |
SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT, |
0 |
| 2970 |
DAG.getConstant(1, dl, VT), ShiftOp); |
0 |
2970 |
DAG.getConstant(1, dl, VT), ShiftOp); |
0 |
| 2971 |
|
--- |
2971 |
|
--- |
| 2972 |
// Emit bit tests and jumps |
--- |
2972 |
// Emit bit tests and jumps |
--- |
| 2973 |
SDValue AndOp = DAG.getNode(ISD::AND, dl, |
0 |
2973 |
SDValue AndOp = DAG.getNode(ISD::AND, dl, |
0 |
| 2974 |
VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT)); |
0 |
2974 |
VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT)); |
0 |
| 2975 |
Cmp = DAG.getSetCC( |
0 |
2975 |
Cmp = DAG.getSetCC( |
0 |
| 2976 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), |
0 |
2976 |
dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), |
0 |
| 2977 |
AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE); |
0 |
2977 |
AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE); |
0 |
| 2978 |
} |
--- |
2978 |
} |
--- |
| 2979 |
|
--- |
2979 |
|
--- |
| 2980 |
// The branch probability from SwitchBB to B.TargetBB is B.ExtraProb. |
--- |
2980 |
// The branch probability from SwitchBB to B.TargetBB is B.ExtraProb. |
--- |
| 2981 |
addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb); |
0 |
2981 |
addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb); |
0 |
| 2982 |
// The branch probability from SwitchBB to NextMBB is BranchProbToNext. |
--- |
2982 |
// The branch probability from SwitchBB to NextMBB is BranchProbToNext. |
--- |
| 2983 |
addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext); |
0 |
2983 |
addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext); |
0 |
| 2984 |
// It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is |
--- |
2984 |
// It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is |
--- |
| 2985 |
// one as they are relative probabilities (and thus work more like weights), |
--- |
2985 |
// one as they are relative probabilities (and thus work more like weights), |
--- |
| 2986 |
// and hence we need to normalize them to let the sum of them become one. |
--- |
2986 |
// and hence we need to normalize them to let the sum of them become one. |
--- |
| 2987 |
SwitchBB->normalizeSuccProbs(); |
0 |
2987 |
SwitchBB->normalizeSuccProbs(); |
0 |
| 2988 |
|
--- |
2988 |
|
--- |
| 2989 |
SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, |
0 |
2989 |
SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, |
0 |
| 2990 |
MVT::Other, getControlRoot(), |
--- |
2990 |
MVT::Other, getControlRoot(), |
--- |
| 2991 |
Cmp, DAG.getBasicBlock(B.TargetBB)); |
0 |
2991 |
Cmp, DAG.getBasicBlock(B.TargetBB)); |
0 |
| 2992 |
|
--- |
2992 |
|
--- |
| 2993 |
// Avoid emitting unnecessary branches to the next block. |
--- |
2993 |
// Avoid emitting unnecessary branches to the next block. |
--- |
| 2994 |
if (NextMBB != NextBlock(SwitchBB)) |
0 |
2994 |
if (NextMBB != NextBlock(SwitchBB)) |
0 |
| 2995 |
BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd, |
0 |
2995 |
BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd, |
0 |
| 2996 |
DAG.getBasicBlock(NextMBB)); |
0 |
2996 |
DAG.getBasicBlock(NextMBB)); |
0 |
| 2997 |
|
--- |
2997 |
|
--- |
| 2998 |
DAG.setRoot(BrAnd); |
0 |
2998 |
DAG.setRoot(BrAnd); |
0 |
| 2999 |
} |
0 |
2999 |
} |
0 |
| 3000 |
|
--- |
3000 |
|
--- |
| 3001 |
void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { |
0 |
3001 |
void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { |
0 |
| 3002 |
MachineBasicBlock *InvokeMBB = FuncInfo.MBB; |
0 |
3002 |
MachineBasicBlock *InvokeMBB = FuncInfo.MBB; |
0 |
| 3003 |
|
--- |
3003 |
|
--- |
| 3004 |
// Retrieve successors. Look through artificial IR level blocks like |
--- |
3004 |
// Retrieve successors. Look through artificial IR level blocks like |
--- |
| 3005 |
// catchswitch for successors. |
--- |
3005 |
// catchswitch for successors. |
--- |
| 3006 |
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; |
0 |
3006 |
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; |
0 |
| 3007 |
const BasicBlock *EHPadBB = I.getSuccessor(1); |
0 |
3007 |
const BasicBlock *EHPadBB = I.getSuccessor(1); |
0 |
| 3008 |
MachineBasicBlock *EHPadMBB = FuncInfo.MBBMap[EHPadBB]; |
0 |
3008 |
MachineBasicBlock *EHPadMBB = FuncInfo.MBBMap[EHPadBB]; |
0 |
| 3009 |
|
--- |
3009 |
|
--- |
| 3010 |
// Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't |
--- |
3010 |
// Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't |
--- |
| 3011 |
// have to do anything here to lower funclet bundles. |
--- |
3011 |
// have to do anything here to lower funclet bundles. |
--- |
| 3012 |
assert(!I.hasOperandBundlesOtherThan( |
0 |
3012 |
assert(!I.hasOperandBundlesOtherThan( |
0 |
| 3013 |
{LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, |
--- |
3013 |
{LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, |
--- |
| 3014 |
LLVMContext::OB_gc_live, LLVMContext::OB_funclet, |
--- |
3014 |
LLVMContext::OB_gc_live, LLVMContext::OB_funclet, |
--- |
| 3015 |
LLVMContext::OB_cfguardtarget, |
--- |
3015 |
LLVMContext::OB_cfguardtarget, |
--- |
| 3016 |
LLVMContext::OB_clang_arc_attachedcall}) && |
--- |
3016 |
LLVMContext::OB_clang_arc_attachedcall}) && |
--- |
| 3017 |
"Cannot lower invokes with arbitrary operand bundles yet!"); |
--- |
3017 |
"Cannot lower invokes with arbitrary operand bundles yet!"); |
--- |
| 3018 |
|
--- |
3018 |
|
--- |
| 3019 |
const Value *Callee(I.getCalledOperand()); |
0 |
3019 |
const Value *Callee(I.getCalledOperand()); |
0 |
| 3020 |
const Function *Fn = dyn_cast(Callee); |
0 |
3020 |
const Function *Fn = dyn_cast(Callee); |
0 |
| 3021 |
if (isa(Callee)) |
0 |
3021 |
if (isa(Callee)) |
0 |
| 3022 |
visitInlineAsm(I, EHPadBB); |
0 |
3022 |
visitInlineAsm(I, EHPadBB); |
0 |
| 3023 |
else if (Fn && Fn->isIntrinsic()) { |
0 |
3023 |
else if (Fn && Fn->isIntrinsic()) { |
0 |
| 3024 |
switch (Fn->getIntrinsicID()) { |
0 |
3024 |
switch (Fn->getIntrinsicID()) { |
0 |
| 3025 |
default: |
0 |
3025 |
default: |
0 |
| 3026 |
llvm_unreachable("Cannot invoke this intrinsic"); |
0 |
3026 |
llvm_unreachable("Cannot invoke this intrinsic"); |
0 |
| 3027 |
case Intrinsic::donothing: |
0 |
3027 |
case Intrinsic::donothing: |
0 |
| 3028 |
// Ignore invokes to @llvm.donothing: jump directly to the next BB. |
--- |
3028 |
// Ignore invokes to @llvm.donothing: jump directly to the next BB. |
--- |
| 3029 |
case Intrinsic::seh_try_begin: |
--- |
3029 |
case Intrinsic::seh_try_begin: |
--- |
| 3030 |
case Intrinsic::seh_scope_begin: |
--- |
3030 |
case Intrinsic::seh_scope_begin: |
--- |
| 3031 |
case Intrinsic::seh_try_end: |
--- |
3031 |
case Intrinsic::seh_try_end: |
--- |
| 3032 |
case Intrinsic::seh_scope_end: |
--- |
3032 |
case Intrinsic::seh_scope_end: |
--- |
| 3033 |
if (EHPadMBB) |
0 |
3033 |
if (EHPadMBB) |
0 |
| 3034 |
// a block referenced by EH table |
--- |
3034 |
// a block referenced by EH table |
--- |
| 3035 |
// so dtor-funclet not removed by opts |
--- |
3035 |
// so dtor-funclet not removed by opts |
--- |
| 3036 |
EHPadMBB->setMachineBlockAddressTaken(); |
0 |
3036 |
EHPadMBB->setMachineBlockAddressTaken(); |
0 |
| 3037 |
break; |
0 |
3037 |
break; |
0 |
| 3038 |
case Intrinsic::experimental_patchpoint_void: |
0 |
3038 |
case Intrinsic::experimental_patchpoint_void: |
0 |
| 3039 |
case Intrinsic::experimental_patchpoint_i64: |
--- |
3039 |
case Intrinsic::experimental_patchpoint_i64: |
--- |
| 3040 |
visitPatchpoint(I, EHPadBB); |
0 |
3040 |
visitPatchpoint(I, EHPadBB); |
0 |
| 3041 |
break; |
0 |
3041 |
break; |
0 |
| 3042 |
case Intrinsic::experimental_gc_statepoint: |
0 |
3042 |
case Intrinsic::experimental_gc_statepoint: |
0 |
| 3043 |
LowerStatepoint(cast(I), EHPadBB); |
0 |
3043 |
LowerStatepoint(cast(I), EHPadBB); |
0 |
| 3044 |
break; |
0 |
3044 |
break; |
0 |
| 3045 |
case Intrinsic::wasm_rethrow: { |
0 |
3045 |
case Intrinsic::wasm_rethrow: { |
0 |
| 3046 |
// This is usually done in visitTargetIntrinsic, but this intrinsic is |
--- |
3046 |
// This is usually done in visitTargetIntrinsic, but this intrinsic is |
--- |
| 3047 |
// special because it can be invoked, so we manually lower it to a DAG |
--- |
3047 |
// special because it can be invoked, so we manually lower it to a DAG |
--- |
| 3048 |
// node here. |
--- |
3048 |
// node here. |
--- |
| 3049 |
SmallVector Ops; |
0 |
3049 |
SmallVector Ops; |
0 |
| 3050 |
Ops.push_back(getRoot()); // inchain |
0 |
3050 |
Ops.push_back(getRoot()); // inchain |
0 |
| 3051 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3051 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3052 |
Ops.push_back( |
0 |
3052 |
Ops.push_back( |
0 |
| 3053 |
DAG.getTargetConstant(Intrinsic::wasm_rethrow, getCurSDLoc(), |
0 |
3053 |
DAG.getTargetConstant(Intrinsic::wasm_rethrow, getCurSDLoc(), |
0 |
| 3054 |
TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
3054 |
TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 3055 |
SDVTList VTs = DAG.getVTList(ArrayRef({MVT::Other})); // outchain |
0 |
3055 |
SDVTList VTs = DAG.getVTList(ArrayRef({MVT::Other})); // outchain |
0 |
| 3056 |
DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops)); |
0 |
3056 |
DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops)); |
0 |
| 3057 |
break; |
0 |
3057 |
break; |
0 |
| 3058 |
} |
0 |
3058 |
} |
0 |
| 3059 |
} |
--- |
3059 |
} |
--- |
| 3060 |
} else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) { |
0 |
3060 |
} else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) { |
0 |
| 3061 |
// Currently we do not lower any intrinsic calls with deopt operand bundles. |
--- |
3061 |
// Currently we do not lower any intrinsic calls with deopt operand bundles. |
--- |
| 3062 |
// Eventually we will support lowering the @llvm.experimental.deoptimize |
--- |
3062 |
// Eventually we will support lowering the @llvm.experimental.deoptimize |
--- |
| 3063 |
// intrinsic, and right now there are no plans to support other intrinsics |
--- |
3063 |
// intrinsic, and right now there are no plans to support other intrinsics |
--- |
| 3064 |
// with deopt state. |
--- |
3064 |
// with deopt state. |
--- |
| 3065 |
LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB); |
0 |
3065 |
LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB); |
0 |
| 3066 |
} else { |
--- |
3066 |
} else { |
--- |
| 3067 |
LowerCallTo(I, getValue(Callee), false, false, EHPadBB); |
0 |
3067 |
LowerCallTo(I, getValue(Callee), false, false, EHPadBB); |
0 |
| 3068 |
} |
--- |
3068 |
} |
--- |
| 3069 |
|
--- |
3069 |
|
--- |
| 3070 |
// If the value of the invoke is used outside of its defining block, make it |
--- |
3070 |
// If the value of the invoke is used outside of its defining block, make it |
--- |
| 3071 |
// available as a virtual register. |
--- |
3071 |
// available as a virtual register. |
--- |
| 3072 |
// We already took care of the exported value for the statepoint instruction |
--- |
3072 |
// We already took care of the exported value for the statepoint instruction |
--- |
| 3073 |
// during call to the LowerStatepoint. |
--- |
3073 |
// during call to the LowerStatepoint. |
--- |
| 3074 |
if (!isa(I)) { |
0 |
3074 |
if (!isa(I)) { |
0 |
| 3075 |
CopyToExportRegsIfNeeded(&I); |
0 |
3075 |
CopyToExportRegsIfNeeded(&I); |
0 |
| 3076 |
} |
--- |
3076 |
} |
--- |
| 3077 |
|
--- |
3077 |
|
--- |
| 3078 |
SmallVector, 1> UnwindDests; |
0 |
3078 |
SmallVector, 1> UnwindDests; |
0 |
| 3079 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
3079 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
| 3080 |
BranchProbability EHPadBBProb = |
--- |
3080 |
BranchProbability EHPadBBProb = |
--- |
| 3081 |
BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB) |
0 |
3081 |
BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB) |
0 |
| 3082 |
: BranchProbability::getZero(); |
0 |
3082 |
: BranchProbability::getZero(); |
0 |
| 3083 |
findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests); |
0 |
3083 |
findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests); |
0 |
| 3084 |
|
--- |
3084 |
|
--- |
| 3085 |
// Update successor info. |
--- |
3085 |
// Update successor info. |
--- |
| 3086 |
addSuccessorWithProb(InvokeMBB, Return); |
0 |
3086 |
addSuccessorWithProb(InvokeMBB, Return); |
0 |
| 3087 |
for (auto &UnwindDest : UnwindDests) { |
0 |
3087 |
for (auto &UnwindDest : UnwindDests) { |
0 |
| 3088 |
UnwindDest.first->setIsEHPad(); |
0 |
3088 |
UnwindDest.first->setIsEHPad(); |
0 |
| 3089 |
addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second); |
0 |
3089 |
addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second); |
0 |
| 3090 |
} |
--- |
3090 |
} |
--- |
| 3091 |
InvokeMBB->normalizeSuccProbs(); |
0 |
3091 |
InvokeMBB->normalizeSuccProbs(); |
0 |
| 3092 |
|
--- |
3092 |
|
--- |
| 3093 |
// Drop into normal successor. |
--- |
3093 |
// Drop into normal successor. |
--- |
| 3094 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(), |
0 |
3094 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(), |
0 |
| 3095 |
DAG.getBasicBlock(Return))); |
0 |
3095 |
DAG.getBasicBlock(Return))); |
0 |
| 3096 |
} |
0 |
3096 |
} |
0 |
| 3097 |
|
--- |
3097 |
|
--- |
| 3098 |
void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) { |
0 |
3098 |
void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) { |
0 |
| 3099 |
MachineBasicBlock *CallBrMBB = FuncInfo.MBB; |
0 |
3099 |
MachineBasicBlock *CallBrMBB = FuncInfo.MBB; |
0 |
| 3100 |
|
--- |
3100 |
|
--- |
| 3101 |
// Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't |
--- |
3101 |
// Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't |
--- |
| 3102 |
// have to do anything here to lower funclet bundles. |
--- |
3102 |
// have to do anything here to lower funclet bundles. |
--- |
| 3103 |
assert(!I.hasOperandBundlesOtherThan( |
0 |
3103 |
assert(!I.hasOperandBundlesOtherThan( |
0 |
| 3104 |
{LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && |
--- |
3104 |
{LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && |
--- |
| 3105 |
"Cannot lower callbrs with arbitrary operand bundles yet!"); |
--- |
3105 |
"Cannot lower callbrs with arbitrary operand bundles yet!"); |
--- |
| 3106 |
|
--- |
3106 |
|
--- |
| 3107 |
assert(I.isInlineAsm() && "Only know how to handle inlineasm callbr"); |
0 |
3107 |
assert(I.isInlineAsm() && "Only know how to handle inlineasm callbr"); |
0 |
| 3108 |
visitInlineAsm(I); |
0 |
3108 |
visitInlineAsm(I); |
0 |
| 3109 |
CopyToExportRegsIfNeeded(&I); |
0 |
3109 |
CopyToExportRegsIfNeeded(&I); |
0 |
| 3110 |
|
--- |
3110 |
|
--- |
| 3111 |
// Retrieve successors. |
--- |
3111 |
// Retrieve successors. |
--- |
| 3112 |
SmallPtrSet Dests; |
0 |
3112 |
SmallPtrSet Dests; |
0 |
| 3113 |
Dests.insert(I.getDefaultDest()); |
0 |
3113 |
Dests.insert(I.getDefaultDest()); |
0 |
| 3114 |
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()]; |
0 |
3114 |
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()]; |
0 |
| 3115 |
|
--- |
3115 |
|
--- |
| 3116 |
// Update successor info. |
--- |
3116 |
// Update successor info. |
--- |
| 3117 |
addSuccessorWithProb(CallBrMBB, Return, BranchProbability::getOne()); |
0 |
3117 |
addSuccessorWithProb(CallBrMBB, Return, BranchProbability::getOne()); |
0 |
| 3118 |
for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) { |
0 |
3118 |
for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) { |
0 |
| 3119 |
BasicBlock *Dest = I.getIndirectDest(i); |
0 |
3119 |
BasicBlock *Dest = I.getIndirectDest(i); |
0 |
| 3120 |
MachineBasicBlock *Target = FuncInfo.MBBMap[Dest]; |
0 |
3120 |
MachineBasicBlock *Target = FuncInfo.MBBMap[Dest]; |
0 |
| 3121 |
Target->setIsInlineAsmBrIndirectTarget(); |
0 |
3121 |
Target->setIsInlineAsmBrIndirectTarget(); |
0 |
| 3122 |
Target->setMachineBlockAddressTaken(); |
0 |
3122 |
Target->setMachineBlockAddressTaken(); |
0 |
| 3123 |
Target->setLabelMustBeEmitted(); |
0 |
3123 |
Target->setLabelMustBeEmitted(); |
0 |
| 3124 |
// Don't add duplicate machine successors. |
--- |
3124 |
// Don't add duplicate machine successors. |
--- |
| 3125 |
if (Dests.insert(Dest).second) |
0 |
3125 |
if (Dests.insert(Dest).second) |
0 |
| 3126 |
addSuccessorWithProb(CallBrMBB, Target, BranchProbability::getZero()); |
0 |
3126 |
addSuccessorWithProb(CallBrMBB, Target, BranchProbability::getZero()); |
0 |
| 3127 |
} |
--- |
3127 |
} |
--- |
| 3128 |
CallBrMBB->normalizeSuccProbs(); |
0 |
3128 |
CallBrMBB->normalizeSuccProbs(); |
0 |
| 3129 |
|
--- |
3129 |
|
--- |
| 3130 |
// Drop into default successor. |
--- |
3130 |
// Drop into default successor. |
--- |
| 3131 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), |
0 |
3131 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), |
0 |
| 3132 |
MVT::Other, getControlRoot(), |
--- |
3132 |
MVT::Other, getControlRoot(), |
--- |
| 3133 |
DAG.getBasicBlock(Return))); |
0 |
3133 |
DAG.getBasicBlock(Return))); |
0 |
| 3134 |
} |
0 |
3134 |
} |
0 |
| 3135 |
|
--- |
3135 |
|
--- |
| 3136 |
void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { |
0 |
3136 |
void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { |
0 |
| 3137 |
llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); |
0 |
3137 |
llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); |
0 |
| 3138 |
} |
--- |
3138 |
} |
--- |
| 3139 |
|
--- |
3139 |
|
--- |
| 3140 |
void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { |
0 |
3140 |
void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { |
0 |
| 3141 |
assert(FuncInfo.MBB->isEHPad() && |
0 |
3141 |
assert(FuncInfo.MBB->isEHPad() && |
0 |
| 3142 |
"Call to landingpad not in landing pad!"); |
--- |
3142 |
"Call to landingpad not in landing pad!"); |
--- |
| 3143 |
|
--- |
3143 |
|
--- |
| 3144 |
// If there aren't registers to copy the values into (e.g., during SjLj |
--- |
3144 |
// If there aren't registers to copy the values into (e.g., during SjLj |
--- |
| 3145 |
// exceptions), then don't bother to create these DAG nodes. |
--- |
3145 |
// exceptions), then don't bother to create these DAG nodes. |
--- |
| 3146 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3146 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3147 |
const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn(); |
0 |
3147 |
const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn(); |
0 |
| 3148 |
if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 && |
0 |
3148 |
if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 && |
0 |
| 3149 |
TLI.getExceptionSelectorRegister(PersonalityFn) == 0) |
0 |
3149 |
TLI.getExceptionSelectorRegister(PersonalityFn) == 0) |
0 |
| 3150 |
return; |
0 |
3150 |
return; |
0 |
| 3151 |
|
--- |
3151 |
|
--- |
| 3152 |
// If landingpad's return type is token type, we don't create DAG nodes |
--- |
3152 |
// If landingpad's return type is token type, we don't create DAG nodes |
--- |
| 3153 |
// for its exception pointer and selector value. The extraction of exception |
--- |
3153 |
// for its exception pointer and selector value. The extraction of exception |
--- |
| 3154 |
// pointer or selector value from token type landingpads is not currently |
--- |
3154 |
// pointer or selector value from token type landingpads is not currently |
--- |
| 3155 |
// supported. |
--- |
3155 |
// supported. |
--- |
| 3156 |
if (LP.getType()->isTokenTy()) |
0 |
3156 |
if (LP.getType()->isTokenTy()) |
0 |
| 3157 |
return; |
0 |
3157 |
return; |
0 |
| 3158 |
|
--- |
3158 |
|
--- |
| 3159 |
SmallVector ValueVTs; |
0 |
3159 |
SmallVector ValueVTs; |
0 |
| 3160 |
SDLoc dl = getCurSDLoc(); |
0 |
3160 |
SDLoc dl = getCurSDLoc(); |
0 |
| 3161 |
ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs); |
0 |
3161 |
ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs); |
0 |
| 3162 |
assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported"); |
0 |
3162 |
assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported"); |
0 |
| 3163 |
|
--- |
3163 |
|
--- |
| 3164 |
// Get the two live-in registers as SDValues. The physregs have already been |
--- |
3164 |
// Get the two live-in registers as SDValues. The physregs have already been |
--- |
| 3165 |
// copied into virtual registers. |
--- |
3165 |
// copied into virtual registers. |
--- |
| 3166 |
SDValue Ops[2]; |
0 |
3166 |
SDValue Ops[2]; |
0 |
| 3167 |
if (FuncInfo.ExceptionPointerVirtReg) { |
0 |
3167 |
if (FuncInfo.ExceptionPointerVirtReg) { |
0 |
| 3168 |
Ops[0] = DAG.getZExtOrTrunc( |
0 |
3168 |
Ops[0] = DAG.getZExtOrTrunc( |
0 |
| 3169 |
DAG.getCopyFromReg(DAG.getEntryNode(), dl, |
0 |
3169 |
DAG.getCopyFromReg(DAG.getEntryNode(), dl, |
0 |
| 3170 |
FuncInfo.ExceptionPointerVirtReg, |
0 |
3170 |
FuncInfo.ExceptionPointerVirtReg, |
0 |
| 3171 |
TLI.getPointerTy(DAG.getDataLayout())), |
0 |
3171 |
TLI.getPointerTy(DAG.getDataLayout())), |
0 |
| 3172 |
dl, ValueVTs[0]); |
0 |
3172 |
dl, ValueVTs[0]); |
0 |
| 3173 |
} else { |
--- |
3173 |
} else { |
--- |
| 3174 |
Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
3174 |
Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 3175 |
} |
--- |
3175 |
} |
--- |
| 3176 |
Ops[1] = DAG.getZExtOrTrunc( |
0 |
3176 |
Ops[1] = DAG.getZExtOrTrunc( |
0 |
| 3177 |
DAG.getCopyFromReg(DAG.getEntryNode(), dl, |
0 |
3177 |
DAG.getCopyFromReg(DAG.getEntryNode(), dl, |
0 |
| 3178 |
FuncInfo.ExceptionSelectorVirtReg, |
0 |
3178 |
FuncInfo.ExceptionSelectorVirtReg, |
0 |
| 3179 |
TLI.getPointerTy(DAG.getDataLayout())), |
0 |
3179 |
TLI.getPointerTy(DAG.getDataLayout())), |
0 |
| 3180 |
dl, ValueVTs[1]); |
0 |
3180 |
dl, ValueVTs[1]); |
0 |
| 3181 |
|
--- |
3181 |
|
--- |
| 3182 |
// Merge into one. |
--- |
3182 |
// Merge into one. |
--- |
| 3183 |
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, |
0 |
3183 |
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, |
0 |
| 3184 |
DAG.getVTList(ValueVTs), Ops); |
0 |
3184 |
DAG.getVTList(ValueVTs), Ops); |
0 |
| 3185 |
setValue(&LP, Res); |
0 |
3185 |
setValue(&LP, Res); |
0 |
| 3186 |
} |
0 |
3186 |
} |
0 |
| 3187 |
|
--- |
3187 |
|
--- |
| 3188 |
void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, |
0 |
3188 |
void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, |
0 |
| 3189 |
MachineBasicBlock *Last) { |
--- |
3189 |
MachineBasicBlock *Last) { |
--- |
| 3190 |
// Update JTCases. |
--- |
3190 |
// Update JTCases. |
--- |
| 3191 |
for (JumpTableBlock &JTB : SL->JTCases) |
0 |
3191 |
for (JumpTableBlock &JTB : SL->JTCases) |
0 |
| 3192 |
if (JTB.first.HeaderBB == First) |
0 |
3192 |
if (JTB.first.HeaderBB == First) |
0 |
| 3193 |
JTB.first.HeaderBB = Last; |
0 |
3193 |
JTB.first.HeaderBB = Last; |
0 |
| 3194 |
|
--- |
3194 |
|
--- |
| 3195 |
// Update BitTestCases. |
--- |
3195 |
// Update BitTestCases. |
--- |
| 3196 |
for (BitTestBlock &BTB : SL->BitTestCases) |
0 |
3196 |
for (BitTestBlock &BTB : SL->BitTestCases) |
0 |
| 3197 |
if (BTB.Parent == First) |
0 |
3197 |
if (BTB.Parent == First) |
0 |
| 3198 |
BTB.Parent = Last; |
0 |
3198 |
BTB.Parent = Last; |
0 |
| 3199 |
} |
0 |
3199 |
} |
0 |
| 3200 |
|
--- |
3200 |
|
--- |
| 3201 |
void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { |
0 |
3201 |
void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { |
0 |
| 3202 |
MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; |
0 |
3202 |
MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; |
0 |
| 3203 |
|
--- |
3203 |
|
--- |
| 3204 |
// Update machine-CFG edges with unique successors. |
--- |
3204 |
// Update machine-CFG edges with unique successors. |
--- |
| 3205 |
SmallSet Done; |
0 |
3205 |
SmallSet Done; |
0 |
| 3206 |
for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { |
0 |
3206 |
for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { |
0 |
| 3207 |
BasicBlock *BB = I.getSuccessor(i); |
0 |
3207 |
BasicBlock *BB = I.getSuccessor(i); |
0 |
| 3208 |
bool Inserted = Done.insert(BB).second; |
0 |
3208 |
bool Inserted = Done.insert(BB).second; |
0 |
| 3209 |
if (!Inserted) |
0 |
3209 |
if (!Inserted) |
0 |
| 3210 |
continue; |
0 |
3210 |
continue; |
0 |
| 3211 |
|
--- |
3211 |
|
--- |
| 3212 |
MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; |
0 |
3212 |
MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; |
0 |
| 3213 |
addSuccessorWithProb(IndirectBrMBB, Succ); |
0 |
3213 |
addSuccessorWithProb(IndirectBrMBB, Succ); |
0 |
| 3214 |
} |
--- |
3214 |
} |
--- |
| 3215 |
IndirectBrMBB->normalizeSuccProbs(); |
0 |
3215 |
IndirectBrMBB->normalizeSuccProbs(); |
0 |
| 3216 |
|
--- |
3216 |
|
--- |
| 3217 |
DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), |
0 |
3217 |
DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), |
0 |
| 3218 |
MVT::Other, getControlRoot(), |
--- |
3218 |
MVT::Other, getControlRoot(), |
--- |
| 3219 |
getValue(I.getAddress()))); |
--- |
3219 |
getValue(I.getAddress()))); |
--- |
| 3220 |
} |
0 |
3220 |
} |
0 |
| 3221 |
|
--- |
3221 |
|
--- |
| 3222 |
void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) { |
0 |
3222 |
void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) { |
0 |
| 3223 |
if (!DAG.getTarget().Options.TrapUnreachable) |
0 |
3223 |
if (!DAG.getTarget().Options.TrapUnreachable) |
0 |
| 3224 |
return; |
0 |
3224 |
return; |
0 |
| 3225 |
|
--- |
3225 |
|
--- |
| 3226 |
// We may be able to ignore unreachable behind a noreturn call. |
--- |
3226 |
// We may be able to ignore unreachable behind a noreturn call. |
--- |
| 3227 |
if (DAG.getTarget().Options.NoTrapAfterNoreturn) { |
0 |
3227 |
if (DAG.getTarget().Options.NoTrapAfterNoreturn) { |
0 |
| 3228 |
const BasicBlock &BB = *I.getParent(); |
0 |
3228 |
const BasicBlock &BB = *I.getParent(); |
0 |
| 3229 |
if (&I != &BB.front()) { |
0 |
3229 |
if (&I != &BB.front()) { |
0 |
| 3230 |
BasicBlock::const_iterator PredI = |
--- |
3230 |
BasicBlock::const_iterator PredI = |
--- |
| 3231 |
std::prev(BasicBlock::const_iterator(&I)); |
0 |
3231 |
std::prev(BasicBlock::const_iterator(&I)); |
0 |
| 3232 |
if (const CallInst *Call = dyn_cast(&*PredI)) { |
0 |
3232 |
if (const CallInst *Call = dyn_cast(&*PredI)) { |
0 |
| 3233 |
if (Call->doesNotReturn()) |
0 |
3233 |
if (Call->doesNotReturn()) |
0 |
| 3234 |
return; |
0 |
3234 |
return; |
0 |
| 3235 |
} |
--- |
3235 |
} |
--- |
| 3236 |
} |
--- |
3236 |
} |
--- |
| 3237 |
} |
--- |
3237 |
} |
--- |
| 3238 |
|
--- |
3238 |
|
--- |
| 3239 |
DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot())); |
0 |
3239 |
DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot())); |
0 |
| 3240 |
} |
--- |
3240 |
} |
--- |
| 3241 |
|
--- |
3241 |
|
--- |
| 3242 |
void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) { |
0 |
3242 |
void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) { |
0 |
| 3243 |
SDNodeFlags Flags; |
0 |
3243 |
SDNodeFlags Flags; |
0 |
| 3244 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
3244 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
| 3245 |
Flags.copyFMF(*FPOp); |
0 |
3245 |
Flags.copyFMF(*FPOp); |
0 |
| 3246 |
|
--- |
3246 |
|
--- |
| 3247 |
SDValue Op = getValue(I.getOperand(0)); |
0 |
3247 |
SDValue Op = getValue(I.getOperand(0)); |
0 |
| 3248 |
SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(), |
0 |
3248 |
SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(), |
0 |
| 3249 |
Op, Flags); |
--- |
3249 |
Op, Flags); |
--- |
| 3250 |
setValue(&I, UnNodeValue); |
0 |
3250 |
setValue(&I, UnNodeValue); |
0 |
| 3251 |
} |
0 |
3251 |
} |
0 |
| 3252 |
|
--- |
3252 |
|
--- |
| 3253 |
void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) { |
0 |
3253 |
void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) { |
0 |
| 3254 |
SDNodeFlags Flags; |
0 |
3254 |
SDNodeFlags Flags; |
0 |
| 3255 |
if (auto *OFBinOp = dyn_cast(&I)) { |
0 |
3255 |
if (auto *OFBinOp = dyn_cast(&I)) { |
0 |
| 3256 |
Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap()); |
0 |
3256 |
Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap()); |
0 |
| 3257 |
Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap()); |
0 |
3257 |
Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap()); |
0 |
| 3258 |
} |
--- |
3258 |
} |
--- |
| 3259 |
if (auto *ExactOp = dyn_cast(&I)) |
0 |
3259 |
if (auto *ExactOp = dyn_cast(&I)) |
0 |
| 3260 |
Flags.setExact(ExactOp->isExact()); |
0 |
3260 |
Flags.setExact(ExactOp->isExact()); |
0 |
| 3261 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
3261 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
| 3262 |
Flags.copyFMF(*FPOp); |
0 |
3262 |
Flags.copyFMF(*FPOp); |
0 |
| 3263 |
|
--- |
3263 |
|
--- |
| 3264 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
3264 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
| 3265 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
3265 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
| 3266 |
SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), |
0 |
3266 |
SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), |
0 |
| 3267 |
Op1, Op2, Flags); |
--- |
3267 |
Op1, Op2, Flags); |
--- |
| 3268 |
setValue(&I, BinNodeValue); |
0 |
3268 |
setValue(&I, BinNodeValue); |
0 |
| 3269 |
} |
0 |
3269 |
} |
0 |
| 3270 |
|
--- |
3270 |
|
--- |
| 3271 |
void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { |
0 |
3271 |
void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { |
0 |
| 3272 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
3272 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
| 3273 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
3273 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
| 3274 |
|
--- |
3274 |
|
--- |
| 3275 |
EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( |
0 |
3275 |
EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( |
0 |
| 3276 |
Op1.getValueType(), DAG.getDataLayout()); |
0 |
3276 |
Op1.getValueType(), DAG.getDataLayout()); |
0 |
| 3277 |
|
--- |
3277 |
|
--- |
| 3278 |
// Coerce the shift amount to the right type if we can. This exposes the |
--- |
3278 |
// Coerce the shift amount to the right type if we can. This exposes the |
--- |
| 3279 |
// truncate or zext to optimization early. |
--- |
3279 |
// truncate or zext to optimization early. |
--- |
| 3280 |
if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { |
0 |
3280 |
if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { |
0 |
| 3281 |
assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && |
0 |
3281 |
assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && |
0 |
| 3282 |
"Unexpected shift type"); |
--- |
3282 |
"Unexpected shift type"); |
--- |
| 3283 |
Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); |
0 |
3283 |
Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); |
0 |
| 3284 |
} |
--- |
3284 |
} |
--- |
| 3285 |
|
--- |
3285 |
|
--- |
| 3286 |
bool nuw = false; |
0 |
3286 |
bool nuw = false; |
0 |
| 3287 |
bool nsw = false; |
0 |
3287 |
bool nsw = false; |
0 |
| 3288 |
bool exact = false; |
0 |
3288 |
bool exact = false; |
0 |
| 3289 |
|
--- |
3289 |
|
--- |
| 3290 |
if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) { |
0 |
3290 |
if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) { |
0 |
| 3291 |
|
--- |
3291 |
|
--- |
| 3292 |
if (const OverflowingBinaryOperator *OFBinOp = |
0 |
3292 |
if (const OverflowingBinaryOperator *OFBinOp = |
0 |
| 3293 |
dyn_cast(&I)) { |
0 |
3293 |
dyn_cast(&I)) { |
0 |
| 3294 |
nuw = OFBinOp->hasNoUnsignedWrap(); |
0 |
3294 |
nuw = OFBinOp->hasNoUnsignedWrap(); |
0 |
| 3295 |
nsw = OFBinOp->hasNoSignedWrap(); |
0 |
3295 |
nsw = OFBinOp->hasNoSignedWrap(); |
0 |
| 3296 |
} |
--- |
3296 |
} |
--- |
| 3297 |
if (const PossiblyExactOperator *ExactOp = |
0 |
3297 |
if (const PossiblyExactOperator *ExactOp = |
0 |
| 3298 |
dyn_cast(&I)) |
0 |
3298 |
dyn_cast(&I)) |
0 |
| 3299 |
exact = ExactOp->isExact(); |
0 |
3299 |
exact = ExactOp->isExact(); |
0 |
| 3300 |
} |
--- |
3300 |
} |
--- |
| 3301 |
SDNodeFlags Flags; |
0 |
3301 |
SDNodeFlags Flags; |
0 |
| 3302 |
Flags.setExact(exact); |
0 |
3302 |
Flags.setExact(exact); |
0 |
| 3303 |
Flags.setNoSignedWrap(nsw); |
0 |
3303 |
Flags.setNoSignedWrap(nsw); |
0 |
| 3304 |
Flags.setNoUnsignedWrap(nuw); |
0 |
3304 |
Flags.setNoUnsignedWrap(nuw); |
0 |
| 3305 |
SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2, |
0 |
3305 |
SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2, |
0 |
| 3306 |
Flags); |
--- |
3306 |
Flags); |
--- |
| 3307 |
setValue(&I, Res); |
0 |
3307 |
setValue(&I, Res); |
0 |
| 3308 |
} |
0 |
3308 |
} |
0 |
| 3309 |
|
--- |
3309 |
|
--- |
| 3310 |
void SelectionDAGBuilder::visitSDiv(const User &I) { |
0 |
3310 |
void SelectionDAGBuilder::visitSDiv(const User &I) { |
0 |
| 3311 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
3311 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
| 3312 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
3312 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
| 3313 |
|
--- |
3313 |
|
--- |
| 3314 |
SDNodeFlags Flags; |
0 |
3314 |
SDNodeFlags Flags; |
0 |
| 3315 |
Flags.setExact(isa(&I) && |
0 |
3315 |
Flags.setExact(isa(&I) && |
0 |
| 3316 |
cast(&I)->isExact()); |
0 |
3316 |
cast(&I)->isExact()); |
0 |
| 3317 |
setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1, |
0 |
3317 |
setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1, |
0 |
| 3318 |
Op2, Flags)); |
--- |
3318 |
Op2, Flags)); |
--- |
| 3319 |
} |
0 |
3319 |
} |
0 |
| 3320 |
|
--- |
3320 |
|
--- |
| 3321 |
void SelectionDAGBuilder::visitICmp(const User &I) { |
1 |
3321 |
void SelectionDAGBuilder::visitICmp(const User &I) { |
1 |
| 3322 |
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; |
1 |
3322 |
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; |
1 |
| 3323 |
if (const ICmpInst *IC = dyn_cast(&I)) |
1 |
3323 |
if (const ICmpInst *IC = dyn_cast(&I)) |
1 |
| 3324 |
predicate = IC->getPredicate(); |
1 |
3324 |
predicate = IC->getPredicate(); |
1 |
| 3325 |
else if (const ConstantExpr *IC = dyn_cast(&I)) |
0 |
3325 |
else if (const ConstantExpr *IC = dyn_cast(&I)) |
0 |
| 3326 |
predicate = ICmpInst::Predicate(IC->getPredicate()); |
0 |
3326 |
predicate = ICmpInst::Predicate(IC->getPredicate()); |
0 |
| 3327 |
SDValue Op1 = getValue(I.getOperand(0)); |
1 |
3327 |
SDValue Op1 = getValue(I.getOperand(0)); |
1 |
| 3328 |
SDValue Op2 = getValue(I.getOperand(1)); |
1 |
3328 |
SDValue Op2 = getValue(I.getOperand(1)); |
1 |
| 3329 |
ISD::CondCode Opcode = getICmpCondCode(predicate); |
1 |
3329 |
ISD::CondCode Opcode = getICmpCondCode(predicate); |
1 |
| 3330 |
|
--- |
3330 |
|
--- |
| 3331 |
auto &TLI = DAG.getTargetLoweringInfo(); |
1 |
3331 |
auto &TLI = DAG.getTargetLoweringInfo(); |
1 |
| 3332 |
EVT MemVT = |
--- |
3332 |
EVT MemVT = |
--- |
| 3333 |
TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType()); |
1 |
3333 |
TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType()); |
1 |
| 3334 |
|
--- |
3334 |
|
--- |
| 3335 |
// If a pointer's DAG type is larger than its memory type then the DAG values |
--- |
3335 |
// If a pointer's DAG type is larger than its memory type then the DAG values |
--- |
| 3336 |
// are zero-extended. This breaks signed comparisons so truncate back to the |
--- |
3336 |
// are zero-extended. This breaks signed comparisons so truncate back to the |
--- |
| 3337 |
// underlying type before doing the compare. |
--- |
3337 |
// underlying type before doing the compare. |
--- |
| 3338 |
if (Op1.getValueType() != MemVT) { |
1 |
3338 |
if (Op1.getValueType() != MemVT) { |
1 |
| 3339 |
Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT); |
0 |
3339 |
Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT); |
0 |
| 3340 |
Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT); |
0 |
3340 |
Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT); |
0 |
| 3341 |
} |
--- |
3341 |
} |
--- |
| 3342 |
|
--- |
3342 |
|
--- |
| 3343 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
1 |
3343 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
1 |
| 3344 |
I.getType()); |
--- |
3344 |
I.getType()); |
--- |
| 3345 |
setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); |
1 |
3345 |
setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); |
1 |
| 3346 |
} |
1 |
3346 |
} |
1 |
| 3347 |
|
--- |
3347 |
|
--- |
| 3348 |
void SelectionDAGBuilder::visitFCmp(const User &I) { |
0 |
3348 |
void SelectionDAGBuilder::visitFCmp(const User &I) { |
0 |
| 3349 |
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; |
0 |
3349 |
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; |
0 |
| 3350 |
if (const FCmpInst *FC = dyn_cast(&I)) |
0 |
3350 |
if (const FCmpInst *FC = dyn_cast(&I)) |
0 |
| 3351 |
predicate = FC->getPredicate(); |
0 |
3351 |
predicate = FC->getPredicate(); |
0 |
| 3352 |
else if (const ConstantExpr *FC = dyn_cast(&I)) |
0 |
3352 |
else if (const ConstantExpr *FC = dyn_cast(&I)) |
0 |
| 3353 |
predicate = FCmpInst::Predicate(FC->getPredicate()); |
0 |
3353 |
predicate = FCmpInst::Predicate(FC->getPredicate()); |
0 |
| 3354 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
3354 |
SDValue Op1 = getValue(I.getOperand(0)); |
0 |
| 3355 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
3355 |
SDValue Op2 = getValue(I.getOperand(1)); |
0 |
| 3356 |
|
--- |
3356 |
|
--- |
| 3357 |
ISD::CondCode Condition = getFCmpCondCode(predicate); |
0 |
3357 |
ISD::CondCode Condition = getFCmpCondCode(predicate); |
0 |
| 3358 |
auto *FPMO = cast(&I); |
0 |
3358 |
auto *FPMO = cast(&I); |
0 |
| 3359 |
if (FPMO->hasNoNaNs() || TM.Options.NoNaNsFPMath) |
0 |
3359 |
if (FPMO->hasNoNaNs() || TM.Options.NoNaNsFPMath) |
0 |
| 3360 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
3360 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
| 3361 |
|
--- |
3361 |
|
--- |
| 3362 |
SDNodeFlags Flags; |
0 |
3362 |
SDNodeFlags Flags; |
0 |
| 3363 |
Flags.copyFMF(*FPMO); |
0 |
3363 |
Flags.copyFMF(*FPMO); |
0 |
| 3364 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
3364 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
| 3365 |
|
--- |
3365 |
|
--- |
| 3366 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3366 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3367 |
I.getType()); |
--- |
3367 |
I.getType()); |
--- |
| 3368 |
setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); |
0 |
3368 |
setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); |
0 |
| 3369 |
} |
0 |
3369 |
} |
0 |
| 3370 |
|
--- |
3370 |
|
--- |
| 3371 |
// Check if the condition of the select has one use or two users that are both |
--- |
3371 |
// Check if the condition of the select has one use or two users that are both |
--- |
| 3372 |
// selects with the same condition. |
--- |
3372 |
// selects with the same condition. |
--- |
| 3373 |
static bool hasOnlySelectUsers(const Value *Cond) { |
0 |
3373 |
static bool hasOnlySelectUsers(const Value *Cond) { |
0 |
| 3374 |
return llvm::all_of(Cond->users(), [](const Value *V) { |
0 |
3374 |
return llvm::all_of(Cond->users(), [](const Value *V) { |
0 |
| 3375 |
return isa(V); |
0 |
3375 |
return isa(V); |
0 |
| 3376 |
}); |
0 |
3376 |
}); |
0 |
| 3377 |
} |
--- |
3377 |
} |
--- |
| 3378 |
|
--- |
3378 |
|
--- |
| 3379 |
void SelectionDAGBuilder::visitSelect(const User &I) { |
0 |
3379 |
void SelectionDAGBuilder::visitSelect(const User &I) { |
0 |
| 3380 |
SmallVector ValueVTs; |
0 |
3380 |
SmallVector ValueVTs; |
0 |
| 3381 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), |
0 |
3381 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), |
0 |
| 3382 |
ValueVTs); |
--- |
3382 |
ValueVTs); |
--- |
| 3383 |
unsigned NumValues = ValueVTs.size(); |
0 |
3383 |
unsigned NumValues = ValueVTs.size(); |
0 |
| 3384 |
if (NumValues == 0) return; |
0 |
3384 |
if (NumValues == 0) return; |
0 |
| 3385 |
|
--- |
3385 |
|
--- |
| 3386 |
SmallVector Values(NumValues); |
0 |
3386 |
SmallVector Values(NumValues); |
0 |
| 3387 |
SDValue Cond = getValue(I.getOperand(0)); |
0 |
3387 |
SDValue Cond = getValue(I.getOperand(0)); |
0 |
| 3388 |
SDValue LHSVal = getValue(I.getOperand(1)); |
0 |
3388 |
SDValue LHSVal = getValue(I.getOperand(1)); |
0 |
| 3389 |
SDValue RHSVal = getValue(I.getOperand(2)); |
0 |
3389 |
SDValue RHSVal = getValue(I.getOperand(2)); |
0 |
| 3390 |
SmallVector BaseOps(1, Cond); |
0 |
3390 |
SmallVector BaseOps(1, Cond); |
0 |
| 3391 |
ISD::NodeType OpCode = |
--- |
3391 |
ISD::NodeType OpCode = |
--- |
| 3392 |
Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; |
0 |
3392 |
Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; |
0 |
| 3393 |
|
--- |
3393 |
|
--- |
| 3394 |
bool IsUnaryAbs = false; |
0 |
3394 |
bool IsUnaryAbs = false; |
0 |
| 3395 |
bool Negate = false; |
0 |
3395 |
bool Negate = false; |
0 |
| 3396 |
|
--- |
3396 |
|
--- |
| 3397 |
SDNodeFlags Flags; |
0 |
3397 |
SDNodeFlags Flags; |
0 |
| 3398 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
3398 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
| 3399 |
Flags.copyFMF(*FPOp); |
0 |
3399 |
Flags.copyFMF(*FPOp); |
0 |
| 3400 |
|
--- |
3400 |
|
--- |
| 3401 |
Flags.setUnpredictable( |
0 |
3401 |
Flags.setUnpredictable( |
0 |
| 3402 |
cast(I).getMetadata(LLVMContext::MD_unpredictable)); |
0 |
3402 |
cast(I).getMetadata(LLVMContext::MD_unpredictable)); |
0 |
| 3403 |
|
--- |
3403 |
|
--- |
| 3404 |
// Min/max matching is only viable if all output VTs are the same. |
--- |
3404 |
// Min/max matching is only viable if all output VTs are the same. |
--- |
| 3405 |
if (all_equal(ValueVTs)) { |
0 |
3405 |
if (all_equal(ValueVTs)) { |
0 |
| 3406 |
EVT VT = ValueVTs[0]; |
0 |
3406 |
EVT VT = ValueVTs[0]; |
0 |
| 3407 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
3407 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
| 3408 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
3408 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3409 |
|
--- |
3409 |
|
--- |
| 3410 |
// We care about the legality of the operation after it has been type |
--- |
3410 |
// We care about the legality of the operation after it has been type |
--- |
| 3411 |
// legalized. |
--- |
3411 |
// legalized. |
--- |
| 3412 |
while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal) |
0 |
3412 |
while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal) |
0 |
| 3413 |
VT = TLI.getTypeToTransformTo(Ctx, VT); |
0 |
3413 |
VT = TLI.getTypeToTransformTo(Ctx, VT); |
0 |
| 3414 |
|
--- |
3414 |
|
--- |
| 3415 |
// If the vselect is legal, assume we want to leave this as a vector setcc + |
--- |
3415 |
// If the vselect is legal, assume we want to leave this as a vector setcc + |
--- |
| 3416 |
// vselect. Otherwise, if this is going to be scalarized, we want to see if |
--- |
3416 |
// vselect. Otherwise, if this is going to be scalarized, we want to see if |
--- |
| 3417 |
// min/max is legal on the scalar type. |
--- |
3417 |
// min/max is legal on the scalar type. |
--- |
| 3418 |
bool UseScalarMinMax = VT.isVector() && |
0 |
3418 |
bool UseScalarMinMax = VT.isVector() && |
0 |
| 3419 |
!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); |
0 |
3419 |
!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); |
0 |
| 3420 |
|
--- |
3420 |
|
--- |
| 3421 |
// ValueTracking's select pattern matching does not account for -0.0, |
--- |
3421 |
// ValueTracking's select pattern matching does not account for -0.0, |
--- |
| 3422 |
// so we can't lower to FMINIMUM/FMAXIMUM because those nodes specify that |
--- |
3422 |
// so we can't lower to FMINIMUM/FMAXIMUM because those nodes specify that |
--- |
| 3423 |
// -0.0 is less than +0.0. |
--- |
3423 |
// -0.0 is less than +0.0. |
--- |
| 3424 |
Value *LHS, *RHS; |
--- |
3424 |
Value *LHS, *RHS; |
--- |
| 3425 |
auto SPR = matchSelectPattern(const_cast(&I), LHS, RHS); |
0 |
3425 |
auto SPR = matchSelectPattern(const_cast(&I), LHS, RHS); |
0 |
| 3426 |
ISD::NodeType Opc = ISD::DELETED_NODE; |
0 |
3426 |
ISD::NodeType Opc = ISD::DELETED_NODE; |
0 |
| 3427 |
switch (SPR.Flavor) { |
0 |
3427 |
switch (SPR.Flavor) { |
0 |
| 3428 |
case SPF_UMAX: Opc = ISD::UMAX; break; |
0 |
3428 |
case SPF_UMAX: Opc = ISD::UMAX; break; |
0 |
| 3429 |
case SPF_UMIN: Opc = ISD::UMIN; break; |
0 |
3429 |
case SPF_UMIN: Opc = ISD::UMIN; break; |
0 |
| 3430 |
case SPF_SMAX: Opc = ISD::SMAX; break; |
0 |
3430 |
case SPF_SMAX: Opc = ISD::SMAX; break; |
0 |
| 3431 |
case SPF_SMIN: Opc = ISD::SMIN; break; |
0 |
3431 |
case SPF_SMIN: Opc = ISD::SMIN; break; |
0 |
| 3432 |
case SPF_FMINNUM: |
0 |
3432 |
case SPF_FMINNUM: |
0 |
| 3433 |
switch (SPR.NaNBehavior) { |
0 |
3433 |
switch (SPR.NaNBehavior) { |
0 |
| 3434 |
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); |
0 |
3434 |
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); |
0 |
| 3435 |
case SPNB_RETURNS_NAN: break; |
0 |
3435 |
case SPNB_RETURNS_NAN: break; |
0 |
| 3436 |
case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; |
0 |
3436 |
case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; |
0 |
| 3437 |
case SPNB_RETURNS_ANY: |
0 |
3437 |
case SPNB_RETURNS_ANY: |
0 |
| 3438 |
if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) || |
0 |
3438 |
if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) || |
0 |
| 3439 |
(UseScalarMinMax && |
0 |
3439 |
(UseScalarMinMax && |
0 |
| 3440 |
TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()))) |
0 |
3440 |
TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()))) |
0 |
| 3441 |
Opc = ISD::FMINNUM; |
0 |
3441 |
Opc = ISD::FMINNUM; |
0 |
| 3442 |
break; |
0 |
3442 |
break; |
0 |
| 3443 |
} |
--- |
3443 |
} |
--- |
| 3444 |
break; |
0 |
3444 |
break; |
0 |
| 3445 |
case SPF_FMAXNUM: |
0 |
3445 |
case SPF_FMAXNUM: |
0 |
| 3446 |
switch (SPR.NaNBehavior) { |
0 |
3446 |
switch (SPR.NaNBehavior) { |
0 |
| 3447 |
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); |
0 |
3447 |
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); |
0 |
| 3448 |
case SPNB_RETURNS_NAN: break; |
0 |
3448 |
case SPNB_RETURNS_NAN: break; |
0 |
| 3449 |
case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; |
0 |
3449 |
case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; |
0 |
| 3450 |
case SPNB_RETURNS_ANY: |
0 |
3450 |
case SPNB_RETURNS_ANY: |
0 |
| 3451 |
if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) || |
0 |
3451 |
if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) || |
0 |
| 3452 |
(UseScalarMinMax && |
0 |
3452 |
(UseScalarMinMax && |
0 |
| 3453 |
TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()))) |
0 |
3453 |
TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()))) |
0 |
| 3454 |
Opc = ISD::FMAXNUM; |
0 |
3454 |
Opc = ISD::FMAXNUM; |
0 |
| 3455 |
break; |
0 |
3455 |
break; |
0 |
| 3456 |
} |
--- |
3456 |
} |
--- |
| 3457 |
break; |
0 |
3457 |
break; |
0 |
| 3458 |
case SPF_NABS: |
0 |
3458 |
case SPF_NABS: |
0 |
| 3459 |
Negate = true; |
0 |
3459 |
Negate = true; |
0 |
| 3460 |
[[fallthrough]]; |
--- |
3460 |
[[fallthrough]]; |
--- |
| 3461 |
case SPF_ABS: |
0 |
3461 |
case SPF_ABS: |
0 |
| 3462 |
IsUnaryAbs = true; |
0 |
3462 |
IsUnaryAbs = true; |
0 |
| 3463 |
Opc = ISD::ABS; |
0 |
3463 |
Opc = ISD::ABS; |
0 |
| 3464 |
break; |
0 |
3464 |
break; |
0 |
| 3465 |
default: break; |
0 |
3465 |
default: break; |
0 |
| 3466 |
} |
--- |
3466 |
} |
--- |
| 3467 |
|
--- |
3467 |
|
--- |
| 3468 |
if (!IsUnaryAbs && Opc != ISD::DELETED_NODE && |
0 |
3468 |
if (!IsUnaryAbs && Opc != ISD::DELETED_NODE && |
0 |
| 3469 |
(TLI.isOperationLegalOrCustom(Opc, VT) || |
0 |
3469 |
(TLI.isOperationLegalOrCustom(Opc, VT) || |
0 |
| 3470 |
(UseScalarMinMax && |
0 |
3470 |
(UseScalarMinMax && |
0 |
| 3471 |
TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) && |
0 |
3471 |
TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) && |
0 |
| 3472 |
// If the underlying comparison instruction is used by any other |
--- |
3472 |
// If the underlying comparison instruction is used by any other |
--- |
| 3473 |
// instruction, the consumed instructions won't be destroyed, so it is |
--- |
3473 |
// instruction, the consumed instructions won't be destroyed, so it is |
--- |
| 3474 |
// not profitable to convert to a min/max. |
--- |
3474 |
// not profitable to convert to a min/max. |
--- |
| 3475 |
hasOnlySelectUsers(cast(I).getCondition())) { |
0 |
3475 |
hasOnlySelectUsers(cast(I).getCondition())) { |
0 |
| 3476 |
OpCode = Opc; |
0 |
3476 |
OpCode = Opc; |
0 |
| 3477 |
LHSVal = getValue(LHS); |
0 |
3477 |
LHSVal = getValue(LHS); |
0 |
| 3478 |
RHSVal = getValue(RHS); |
0 |
3478 |
RHSVal = getValue(RHS); |
0 |
| 3479 |
BaseOps.clear(); |
0 |
3479 |
BaseOps.clear(); |
0 |
| 3480 |
} |
--- |
3480 |
} |
--- |
| 3481 |
|
--- |
3481 |
|
--- |
| 3482 |
if (IsUnaryAbs) { |
0 |
3482 |
if (IsUnaryAbs) { |
0 |
| 3483 |
OpCode = Opc; |
0 |
3483 |
OpCode = Opc; |
0 |
| 3484 |
LHSVal = getValue(LHS); |
0 |
3484 |
LHSVal = getValue(LHS); |
0 |
| 3485 |
BaseOps.clear(); |
0 |
3485 |
BaseOps.clear(); |
0 |
| 3486 |
} |
--- |
3486 |
} |
--- |
| 3487 |
} |
--- |
3487 |
} |
--- |
| 3488 |
|
--- |
3488 |
|
--- |
| 3489 |
if (IsUnaryAbs) { |
0 |
3489 |
if (IsUnaryAbs) { |
0 |
| 3490 |
for (unsigned i = 0; i != NumValues; ++i) { |
0 |
3490 |
for (unsigned i = 0; i != NumValues; ++i) { |
0 |
| 3491 |
SDLoc dl = getCurSDLoc(); |
0 |
3491 |
SDLoc dl = getCurSDLoc(); |
0 |
| 3492 |
EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); |
0 |
3492 |
EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); |
0 |
| 3493 |
Values[i] = |
0 |
3493 |
Values[i] = |
0 |
| 3494 |
DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); |
0 |
3494 |
DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); |
0 |
| 3495 |
if (Negate) |
0 |
3495 |
if (Negate) |
0 |
| 3496 |
Values[i] = DAG.getNegative(Values[i], dl, VT); |
0 |
3496 |
Values[i] = DAG.getNegative(Values[i], dl, VT); |
0 |
| 3497 |
} |
0 |
3497 |
} |
0 |
| 3498 |
} else { |
--- |
3498 |
} else { |
--- |
| 3499 |
for (unsigned i = 0; i != NumValues; ++i) { |
0 |
3499 |
for (unsigned i = 0; i != NumValues; ++i) { |
0 |
| 3500 |
SmallVector Ops(BaseOps.begin(), BaseOps.end()); |
0 |
3500 |
SmallVector Ops(BaseOps.begin(), BaseOps.end()); |
0 |
| 3501 |
Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); |
0 |
3501 |
Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); |
0 |
| 3502 |
Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); |
0 |
3502 |
Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); |
0 |
| 3503 |
Values[i] = DAG.getNode( |
0 |
3503 |
Values[i] = DAG.getNode( |
0 |
| 3504 |
OpCode, getCurSDLoc(), |
0 |
3504 |
OpCode, getCurSDLoc(), |
0 |
| 3505 |
LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags); |
0 |
3505 |
LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags); |
0 |
| 3506 |
} |
0 |
3506 |
} |
0 |
| 3507 |
} |
--- |
3507 |
} |
--- |
| 3508 |
|
--- |
3508 |
|
--- |
| 3509 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
3509 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
| 3510 |
DAG.getVTList(ValueVTs), Values)); |
0 |
3510 |
DAG.getVTList(ValueVTs), Values)); |
0 |
| 3511 |
} |
0 |
3511 |
} |
0 |
| 3512 |
|
--- |
3512 |
|
--- |
| 3513 |
void SelectionDAGBuilder::visitTrunc(const User &I) { |
0 |
3513 |
void SelectionDAGBuilder::visitTrunc(const User &I) { |
0 |
| 3514 |
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). |
--- |
3514 |
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). |
--- |
| 3515 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3515 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3516 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3516 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3517 |
I.getType()); |
--- |
3517 |
I.getType()); |
--- |
| 3518 |
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); |
0 |
3518 |
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); |
0 |
| 3519 |
} |
0 |
3519 |
} |
0 |
| 3520 |
|
--- |
3520 |
|
--- |
| 3521 |
void SelectionDAGBuilder::visitZExt(const User &I) { |
0 |
3521 |
void SelectionDAGBuilder::visitZExt(const User &I) { |
0 |
| 3522 |
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). |
--- |
3522 |
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). |
--- |
| 3523 |
// ZExt also can't be a cast to bool for same reason. So, nothing much to do |
--- |
3523 |
// ZExt also can't be a cast to bool for same reason. So, nothing much to do |
--- |
| 3524 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3524 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3525 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3525 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3526 |
I.getType()); |
--- |
3526 |
I.getType()); |
--- |
| 3527 |
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); |
0 |
3527 |
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); |
0 |
| 3528 |
} |
0 |
3528 |
} |
0 |
| 3529 |
|
--- |
3529 |
|
--- |
| 3530 |
void SelectionDAGBuilder::visitSExt(const User &I) { |
0 |
3530 |
void SelectionDAGBuilder::visitSExt(const User &I) { |
0 |
| 3531 |
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). |
--- |
3531 |
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). |
--- |
| 3532 |
// SExt also can't be a cast to bool for same reason. So, nothing much to do |
--- |
3532 |
// SExt also can't be a cast to bool for same reason. So, nothing much to do |
--- |
| 3533 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3533 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3534 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3534 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3535 |
I.getType()); |
--- |
3535 |
I.getType()); |
--- |
| 3536 |
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); |
0 |
3536 |
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); |
0 |
| 3537 |
} |
0 |
3537 |
} |
0 |
| 3538 |
|
--- |
3538 |
|
--- |
| 3539 |
void SelectionDAGBuilder::visitFPTrunc(const User &I) { |
0 |
3539 |
void SelectionDAGBuilder::visitFPTrunc(const User &I) { |
0 |
| 3540 |
// FPTrunc is never a no-op cast, no need to check |
--- |
3540 |
// FPTrunc is never a no-op cast, no need to check |
--- |
| 3541 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3541 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3542 |
SDLoc dl = getCurSDLoc(); |
0 |
3542 |
SDLoc dl = getCurSDLoc(); |
0 |
| 3543 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3543 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3544 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
3544 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 3545 |
setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, |
0 |
3545 |
setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, |
0 |
| 3546 |
DAG.getTargetConstant( |
0 |
3546 |
DAG.getTargetConstant( |
0 |
| 3547 |
0, dl, TLI.getPointerTy(DAG.getDataLayout())))); |
0 |
3547 |
0, dl, TLI.getPointerTy(DAG.getDataLayout())))); |
0 |
| 3548 |
} |
0 |
3548 |
} |
0 |
| 3549 |
|
--- |
3549 |
|
--- |
| 3550 |
void SelectionDAGBuilder::visitFPExt(const User &I) { |
0 |
3550 |
void SelectionDAGBuilder::visitFPExt(const User &I) { |
0 |
| 3551 |
// FPExt is never a no-op cast, no need to check |
--- |
3551 |
// FPExt is never a no-op cast, no need to check |
--- |
| 3552 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3552 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3553 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3553 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3554 |
I.getType()); |
--- |
3554 |
I.getType()); |
--- |
| 3555 |
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); |
0 |
3555 |
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); |
0 |
| 3556 |
} |
0 |
3556 |
} |
0 |
| 3557 |
|
--- |
3557 |
|
--- |
| 3558 |
void SelectionDAGBuilder::visitFPToUI(const User &I) { |
0 |
3558 |
void SelectionDAGBuilder::visitFPToUI(const User &I) { |
0 |
| 3559 |
// FPToUI is never a no-op cast, no need to check |
--- |
3559 |
// FPToUI is never a no-op cast, no need to check |
--- |
| 3560 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3560 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3561 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3561 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3562 |
I.getType()); |
--- |
3562 |
I.getType()); |
--- |
| 3563 |
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); |
0 |
3563 |
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); |
0 |
| 3564 |
} |
0 |
3564 |
} |
0 |
| 3565 |
|
--- |
3565 |
|
--- |
| 3566 |
void SelectionDAGBuilder::visitFPToSI(const User &I) { |
0 |
3566 |
void SelectionDAGBuilder::visitFPToSI(const User &I) { |
0 |
| 3567 |
// FPToSI is never a no-op cast, no need to check |
--- |
3567 |
// FPToSI is never a no-op cast, no need to check |
--- |
| 3568 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3568 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3569 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3569 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3570 |
I.getType()); |
--- |
3570 |
I.getType()); |
--- |
| 3571 |
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); |
0 |
3571 |
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); |
0 |
| 3572 |
} |
0 |
3572 |
} |
0 |
| 3573 |
|
--- |
3573 |
|
--- |
| 3574 |
void SelectionDAGBuilder::visitUIToFP(const User &I) { |
0 |
3574 |
void SelectionDAGBuilder::visitUIToFP(const User &I) { |
0 |
| 3575 |
// UIToFP is never a no-op cast, no need to check |
--- |
3575 |
// UIToFP is never a no-op cast, no need to check |
--- |
| 3576 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3576 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3577 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3577 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3578 |
I.getType()); |
--- |
3578 |
I.getType()); |
--- |
| 3579 |
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); |
0 |
3579 |
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); |
0 |
| 3580 |
} |
0 |
3580 |
} |
0 |
| 3581 |
|
--- |
3581 |
|
--- |
| 3582 |
void SelectionDAGBuilder::visitSIToFP(const User &I) { |
0 |
3582 |
void SelectionDAGBuilder::visitSIToFP(const User &I) { |
0 |
| 3583 |
// SIToFP is never a no-op cast, no need to check |
--- |
3583 |
// SIToFP is never a no-op cast, no need to check |
--- |
| 3584 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3584 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3585 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3585 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3586 |
I.getType()); |
--- |
3586 |
I.getType()); |
--- |
| 3587 |
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); |
0 |
3587 |
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); |
0 |
| 3588 |
} |
0 |
3588 |
} |
0 |
| 3589 |
|
--- |
3589 |
|
--- |
| 3590 |
void SelectionDAGBuilder::visitPtrToInt(const User &I) { |
0 |
3590 |
void SelectionDAGBuilder::visitPtrToInt(const User &I) { |
0 |
| 3591 |
// What to do depends on the size of the integer and the size of the pointer. |
--- |
3591 |
// What to do depends on the size of the integer and the size of the pointer. |
--- |
| 3592 |
// We can either truncate, zero extend, or no-op, accordingly. |
--- |
3592 |
// We can either truncate, zero extend, or no-op, accordingly. |
--- |
| 3593 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3593 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3594 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
3594 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3595 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3595 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3596 |
I.getType()); |
--- |
3596 |
I.getType()); |
--- |
| 3597 |
EVT PtrMemVT = |
--- |
3597 |
EVT PtrMemVT = |
--- |
| 3598 |
TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType()); |
0 |
3598 |
TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType()); |
0 |
| 3599 |
N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT); |
0 |
3599 |
N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT); |
0 |
| 3600 |
N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); |
0 |
3600 |
N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); |
0 |
| 3601 |
setValue(&I, N); |
0 |
3601 |
setValue(&I, N); |
0 |
| 3602 |
} |
0 |
3602 |
} |
0 |
| 3603 |
|
--- |
3603 |
|
--- |
| 3604 |
void SelectionDAGBuilder::visitIntToPtr(const User &I) { |
0 |
3604 |
void SelectionDAGBuilder::visitIntToPtr(const User &I) { |
0 |
| 3605 |
// What to do depends on the size of the integer and the size of the pointer. |
--- |
3605 |
// What to do depends on the size of the integer and the size of the pointer. |
--- |
| 3606 |
// We can either truncate, zero extend, or no-op, accordingly. |
--- |
3606 |
// We can either truncate, zero extend, or no-op, accordingly. |
--- |
| 3607 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3607 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3608 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
3608 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3609 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
3609 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 3610 |
EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType()); |
0 |
3610 |
EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 3611 |
N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT); |
0 |
3611 |
N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT); |
0 |
| 3612 |
N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT); |
0 |
3612 |
N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT); |
0 |
| 3613 |
setValue(&I, N); |
0 |
3613 |
setValue(&I, N); |
0 |
| 3614 |
} |
0 |
3614 |
} |
0 |
| 3615 |
|
--- |
3615 |
|
--- |
| 3616 |
void SelectionDAGBuilder::visitBitCast(const User &I) { |
0 |
3616 |
void SelectionDAGBuilder::visitBitCast(const User &I) { |
0 |
| 3617 |
SDValue N = getValue(I.getOperand(0)); |
0 |
3617 |
SDValue N = getValue(I.getOperand(0)); |
0 |
| 3618 |
SDLoc dl = getCurSDLoc(); |
0 |
3618 |
SDLoc dl = getCurSDLoc(); |
0 |
| 3619 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
3619 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 3620 |
I.getType()); |
--- |
3620 |
I.getType()); |
--- |
| 3621 |
|
--- |
3621 |
|
--- |
| 3622 |
// BitCast assures us that source and destination are the same size so this is |
--- |
3622 |
// BitCast assures us that source and destination are the same size so this is |
--- |
| 3623 |
// either a BITCAST or a no-op. |
--- |
3623 |
// either a BITCAST or a no-op. |
--- |
| 3624 |
if (DestVT != N.getValueType()) |
0 |
3624 |
if (DestVT != N.getValueType()) |
0 |
| 3625 |
setValue(&I, DAG.getNode(ISD::BITCAST, dl, |
0 |
3625 |
setValue(&I, DAG.getNode(ISD::BITCAST, dl, |
0 |
| 3626 |
DestVT, N)); // convert types. |
--- |
3626 |
DestVT, N)); // convert types. |
--- |
| 3627 |
// Check if the original LLVM IR Operand was a ConstantInt, because getValue() |
--- |
3627 |
// Check if the original LLVM IR Operand was a ConstantInt, because getValue() |
--- |
| 3628 |
// might fold any kind of constant expression to an integer constant and that |
--- |
3628 |
// might fold any kind of constant expression to an integer constant and that |
--- |
| 3629 |
// is not what we are looking for. Only recognize a bitcast of a genuine |
--- |
3629 |
// is not what we are looking for. Only recognize a bitcast of a genuine |
--- |
| 3630 |
// constant integer as an opaque constant. |
--- |
3630 |
// constant integer as an opaque constant. |
--- |
| 3631 |
else if(ConstantInt *C = dyn_cast(I.getOperand(0))) |
0 |
3631 |
else if(ConstantInt *C = dyn_cast(I.getOperand(0))) |
0 |
| 3632 |
setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false, |
0 |
3632 |
setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false, |
0 |
| 3633 |
/*isOpaque*/true)); |
--- |
3633 |
/*isOpaque*/true)); |
--- |
| 3634 |
else |
--- |
3634 |
else |
--- |
| 3635 |
setValue(&I, N); // noop cast. |
0 |
3635 |
setValue(&I, N); // noop cast. |
0 |
| 3636 |
} |
0 |
3636 |
} |
0 |
| 3637 |
|
--- |
3637 |
|
--- |
| 3638 |
void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) { |
0 |
3638 |
void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) { |
0 |
| 3639 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3639 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3640 |
const Value *SV = I.getOperand(0); |
0 |
3640 |
const Value *SV = I.getOperand(0); |
0 |
| 3641 |
SDValue N = getValue(SV); |
0 |
3641 |
SDValue N = getValue(SV); |
0 |
| 3642 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
3642 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 3643 |
|
--- |
3643 |
|
--- |
| 3644 |
unsigned SrcAS = SV->getType()->getPointerAddressSpace(); |
0 |
3644 |
unsigned SrcAS = SV->getType()->getPointerAddressSpace(); |
0 |
| 3645 |
unsigned DestAS = I.getType()->getPointerAddressSpace(); |
0 |
3645 |
unsigned DestAS = I.getType()->getPointerAddressSpace(); |
0 |
| 3646 |
|
--- |
3646 |
|
--- |
| 3647 |
if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS)) |
0 |
3647 |
if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS)) |
0 |
| 3648 |
N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS); |
0 |
3648 |
N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS); |
0 |
| 3649 |
|
--- |
3649 |
|
--- |
| 3650 |
setValue(&I, N); |
0 |
3650 |
setValue(&I, N); |
0 |
| 3651 |
} |
0 |
3651 |
} |
0 |
| 3652 |
|
--- |
3652 |
|
--- |
| 3653 |
void SelectionDAGBuilder::visitInsertElement(const User &I) { |
0 |
3653 |
void SelectionDAGBuilder::visitInsertElement(const User &I) { |
0 |
| 3654 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3654 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3655 |
SDValue InVec = getValue(I.getOperand(0)); |
0 |
3655 |
SDValue InVec = getValue(I.getOperand(0)); |
0 |
| 3656 |
SDValue InVal = getValue(I.getOperand(1)); |
0 |
3656 |
SDValue InVal = getValue(I.getOperand(1)); |
0 |
| 3657 |
SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(), |
0 |
3657 |
SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(), |
0 |
| 3658 |
TLI.getVectorIdxTy(DAG.getDataLayout())); |
0 |
3658 |
TLI.getVectorIdxTy(DAG.getDataLayout())); |
0 |
| 3659 |
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), |
0 |
3659 |
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), |
0 |
| 3660 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
3660 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
| 3661 |
InVec, InVal, InIdx)); |
--- |
3661 |
InVec, InVal, InIdx)); |
--- |
| 3662 |
} |
0 |
3662 |
} |
0 |
| 3663 |
|
--- |
3663 |
|
--- |
| 3664 |
void SelectionDAGBuilder::visitExtractElement(const User &I) { |
0 |
3664 |
void SelectionDAGBuilder::visitExtractElement(const User &I) { |
0 |
| 3665 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3665 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3666 |
SDValue InVec = getValue(I.getOperand(0)); |
0 |
3666 |
SDValue InVec = getValue(I.getOperand(0)); |
0 |
| 3667 |
SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(), |
0 |
3667 |
SDValue InIdx = DAG.getZExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(), |
0 |
| 3668 |
TLI.getVectorIdxTy(DAG.getDataLayout())); |
0 |
3668 |
TLI.getVectorIdxTy(DAG.getDataLayout())); |
0 |
| 3669 |
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), |
0 |
3669 |
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), |
0 |
| 3670 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
3670 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
| 3671 |
InVec, InIdx)); |
--- |
3671 |
InVec, InIdx)); |
--- |
| 3672 |
} |
0 |
3672 |
} |
0 |
| 3673 |
|
--- |
3673 |
|
--- |
| 3674 |
void SelectionDAGBuilder::visitShuffleVector(const User &I) { |
0 |
3674 |
void SelectionDAGBuilder::visitShuffleVector(const User &I) { |
0 |
| 3675 |
SDValue Src1 = getValue(I.getOperand(0)); |
0 |
3675 |
SDValue Src1 = getValue(I.getOperand(0)); |
0 |
| 3676 |
SDValue Src2 = getValue(I.getOperand(1)); |
0 |
3676 |
SDValue Src2 = getValue(I.getOperand(1)); |
0 |
| 3677 |
ArrayRef Mask; |
0 |
3677 |
ArrayRef Mask; |
0 |
| 3678 |
if (auto *SVI = dyn_cast(&I)) |
0 |
3678 |
if (auto *SVI = dyn_cast(&I)) |
0 |
| 3679 |
Mask = SVI->getShuffleMask(); |
0 |
3679 |
Mask = SVI->getShuffleMask(); |
0 |
| 3680 |
else |
--- |
3680 |
else |
--- |
| 3681 |
Mask = cast(I).getShuffleMask(); |
0 |
3681 |
Mask = cast(I).getShuffleMask(); |
0 |
| 3682 |
SDLoc DL = getCurSDLoc(); |
0 |
3682 |
SDLoc DL = getCurSDLoc(); |
0 |
| 3683 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3683 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3684 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
3684 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 3685 |
EVT SrcVT = Src1.getValueType(); |
0 |
3685 |
EVT SrcVT = Src1.getValueType(); |
0 |
| 3686 |
|
--- |
3686 |
|
--- |
| 3687 |
if (all_of(Mask, [](int Elem) { return Elem == 0; }) && |
0 |
3687 |
if (all_of(Mask, [](int Elem) { return Elem == 0; }) && |
0 |
| 3688 |
VT.isScalableVector()) { |
0 |
3688 |
VT.isScalableVector()) { |
0 |
| 3689 |
// Canonical splat form of first element of first input vector. |
--- |
3689 |
// Canonical splat form of first element of first input vector. |
--- |
| 3690 |
SDValue FirstElt = |
--- |
3690 |
SDValue FirstElt = |
--- |
| 3691 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcVT.getScalarType(), Src1, |
0 |
3691 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcVT.getScalarType(), Src1, |
0 |
| 3692 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
3692 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
| 3693 |
setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); |
0 |
3693 |
setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); |
0 |
| 3694 |
return; |
0 |
3694 |
return; |
0 |
| 3695 |
} |
--- |
3695 |
} |
--- |
| 3696 |
|
--- |
3696 |
|
--- |
| 3697 |
// For now, we only handle splats for scalable vectors. |
--- |
3697 |
// For now, we only handle splats for scalable vectors. |
--- |
| 3698 |
// The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation |
--- |
3698 |
// The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation |
--- |
| 3699 |
// for targets that support a SPLAT_VECTOR for non-scalable vector types. |
--- |
3699 |
// for targets that support a SPLAT_VECTOR for non-scalable vector types. |
--- |
| 3700 |
assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle"); |
0 |
3700 |
assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle"); |
0 |
| 3701 |
|
--- |
3701 |
|
--- |
| 3702 |
unsigned SrcNumElts = SrcVT.getVectorNumElements(); |
0 |
3702 |
unsigned SrcNumElts = SrcVT.getVectorNumElements(); |
0 |
| 3703 |
unsigned MaskNumElts = Mask.size(); |
0 |
3703 |
unsigned MaskNumElts = Mask.size(); |
0 |
| 3704 |
|
--- |
3704 |
|
--- |
| 3705 |
if (SrcNumElts == MaskNumElts) { |
0 |
3705 |
if (SrcNumElts == MaskNumElts) { |
0 |
| 3706 |
setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask)); |
0 |
3706 |
setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask)); |
0 |
| 3707 |
return; |
0 |
3707 |
return; |
0 |
| 3708 |
} |
--- |
3708 |
} |
--- |
| 3709 |
|
--- |
3709 |
|
--- |
| 3710 |
// Normalize the shuffle vector since mask and vector length don't match. |
--- |
3710 |
// Normalize the shuffle vector since mask and vector length don't match. |
--- |
| 3711 |
if (SrcNumElts < MaskNumElts) { |
0 |
3711 |
if (SrcNumElts < MaskNumElts) { |
0 |
| 3712 |
// Mask is longer than the source vectors. We can use concatenate vector to |
--- |
3712 |
// Mask is longer than the source vectors. We can use concatenate vector to |
--- |
| 3713 |
// make the mask and vectors lengths match. |
--- |
3713 |
// make the mask and vectors lengths match. |
--- |
| 3714 |
|
--- |
3714 |
|
--- |
| 3715 |
if (MaskNumElts % SrcNumElts == 0) { |
0 |
3715 |
if (MaskNumElts % SrcNumElts == 0) { |
0 |
| 3716 |
// Mask length is a multiple of the source vector length. |
--- |
3716 |
// Mask length is a multiple of the source vector length. |
--- |
| 3717 |
// Check if the shuffle is some kind of concatenation of the input |
--- |
3717 |
// Check if the shuffle is some kind of concatenation of the input |
--- |
| 3718 |
// vectors. |
--- |
3718 |
// vectors. |
--- |
| 3719 |
unsigned NumConcat = MaskNumElts / SrcNumElts; |
0 |
3719 |
unsigned NumConcat = MaskNumElts / SrcNumElts; |
0 |
| 3720 |
bool IsConcat = true; |
0 |
3720 |
bool IsConcat = true; |
0 |
| 3721 |
SmallVector ConcatSrcs(NumConcat, -1); |
0 |
3721 |
SmallVector ConcatSrcs(NumConcat, -1); |
0 |
| 3722 |
for (unsigned i = 0; i != MaskNumElts; ++i) { |
0 |
3722 |
for (unsigned i = 0; i != MaskNumElts; ++i) { |
0 |
| 3723 |
int Idx = Mask[i]; |
0 |
3723 |
int Idx = Mask[i]; |
0 |
| 3724 |
if (Idx < 0) |
0 |
3724 |
if (Idx < 0) |
0 |
| 3725 |
continue; |
0 |
3725 |
continue; |
0 |
| 3726 |
// Ensure the indices in each SrcVT sized piece are sequential and that |
--- |
3726 |
// Ensure the indices in each SrcVT sized piece are sequential and that |
--- |
| 3727 |
// the same source is used for the whole piece. |
--- |
3727 |
// the same source is used for the whole piece. |
--- |
| 3728 |
if ((Idx % SrcNumElts != (i % SrcNumElts)) || |
0 |
3728 |
if ((Idx % SrcNumElts != (i % SrcNumElts)) || |
0 |
| 3729 |
(ConcatSrcs[i / SrcNumElts] >= 0 && |
0 |
3729 |
(ConcatSrcs[i / SrcNumElts] >= 0 && |
0 |
| 3730 |
ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) { |
0 |
3730 |
ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) { |
0 |
| 3731 |
IsConcat = false; |
0 |
3731 |
IsConcat = false; |
0 |
| 3732 |
break; |
0 |
3732 |
break; |
0 |
| 3733 |
} |
--- |
3733 |
} |
--- |
| 3734 |
// Remember which source this index came from. |
--- |
3734 |
// Remember which source this index came from. |
--- |
| 3735 |
ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts; |
0 |
3735 |
ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts; |
0 |
| 3736 |
} |
--- |
3736 |
} |
--- |
| 3737 |
|
--- |
3737 |
|
--- |
| 3738 |
// The shuffle is concatenating multiple vectors together. Just emit |
--- |
3738 |
// The shuffle is concatenating multiple vectors together. Just emit |
--- |
| 3739 |
// a CONCAT_VECTORS operation. |
--- |
3739 |
// a CONCAT_VECTORS operation. |
--- |
| 3740 |
if (IsConcat) { |
0 |
3740 |
if (IsConcat) { |
0 |
| 3741 |
SmallVector ConcatOps; |
0 |
3741 |
SmallVector ConcatOps; |
0 |
| 3742 |
for (auto Src : ConcatSrcs) { |
0 |
3742 |
for (auto Src : ConcatSrcs) { |
0 |
| 3743 |
if (Src < 0) |
0 |
3743 |
if (Src < 0) |
0 |
| 3744 |
ConcatOps.push_back(DAG.getUNDEF(SrcVT)); |
0 |
3744 |
ConcatOps.push_back(DAG.getUNDEF(SrcVT)); |
0 |
| 3745 |
else if (Src == 0) |
0 |
3745 |
else if (Src == 0) |
0 |
| 3746 |
ConcatOps.push_back(Src1); |
0 |
3746 |
ConcatOps.push_back(Src1); |
0 |
| 3747 |
else |
--- |
3747 |
else |
--- |
| 3748 |
ConcatOps.push_back(Src2); |
0 |
3748 |
ConcatOps.push_back(Src2); |
0 |
| 3749 |
} |
--- |
3749 |
} |
--- |
| 3750 |
setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); |
0 |
3750 |
setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); |
0 |
| 3751 |
return; |
0 |
3751 |
return; |
0 |
| 3752 |
} |
0 |
3752 |
} |
0 |
| 3753 |
} |
0 |
3753 |
} |
0 |
| 3754 |
|
--- |
3754 |
|
--- |
| 3755 |
unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts); |
0 |
3755 |
unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts); |
0 |
| 3756 |
unsigned NumConcat = PaddedMaskNumElts / SrcNumElts; |
0 |
3756 |
unsigned NumConcat = PaddedMaskNumElts / SrcNumElts; |
0 |
| 3757 |
EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), |
0 |
3757 |
EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), |
0 |
| 3758 |
PaddedMaskNumElts); |
--- |
3758 |
PaddedMaskNumElts); |
--- |
| 3759 |
|
--- |
3759 |
|
--- |
| 3760 |
// Pad both vectors with undefs to make them the same length as the mask. |
--- |
3760 |
// Pad both vectors with undefs to make them the same length as the mask. |
--- |
| 3761 |
SDValue UndefVal = DAG.getUNDEF(SrcVT); |
0 |
3761 |
SDValue UndefVal = DAG.getUNDEF(SrcVT); |
0 |
| 3762 |
|
--- |
3762 |
|
--- |
| 3763 |
SmallVector MOps1(NumConcat, UndefVal); |
0 |
3763 |
SmallVector MOps1(NumConcat, UndefVal); |
0 |
| 3764 |
SmallVector MOps2(NumConcat, UndefVal); |
0 |
3764 |
SmallVector MOps2(NumConcat, UndefVal); |
0 |
| 3765 |
MOps1[0] = Src1; |
0 |
3765 |
MOps1[0] = Src1; |
0 |
| 3766 |
MOps2[0] = Src2; |
0 |
3766 |
MOps2[0] = Src2; |
0 |
| 3767 |
|
--- |
3767 |
|
--- |
| 3768 |
Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); |
0 |
3768 |
Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); |
0 |
| 3769 |
Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); |
0 |
3769 |
Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); |
0 |
| 3770 |
|
--- |
3770 |
|
--- |
| 3771 |
// Readjust mask for new input vector length. |
--- |
3771 |
// Readjust mask for new input vector length. |
--- |
| 3772 |
SmallVector MappedOps(PaddedMaskNumElts, -1); |
0 |
3772 |
SmallVector MappedOps(PaddedMaskNumElts, -1); |
0 |
| 3773 |
for (unsigned i = 0; i != MaskNumElts; ++i) { |
0 |
3773 |
for (unsigned i = 0; i != MaskNumElts; ++i) { |
0 |
| 3774 |
int Idx = Mask[i]; |
0 |
3774 |
int Idx = Mask[i]; |
0 |
| 3775 |
if (Idx >= (int)SrcNumElts) |
0 |
3775 |
if (Idx >= (int)SrcNumElts) |
0 |
| 3776 |
Idx -= SrcNumElts - PaddedMaskNumElts; |
0 |
3776 |
Idx -= SrcNumElts - PaddedMaskNumElts; |
0 |
| 3777 |
MappedOps[i] = Idx; |
0 |
3777 |
MappedOps[i] = Idx; |
0 |
| 3778 |
} |
--- |
3778 |
} |
--- |
| 3779 |
|
--- |
3779 |
|
--- |
| 3780 |
SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps); |
0 |
3780 |
SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps); |
0 |
| 3781 |
|
--- |
3781 |
|
--- |
| 3782 |
// If the concatenated vector was padded, extract a subvector with the |
--- |
3782 |
// If the concatenated vector was padded, extract a subvector with the |
--- |
| 3783 |
// correct number of elements. |
--- |
3783 |
// correct number of elements. |
--- |
| 3784 |
if (MaskNumElts != PaddedMaskNumElts) |
0 |
3784 |
if (MaskNumElts != PaddedMaskNumElts) |
0 |
| 3785 |
Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, |
0 |
3785 |
Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, |
0 |
| 3786 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
3786 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
| 3787 |
|
--- |
3787 |
|
--- |
| 3788 |
setValue(&I, Result); |
0 |
3788 |
setValue(&I, Result); |
0 |
| 3789 |
return; |
0 |
3789 |
return; |
0 |
| 3790 |
} |
0 |
3790 |
} |
0 |
| 3791 |
|
--- |
3791 |
|
--- |
| 3792 |
if (SrcNumElts > MaskNumElts) { |
0 |
3792 |
if (SrcNumElts > MaskNumElts) { |
0 |
| 3793 |
// Analyze the access pattern of the vector to see if we can extract |
--- |
3793 |
// Analyze the access pattern of the vector to see if we can extract |
--- |
| 3794 |
// two subvectors and do the shuffle. |
--- |
3794 |
// two subvectors and do the shuffle. |
--- |
| 3795 |
int StartIdx[2] = { -1, -1 }; // StartIdx to extract from |
0 |
3795 |
int StartIdx[2] = { -1, -1 }; // StartIdx to extract from |
0 |
| 3796 |
bool CanExtract = true; |
0 |
3796 |
bool CanExtract = true; |
0 |
| 3797 |
for (int Idx : Mask) { |
0 |
3797 |
for (int Idx : Mask) { |
0 |
| 3798 |
unsigned Input = 0; |
0 |
3798 |
unsigned Input = 0; |
0 |
| 3799 |
if (Idx < 0) |
0 |
3799 |
if (Idx < 0) |
0 |
| 3800 |
continue; |
0 |
3800 |
continue; |
0 |
| 3801 |
|
--- |
3801 |
|
--- |
| 3802 |
if (Idx >= (int)SrcNumElts) { |
0 |
3802 |
if (Idx >= (int)SrcNumElts) { |
0 |
| 3803 |
Input = 1; |
0 |
3803 |
Input = 1; |
0 |
| 3804 |
Idx -= SrcNumElts; |
0 |
3804 |
Idx -= SrcNumElts; |
0 |
| 3805 |
} |
--- |
3805 |
} |
--- |
| 3806 |
|
--- |
3806 |
|
--- |
| 3807 |
// If all the indices come from the same MaskNumElts sized portion of |
--- |
3807 |
// If all the indices come from the same MaskNumElts sized portion of |
--- |
| 3808 |
// the sources we can use extract. Also make sure the extract wouldn't |
--- |
3808 |
// the sources we can use extract. Also make sure the extract wouldn't |
--- |
| 3809 |
// extract past the end of the source. |
--- |
3809 |
// extract past the end of the source. |
--- |
| 3810 |
int NewStartIdx = alignDown(Idx, MaskNumElts); |
0 |
3810 |
int NewStartIdx = alignDown(Idx, MaskNumElts); |
0 |
| 3811 |
if (NewStartIdx + MaskNumElts > SrcNumElts || |
0 |
3811 |
if (NewStartIdx + MaskNumElts > SrcNumElts || |
0 |
| 3812 |
(StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx)) |
0 |
3812 |
(StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx)) |
0 |
| 3813 |
CanExtract = false; |
0 |
3813 |
CanExtract = false; |
0 |
| 3814 |
// Make sure we always update StartIdx as we use it to track if all |
--- |
3814 |
// Make sure we always update StartIdx as we use it to track if all |
--- |
| 3815 |
// elements are undef. |
--- |
3815 |
// elements are undef. |
--- |
| 3816 |
StartIdx[Input] = NewStartIdx; |
0 |
3816 |
StartIdx[Input] = NewStartIdx; |
0 |
| 3817 |
} |
--- |
3817 |
} |
--- |
| 3818 |
|
--- |
3818 |
|
--- |
| 3819 |
if (StartIdx[0] < 0 && StartIdx[1] < 0) { |
0 |
3819 |
if (StartIdx[0] < 0 && StartIdx[1] < 0) { |
0 |
| 3820 |
setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. |
0 |
3820 |
setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. |
0 |
| 3821 |
return; |
0 |
3821 |
return; |
0 |
| 3822 |
} |
--- |
3822 |
} |
--- |
| 3823 |
if (CanExtract) { |
0 |
3823 |
if (CanExtract) { |
0 |
| 3824 |
// Extract appropriate subvector and generate a vector shuffle |
--- |
3824 |
// Extract appropriate subvector and generate a vector shuffle |
--- |
| 3825 |
for (unsigned Input = 0; Input < 2; ++Input) { |
0 |
3825 |
for (unsigned Input = 0; Input < 2; ++Input) { |
0 |
| 3826 |
SDValue &Src = Input == 0 ? Src1 : Src2; |
0 |
3826 |
SDValue &Src = Input == 0 ? Src1 : Src2; |
0 |
| 3827 |
if (StartIdx[Input] < 0) |
0 |
3827 |
if (StartIdx[Input] < 0) |
0 |
| 3828 |
Src = DAG.getUNDEF(VT); |
0 |
3828 |
Src = DAG.getUNDEF(VT); |
0 |
| 3829 |
else { |
--- |
3829 |
else { |
--- |
| 3830 |
Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, |
0 |
3830 |
Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, |
0 |
| 3831 |
DAG.getVectorIdxConstant(StartIdx[Input], DL)); |
0 |
3831 |
DAG.getVectorIdxConstant(StartIdx[Input], DL)); |
0 |
| 3832 |
} |
--- |
3832 |
} |
--- |
| 3833 |
} |
--- |
3833 |
} |
--- |
| 3834 |
|
--- |
3834 |
|
--- |
| 3835 |
// Calculate new mask. |
--- |
3835 |
// Calculate new mask. |
--- |
| 3836 |
SmallVector MappedOps(Mask); |
0 |
3836 |
SmallVector MappedOps(Mask); |
0 |
| 3837 |
for (int &Idx : MappedOps) { |
0 |
3837 |
for (int &Idx : MappedOps) { |
0 |
| 3838 |
if (Idx >= (int)SrcNumElts) |
0 |
3838 |
if (Idx >= (int)SrcNumElts) |
0 |
| 3839 |
Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; |
0 |
3839 |
Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; |
0 |
| 3840 |
else if (Idx >= 0) |
0 |
3840 |
else if (Idx >= 0) |
0 |
| 3841 |
Idx -= StartIdx[0]; |
0 |
3841 |
Idx -= StartIdx[0]; |
0 |
| 3842 |
} |
--- |
3842 |
} |
--- |
| 3843 |
|
--- |
3843 |
|
--- |
| 3844 |
setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps)); |
0 |
3844 |
setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps)); |
0 |
| 3845 |
return; |
0 |
3845 |
return; |
0 |
| 3846 |
} |
0 |
3846 |
} |
0 |
| 3847 |
} |
--- |
3847 |
} |
--- |
| 3848 |
|
--- |
3848 |
|
--- |
| 3849 |
// We can't use either concat vectors or extract subvectors so fall back to |
--- |
3849 |
// We can't use either concat vectors or extract subvectors so fall back to |
--- |
| 3850 |
// replacing the shuffle with extract and build vector. |
--- |
3850 |
// replacing the shuffle with extract and build vector. |
--- |
| 3851 |
// to insert and build vector. |
--- |
3851 |
// to insert and build vector. |
--- |
| 3852 |
EVT EltVT = VT.getVectorElementType(); |
0 |
3852 |
EVT EltVT = VT.getVectorElementType(); |
0 |
| 3853 |
SmallVector Ops; |
0 |
3853 |
SmallVector Ops; |
0 |
| 3854 |
for (int Idx : Mask) { |
0 |
3854 |
for (int Idx : Mask) { |
0 |
| 3855 |
SDValue Res; |
0 |
3855 |
SDValue Res; |
0 |
| 3856 |
|
--- |
3856 |
|
--- |
| 3857 |
if (Idx < 0) { |
0 |
3857 |
if (Idx < 0) { |
0 |
| 3858 |
Res = DAG.getUNDEF(EltVT); |
0 |
3858 |
Res = DAG.getUNDEF(EltVT); |
0 |
| 3859 |
} else { |
--- |
3859 |
} else { |
--- |
| 3860 |
SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; |
0 |
3860 |
SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; |
0 |
| 3861 |
if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; |
0 |
3861 |
if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; |
0 |
| 3862 |
|
--- |
3862 |
|
--- |
| 3863 |
Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src, |
0 |
3863 |
Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src, |
0 |
| 3864 |
DAG.getVectorIdxConstant(Idx, DL)); |
0 |
3864 |
DAG.getVectorIdxConstant(Idx, DL)); |
0 |
| 3865 |
} |
--- |
3865 |
} |
--- |
| 3866 |
|
--- |
3866 |
|
--- |
| 3867 |
Ops.push_back(Res); |
0 |
3867 |
Ops.push_back(Res); |
0 |
| 3868 |
} |
--- |
3868 |
} |
--- |
| 3869 |
|
--- |
3869 |
|
--- |
| 3870 |
setValue(&I, DAG.getBuildVector(VT, DL, Ops)); |
0 |
3870 |
setValue(&I, DAG.getBuildVector(VT, DL, Ops)); |
0 |
| 3871 |
} |
0 |
3871 |
} |
0 |
| 3872 |
|
--- |
3872 |
|
--- |
| 3873 |
void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { |
0 |
3873 |
void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { |
0 |
| 3874 |
ArrayRef Indices = I.getIndices(); |
0 |
3874 |
ArrayRef Indices = I.getIndices(); |
0 |
| 3875 |
const Value *Op0 = I.getOperand(0); |
0 |
3875 |
const Value *Op0 = I.getOperand(0); |
0 |
| 3876 |
const Value *Op1 = I.getOperand(1); |
0 |
3876 |
const Value *Op1 = I.getOperand(1); |
0 |
| 3877 |
Type *AggTy = I.getType(); |
0 |
3877 |
Type *AggTy = I.getType(); |
0 |
| 3878 |
Type *ValTy = Op1->getType(); |
0 |
3878 |
Type *ValTy = Op1->getType(); |
0 |
| 3879 |
bool IntoUndef = isa(Op0); |
0 |
3879 |
bool IntoUndef = isa(Op0); |
0 |
| 3880 |
bool FromUndef = isa(Op1); |
0 |
3880 |
bool FromUndef = isa(Op1); |
0 |
| 3881 |
|
--- |
3881 |
|
--- |
| 3882 |
unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); |
0 |
3882 |
unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); |
0 |
| 3883 |
|
--- |
3883 |
|
--- |
| 3884 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3884 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3885 |
SmallVector AggValueVTs; |
0 |
3885 |
SmallVector AggValueVTs; |
0 |
| 3886 |
ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs); |
0 |
3886 |
ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs); |
0 |
| 3887 |
SmallVector ValValueVTs; |
0 |
3887 |
SmallVector ValValueVTs; |
0 |
| 3888 |
ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); |
0 |
3888 |
ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); |
0 |
| 3889 |
|
--- |
3889 |
|
--- |
| 3890 |
unsigned NumAggValues = AggValueVTs.size(); |
0 |
3890 |
unsigned NumAggValues = AggValueVTs.size(); |
0 |
| 3891 |
unsigned NumValValues = ValValueVTs.size(); |
0 |
3891 |
unsigned NumValValues = ValValueVTs.size(); |
0 |
| 3892 |
SmallVector Values(NumAggValues); |
0 |
3892 |
SmallVector Values(NumAggValues); |
0 |
| 3893 |
|
--- |
3893 |
|
--- |
| 3894 |
// Ignore an insertvalue that produces an empty object |
--- |
3894 |
// Ignore an insertvalue that produces an empty object |
--- |
| 3895 |
if (!NumAggValues) { |
0 |
3895 |
if (!NumAggValues) { |
0 |
| 3896 |
setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); |
0 |
3896 |
setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); |
0 |
| 3897 |
return; |
0 |
3897 |
return; |
0 |
| 3898 |
} |
--- |
3898 |
} |
--- |
| 3899 |
|
--- |
3899 |
|
--- |
| 3900 |
SDValue Agg = getValue(Op0); |
0 |
3900 |
SDValue Agg = getValue(Op0); |
0 |
| 3901 |
unsigned i = 0; |
0 |
3901 |
unsigned i = 0; |
0 |
| 3902 |
// Copy the beginning value(s) from the original aggregate. |
--- |
3902 |
// Copy the beginning value(s) from the original aggregate. |
--- |
| 3903 |
for (; i != LinearIndex; ++i) |
0 |
3903 |
for (; i != LinearIndex; ++i) |
0 |
| 3904 |
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : |
0 |
3904 |
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : |
0 |
| 3905 |
SDValue(Agg.getNode(), Agg.getResNo() + i); |
0 |
3905 |
SDValue(Agg.getNode(), Agg.getResNo() + i); |
0 |
| 3906 |
// Copy values from the inserted value(s). |
--- |
3906 |
// Copy values from the inserted value(s). |
--- |
| 3907 |
if (NumValValues) { |
0 |
3907 |
if (NumValValues) { |
0 |
| 3908 |
SDValue Val = getValue(Op1); |
0 |
3908 |
SDValue Val = getValue(Op1); |
0 |
| 3909 |
for (; i != LinearIndex + NumValValues; ++i) |
0 |
3909 |
for (; i != LinearIndex + NumValValues; ++i) |
0 |
| 3910 |
Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : |
0 |
3910 |
Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : |
0 |
| 3911 |
SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); |
0 |
3911 |
SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); |
0 |
| 3912 |
} |
--- |
3912 |
} |
--- |
| 3913 |
// Copy remaining value(s) from the original aggregate. |
--- |
3913 |
// Copy remaining value(s) from the original aggregate. |
--- |
| 3914 |
for (; i != NumAggValues; ++i) |
0 |
3914 |
for (; i != NumAggValues; ++i) |
0 |
| 3915 |
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : |
0 |
3915 |
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : |
0 |
| 3916 |
SDValue(Agg.getNode(), Agg.getResNo() + i); |
0 |
3916 |
SDValue(Agg.getNode(), Agg.getResNo() + i); |
0 |
| 3917 |
|
--- |
3917 |
|
--- |
| 3918 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
3918 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
| 3919 |
DAG.getVTList(AggValueVTs), Values)); |
0 |
3919 |
DAG.getVTList(AggValueVTs), Values)); |
0 |
| 3920 |
} |
0 |
3920 |
} |
0 |
| 3921 |
|
--- |
3921 |
|
--- |
| 3922 |
void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { |
0 |
3922 |
void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { |
0 |
| 3923 |
ArrayRef Indices = I.getIndices(); |
0 |
3923 |
ArrayRef Indices = I.getIndices(); |
0 |
| 3924 |
const Value *Op0 = I.getOperand(0); |
0 |
3924 |
const Value *Op0 = I.getOperand(0); |
0 |
| 3925 |
Type *AggTy = Op0->getType(); |
0 |
3925 |
Type *AggTy = Op0->getType(); |
0 |
| 3926 |
Type *ValTy = I.getType(); |
0 |
3926 |
Type *ValTy = I.getType(); |
0 |
| 3927 |
bool OutOfUndef = isa(Op0); |
0 |
3927 |
bool OutOfUndef = isa(Op0); |
0 |
| 3928 |
|
--- |
3928 |
|
--- |
| 3929 |
unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); |
0 |
3929 |
unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); |
0 |
| 3930 |
|
--- |
3930 |
|
--- |
| 3931 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
3931 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3932 |
SmallVector ValValueVTs; |
0 |
3932 |
SmallVector ValValueVTs; |
0 |
| 3933 |
ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); |
0 |
3933 |
ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); |
0 |
| 3934 |
|
--- |
3934 |
|
--- |
| 3935 |
unsigned NumValValues = ValValueVTs.size(); |
0 |
3935 |
unsigned NumValValues = ValValueVTs.size(); |
0 |
| 3936 |
|
--- |
3936 |
|
--- |
| 3937 |
// Ignore a extractvalue that produces an empty object |
--- |
3937 |
// Ignore a extractvalue that produces an empty object |
--- |
| 3938 |
if (!NumValValues) { |
0 |
3938 |
if (!NumValValues) { |
0 |
| 3939 |
setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); |
0 |
3939 |
setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); |
0 |
| 3940 |
return; |
0 |
3940 |
return; |
0 |
| 3941 |
} |
--- |
3941 |
} |
--- |
| 3942 |
|
--- |
3942 |
|
--- |
| 3943 |
SmallVector Values(NumValValues); |
0 |
3943 |
SmallVector Values(NumValValues); |
0 |
| 3944 |
|
--- |
3944 |
|
--- |
| 3945 |
SDValue Agg = getValue(Op0); |
0 |
3945 |
SDValue Agg = getValue(Op0); |
0 |
| 3946 |
// Copy out the selected value(s). |
--- |
3946 |
// Copy out the selected value(s). |
--- |
| 3947 |
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) |
0 |
3947 |
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) |
0 |
| 3948 |
Values[i - LinearIndex] = |
0 |
3948 |
Values[i - LinearIndex] = |
0 |
| 3949 |
OutOfUndef ? |
0 |
3949 |
OutOfUndef ? |
0 |
| 3950 |
DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : |
0 |
3950 |
DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : |
0 |
| 3951 |
SDValue(Agg.getNode(), Agg.getResNo() + i); |
0 |
3951 |
SDValue(Agg.getNode(), Agg.getResNo() + i); |
0 |
| 3952 |
|
--- |
3952 |
|
--- |
| 3953 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
3953 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
| 3954 |
DAG.getVTList(ValValueVTs), Values)); |
0 |
3954 |
DAG.getVTList(ValValueVTs), Values)); |
0 |
| 3955 |
} |
0 |
3955 |
} |
0 |
| 3956 |
|
--- |
3956 |
|
--- |
| 3957 |
void SelectionDAGBuilder::visitGetElementPtr(const User &I) { |
0 |
3957 |
void SelectionDAGBuilder::visitGetElementPtr(const User &I) { |
0 |
| 3958 |
Value *Op0 = I.getOperand(0); |
0 |
3958 |
Value *Op0 = I.getOperand(0); |
0 |
| 3959 |
// Note that the pointer operand may be a vector of pointers. Take the scalar |
--- |
3959 |
// Note that the pointer operand may be a vector of pointers. Take the scalar |
--- |
| 3960 |
// element which holds a pointer. |
--- |
3960 |
// element which holds a pointer. |
--- |
| 3961 |
unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
3961 |
unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
| 3962 |
SDValue N = getValue(Op0); |
0 |
3962 |
SDValue N = getValue(Op0); |
0 |
| 3963 |
SDLoc dl = getCurSDLoc(); |
0 |
3963 |
SDLoc dl = getCurSDLoc(); |
0 |
| 3964 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
3964 |
auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 3965 |
|
--- |
3965 |
|
--- |
| 3966 |
// Normalize Vector GEP - all scalar operands should be converted to the |
--- |
3966 |
// Normalize Vector GEP - all scalar operands should be converted to the |
--- |
| 3967 |
// splat vector. |
--- |
3967 |
// splat vector. |
--- |
| 3968 |
bool IsVectorGEP = I.getType()->isVectorTy(); |
0 |
3968 |
bool IsVectorGEP = I.getType()->isVectorTy(); |
0 |
| 3969 |
ElementCount VectorElementCount = |
--- |
3969 |
ElementCount VectorElementCount = |
--- |
| 3970 |
IsVectorGEP ? cast(I.getType())->getElementCount() |
0 |
3970 |
IsVectorGEP ? cast(I.getType())->getElementCount() |
0 |
| 3971 |
: ElementCount::getFixed(0); |
0 |
3971 |
: ElementCount::getFixed(0); |
0 |
| 3972 |
|
--- |
3972 |
|
--- |
| 3973 |
if (IsVectorGEP && !N.getValueType().isVector()) { |
0 |
3973 |
if (IsVectorGEP && !N.getValueType().isVector()) { |
0 |
| 3974 |
LLVMContext &Context = *DAG.getContext(); |
0 |
3974 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 3975 |
EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorElementCount); |
0 |
3975 |
EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorElementCount); |
0 |
| 3976 |
N = DAG.getSplat(VT, dl, N); |
0 |
3976 |
N = DAG.getSplat(VT, dl, N); |
0 |
| 3977 |
} |
--- |
3977 |
} |
--- |
| 3978 |
|
--- |
3978 |
|
--- |
| 3979 |
for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I); |
0 |
3979 |
for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I); |
0 |
| 3980 |
GTI != E; ++GTI) { |
0 |
3980 |
GTI != E; ++GTI) { |
0 |
| 3981 |
const Value *Idx = GTI.getOperand(); |
0 |
3981 |
const Value *Idx = GTI.getOperand(); |
0 |
| 3982 |
if (StructType *StTy = GTI.getStructTypeOrNull()) { |
0 |
3982 |
if (StructType *StTy = GTI.getStructTypeOrNull()) { |
0 |
| 3983 |
unsigned Field = cast(Idx)->getUniqueInteger().getZExtValue(); |
0 |
3983 |
unsigned Field = cast(Idx)->getUniqueInteger().getZExtValue(); |
0 |
| 3984 |
if (Field) { |
0 |
3984 |
if (Field) { |
0 |
| 3985 |
// N = N + Offset |
--- |
3985 |
// N = N + Offset |
--- |
| 3986 |
uint64_t Offset = |
--- |
3986 |
uint64_t Offset = |
--- |
| 3987 |
DAG.getDataLayout().getStructLayout(StTy)->getElementOffset(Field); |
0 |
3987 |
DAG.getDataLayout().getStructLayout(StTy)->getElementOffset(Field); |
0 |
| 3988 |
|
--- |
3988 |
|
--- |
| 3989 |
// In an inbounds GEP with an offset that is nonnegative even when |
--- |
3989 |
// In an inbounds GEP with an offset that is nonnegative even when |
--- |
| 3990 |
// interpreted as signed, assume there is no unsigned overflow. |
--- |
3990 |
// interpreted as signed, assume there is no unsigned overflow. |
--- |
| 3991 |
SDNodeFlags Flags; |
0 |
3991 |
SDNodeFlags Flags; |
0 |
| 3992 |
if (int64_t(Offset) >= 0 && cast(I).isInBounds()) |
0 |
3992 |
if (int64_t(Offset) >= 0 && cast(I).isInBounds()) |
0 |
| 3993 |
Flags.setNoUnsignedWrap(true); |
0 |
3993 |
Flags.setNoUnsignedWrap(true); |
0 |
| 3994 |
|
--- |
3994 |
|
--- |
| 3995 |
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, |
0 |
3995 |
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, |
0 |
| 3996 |
DAG.getConstant(Offset, dl, N.getValueType()), Flags); |
0 |
3996 |
DAG.getConstant(Offset, dl, N.getValueType()), Flags); |
0 |
| 3997 |
} |
--- |
3997 |
} |
--- |
| 3998 |
} else { |
--- |
3998 |
} else { |
--- |
| 3999 |
// IdxSize is the width of the arithmetic according to IR semantics. |
--- |
3999 |
// IdxSize is the width of the arithmetic according to IR semantics. |
--- |
| 4000 |
// In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth |
--- |
4000 |
// In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth |
--- |
| 4001 |
// (and fix up the result later). |
--- |
4001 |
// (and fix up the result later). |
--- |
| 4002 |
unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS); |
0 |
4002 |
unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS); |
0 |
| 4003 |
MVT IdxTy = MVT::getIntegerVT(IdxSize); |
0 |
4003 |
MVT IdxTy = MVT::getIntegerVT(IdxSize); |
0 |
| 4004 |
TypeSize ElementSize = |
--- |
4004 |
TypeSize ElementSize = |
--- |
| 4005 |
DAG.getDataLayout().getTypeAllocSize(GTI.getIndexedType()); |
0 |
4005 |
DAG.getDataLayout().getTypeAllocSize(GTI.getIndexedType()); |
0 |
| 4006 |
// We intentionally mask away the high bits here; ElementSize may not |
--- |
4006 |
// We intentionally mask away the high bits here; ElementSize may not |
--- |
| 4007 |
// fit in IdxTy. |
--- |
4007 |
// fit in IdxTy. |
--- |
| 4008 |
APInt ElementMul(IdxSize, ElementSize.getKnownMinValue()); |
0 |
4008 |
APInt ElementMul(IdxSize, ElementSize.getKnownMinValue()); |
0 |
| 4009 |
bool ElementScalable = ElementSize.isScalable(); |
0 |
4009 |
bool ElementScalable = ElementSize.isScalable(); |
0 |
| 4010 |
|
--- |
4010 |
|
--- |
| 4011 |
// If this is a scalar constant or a splat vector of constants, |
--- |
4011 |
// If this is a scalar constant or a splat vector of constants, |
--- |
| 4012 |
// handle it quickly. |
--- |
4012 |
// handle it quickly. |
--- |
| 4013 |
const auto *C = dyn_cast(Idx); |
0 |
4013 |
const auto *C = dyn_cast(Idx); |
0 |
| 4014 |
if (C && isa(C->getType())) |
0 |
4014 |
if (C && isa(C->getType())) |
0 |
| 4015 |
C = C->getSplatValue(); |
0 |
4015 |
C = C->getSplatValue(); |
0 |
| 4016 |
|
--- |
4016 |
|
--- |
| 4017 |
const auto *CI = dyn_cast_or_null(C); |
0 |
4017 |
const auto *CI = dyn_cast_or_null(C); |
0 |
| 4018 |
if (CI && CI->isZero()) |
0 |
4018 |
if (CI && CI->isZero()) |
0 |
| 4019 |
continue; |
0 |
4019 |
continue; |
0 |
| 4020 |
if (CI && !ElementScalable) { |
0 |
4020 |
if (CI && !ElementScalable) { |
0 |
| 4021 |
APInt Offs = ElementMul * CI->getValue().sextOrTrunc(IdxSize); |
0 |
4021 |
APInt Offs = ElementMul * CI->getValue().sextOrTrunc(IdxSize); |
0 |
| 4022 |
LLVMContext &Context = *DAG.getContext(); |
0 |
4022 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 4023 |
SDValue OffsVal; |
0 |
4023 |
SDValue OffsVal; |
0 |
| 4024 |
if (IsVectorGEP) |
0 |
4024 |
if (IsVectorGEP) |
0 |
| 4025 |
OffsVal = DAG.getConstant( |
0 |
4025 |
OffsVal = DAG.getConstant( |
0 |
| 4026 |
Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorElementCount)); |
--- |
4026 |
Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorElementCount)); |
--- |
| 4027 |
else |
--- |
4027 |
else |
--- |
| 4028 |
OffsVal = DAG.getConstant(Offs, dl, IdxTy); |
0 |
4028 |
OffsVal = DAG.getConstant(Offs, dl, IdxTy); |
0 |
| 4029 |
|
--- |
4029 |
|
--- |
| 4030 |
// In an inbounds GEP with an offset that is nonnegative even when |
--- |
4030 |
// In an inbounds GEP with an offset that is nonnegative even when |
--- |
| 4031 |
// interpreted as signed, assume there is no unsigned overflow. |
--- |
4031 |
// interpreted as signed, assume there is no unsigned overflow. |
--- |
| 4032 |
SDNodeFlags Flags; |
0 |
4032 |
SDNodeFlags Flags; |
0 |
| 4033 |
if (Offs.isNonNegative() && cast(I).isInBounds()) |
0 |
4033 |
if (Offs.isNonNegative() && cast(I).isInBounds()) |
0 |
| 4034 |
Flags.setNoUnsignedWrap(true); |
0 |
4034 |
Flags.setNoUnsignedWrap(true); |
0 |
| 4035 |
|
--- |
4035 |
|
--- |
| 4036 |
OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType()); |
0 |
4036 |
OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType()); |
0 |
| 4037 |
|
--- |
4037 |
|
--- |
| 4038 |
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags); |
0 |
4038 |
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags); |
0 |
| 4039 |
continue; |
0 |
4039 |
continue; |
0 |
| 4040 |
} |
0 |
4040 |
} |
0 |
| 4041 |
|
--- |
4041 |
|
--- |
| 4042 |
// N = N + Idx * ElementMul; |
--- |
4042 |
// N = N + Idx * ElementMul; |
--- |
| 4043 |
SDValue IdxN = getValue(Idx); |
0 |
4043 |
SDValue IdxN = getValue(Idx); |
0 |
| 4044 |
|
--- |
4044 |
|
--- |
| 4045 |
if (!IdxN.getValueType().isVector() && IsVectorGEP) { |
0 |
4045 |
if (!IdxN.getValueType().isVector() && IsVectorGEP) { |
0 |
| 4046 |
EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), |
0 |
4046 |
EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), |
0 |
| 4047 |
VectorElementCount); |
--- |
4047 |
VectorElementCount); |
--- |
| 4048 |
IdxN = DAG.getSplat(VT, dl, IdxN); |
0 |
4048 |
IdxN = DAG.getSplat(VT, dl, IdxN); |
0 |
| 4049 |
} |
--- |
4049 |
} |
--- |
| 4050 |
|
--- |
4050 |
|
--- |
| 4051 |
// If the index is smaller or larger than intptr_t, truncate or extend |
--- |
4051 |
// If the index is smaller or larger than intptr_t, truncate or extend |
--- |
| 4052 |
// it. |
--- |
4052 |
// it. |
--- |
| 4053 |
IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType()); |
0 |
4053 |
IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType()); |
0 |
| 4054 |
|
--- |
4054 |
|
--- |
| 4055 |
if (ElementScalable) { |
0 |
4055 |
if (ElementScalable) { |
0 |
| 4056 |
EVT VScaleTy = N.getValueType().getScalarType(); |
0 |
4056 |
EVT VScaleTy = N.getValueType().getScalarType(); |
0 |
| 4057 |
SDValue VScale = DAG.getNode( |
0 |
4057 |
SDValue VScale = DAG.getNode( |
0 |
| 4058 |
ISD::VSCALE, dl, VScaleTy, |
--- |
4058 |
ISD::VSCALE, dl, VScaleTy, |
--- |
| 4059 |
DAG.getConstant(ElementMul.getZExtValue(), dl, VScaleTy)); |
0 |
4059 |
DAG.getConstant(ElementMul.getZExtValue(), dl, VScaleTy)); |
0 |
| 4060 |
if (IsVectorGEP) |
0 |
4060 |
if (IsVectorGEP) |
0 |
| 4061 |
VScale = DAG.getSplatVector(N.getValueType(), dl, VScale); |
0 |
4061 |
VScale = DAG.getSplatVector(N.getValueType(), dl, VScale); |
0 |
| 4062 |
IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale); |
0 |
4062 |
IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale); |
0 |
| 4063 |
} else { |
--- |
4063 |
} else { |
--- |
| 4064 |
// If this is a multiply by a power of two, turn it into a shl |
--- |
4064 |
// If this is a multiply by a power of two, turn it into a shl |
--- |
| 4065 |
// immediately. This is a very common case. |
--- |
4065 |
// immediately. This is a very common case. |
--- |
| 4066 |
if (ElementMul != 1) { |
0 |
4066 |
if (ElementMul != 1) { |
0 |
| 4067 |
if (ElementMul.isPowerOf2()) { |
0 |
4067 |
if (ElementMul.isPowerOf2()) { |
0 |
| 4068 |
unsigned Amt = ElementMul.logBase2(); |
0 |
4068 |
unsigned Amt = ElementMul.logBase2(); |
0 |
| 4069 |
IdxN = DAG.getNode(ISD::SHL, dl, |
0 |
4069 |
IdxN = DAG.getNode(ISD::SHL, dl, |
0 |
| 4070 |
N.getValueType(), IdxN, |
--- |
4070 |
N.getValueType(), IdxN, |
--- |
| 4071 |
DAG.getConstant(Amt, dl, IdxN.getValueType())); |
0 |
4071 |
DAG.getConstant(Amt, dl, IdxN.getValueType())); |
0 |
| 4072 |
} else { |
--- |
4072 |
} else { |
--- |
| 4073 |
SDValue Scale = DAG.getConstant(ElementMul.getZExtValue(), dl, |
0 |
4073 |
SDValue Scale = DAG.getConstant(ElementMul.getZExtValue(), dl, |
0 |
| 4074 |
IdxN.getValueType()); |
--- |
4074 |
IdxN.getValueType()); |
--- |
| 4075 |
IdxN = DAG.getNode(ISD::MUL, dl, |
0 |
4075 |
IdxN = DAG.getNode(ISD::MUL, dl, |
0 |
| 4076 |
N.getValueType(), IdxN, Scale); |
--- |
4076 |
N.getValueType(), IdxN, Scale); |
--- |
| 4077 |
} |
--- |
4077 |
} |
--- |
| 4078 |
} |
--- |
4078 |
} |
--- |
| 4079 |
} |
--- |
4079 |
} |
--- |
| 4080 |
|
--- |
4080 |
|
--- |
| 4081 |
N = DAG.getNode(ISD::ADD, dl, |
0 |
4081 |
N = DAG.getNode(ISD::ADD, dl, |
0 |
| 4082 |
N.getValueType(), N, IdxN); |
--- |
4082 |
N.getValueType(), N, IdxN); |
--- |
| 4083 |
} |
0 |
4083 |
} |
0 |
| 4084 |
} |
--- |
4084 |
} |
--- |
| 4085 |
|
--- |
4085 |
|
--- |
| 4086 |
MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS); |
0 |
4086 |
MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS); |
0 |
| 4087 |
MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS); |
0 |
4087 |
MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS); |
0 |
| 4088 |
if (IsVectorGEP) { |
0 |
4088 |
if (IsVectorGEP) { |
0 |
| 4089 |
PtrTy = MVT::getVectorVT(PtrTy, VectorElementCount); |
0 |
4089 |
PtrTy = MVT::getVectorVT(PtrTy, VectorElementCount); |
0 |
| 4090 |
PtrMemTy = MVT::getVectorVT(PtrMemTy, VectorElementCount); |
0 |
4090 |
PtrMemTy = MVT::getVectorVT(PtrMemTy, VectorElementCount); |
0 |
| 4091 |
} |
--- |
4091 |
} |
--- |
| 4092 |
|
--- |
4092 |
|
--- |
| 4093 |
if (PtrMemTy != PtrTy && !cast(I).isInBounds()) |
0 |
4093 |
if (PtrMemTy != PtrTy && !cast(I).isInBounds()) |
0 |
| 4094 |
N = DAG.getPtrExtendInReg(N, dl, PtrMemTy); |
0 |
4094 |
N = DAG.getPtrExtendInReg(N, dl, PtrMemTy); |
0 |
| 4095 |
|
--- |
4095 |
|
--- |
| 4096 |
setValue(&I, N); |
0 |
4096 |
setValue(&I, N); |
0 |
| 4097 |
} |
0 |
4097 |
} |
0 |
| 4098 |
|
--- |
4098 |
|
--- |
| 4099 |
void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { |
3 |
4099 |
void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { |
3 |
| 4100 |
// If this is a fixed sized alloca in the entry block of the function, |
--- |
4100 |
// If this is a fixed sized alloca in the entry block of the function, |
--- |
| 4101 |
// allocate it statically on the stack. |
--- |
4101 |
// allocate it statically on the stack. |
--- |
| 4102 |
if (FuncInfo.StaticAllocaMap.count(&I)) |
3 |
4102 |
if (FuncInfo.StaticAllocaMap.count(&I)) |
3 |
| 4103 |
return; // getValue will auto-populate this. |
3 |
4103 |
return; // getValue will auto-populate this. |
3 |
| 4104 |
|
--- |
4104 |
|
--- |
| 4105 |
SDLoc dl = getCurSDLoc(); |
0 |
4105 |
SDLoc dl = getCurSDLoc(); |
0 |
| 4106 |
Type *Ty = I.getAllocatedType(); |
0 |
4106 |
Type *Ty = I.getAllocatedType(); |
0 |
| 4107 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4107 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4108 |
auto &DL = DAG.getDataLayout(); |
0 |
4108 |
auto &DL = DAG.getDataLayout(); |
0 |
| 4109 |
TypeSize TySize = DL.getTypeAllocSize(Ty); |
0 |
4109 |
TypeSize TySize = DL.getTypeAllocSize(Ty); |
0 |
| 4110 |
MaybeAlign Alignment = std::max(DL.getPrefTypeAlign(Ty), I.getAlign()); |
0 |
4110 |
MaybeAlign Alignment = std::max(DL.getPrefTypeAlign(Ty), I.getAlign()); |
0 |
| 4111 |
|
--- |
4111 |
|
--- |
| 4112 |
SDValue AllocSize = getValue(I.getArraySize()); |
0 |
4112 |
SDValue AllocSize = getValue(I.getArraySize()); |
0 |
| 4113 |
|
--- |
4113 |
|
--- |
| 4114 |
EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), I.getAddressSpace()); |
0 |
4114 |
EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), I.getAddressSpace()); |
0 |
| 4115 |
if (AllocSize.getValueType() != IntPtr) |
0 |
4115 |
if (AllocSize.getValueType() != IntPtr) |
0 |
| 4116 |
AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr); |
0 |
4116 |
AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr); |
0 |
| 4117 |
|
--- |
4117 |
|
--- |
| 4118 |
if (TySize.isScalable()) |
0 |
4118 |
if (TySize.isScalable()) |
0 |
| 4119 |
AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize, |
0 |
4119 |
AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize, |
0 |
| 4120 |
DAG.getVScale(dl, IntPtr, |
0 |
4120 |
DAG.getVScale(dl, IntPtr, |
0 |
| 4121 |
APInt(IntPtr.getScalarSizeInBits(), |
0 |
4121 |
APInt(IntPtr.getScalarSizeInBits(), |
0 |
| 4122 |
TySize.getKnownMinValue()))); |
--- |
4122 |
TySize.getKnownMinValue()))); |
--- |
| 4123 |
else |
--- |
4123 |
else |
--- |
| 4124 |
AllocSize = |
0 |
4124 |
AllocSize = |
0 |
| 4125 |
DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize, |
0 |
4125 |
DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize, |
0 |
| 4126 |
DAG.getConstant(TySize.getFixedValue(), dl, IntPtr)); |
0 |
4126 |
DAG.getConstant(TySize.getFixedValue(), dl, IntPtr)); |
0 |
| 4127 |
|
--- |
4127 |
|
--- |
| 4128 |
// Handle alignment. If the requested alignment is less than or equal to |
--- |
4128 |
// Handle alignment. If the requested alignment is less than or equal to |
--- |
| 4129 |
// the stack alignment, ignore it. If the size is greater than or equal to |
--- |
4129 |
// the stack alignment, ignore it. If the size is greater than or equal to |
--- |
| 4130 |
// the stack alignment, we note this in the DYNAMIC_STACKALLOC node. |
--- |
4130 |
// the stack alignment, we note this in the DYNAMIC_STACKALLOC node. |
--- |
| 4131 |
Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign(); |
0 |
4131 |
Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign(); |
0 |
| 4132 |
if (*Alignment <= StackAlign) |
0 |
4132 |
if (*Alignment <= StackAlign) |
0 |
| 4133 |
Alignment = std::nullopt; |
0 |
4133 |
Alignment = std::nullopt; |
0 |
| 4134 |
|
--- |
4134 |
|
--- |
| 4135 |
const uint64_t StackAlignMask = StackAlign.value() - 1U; |
0 |
4135 |
const uint64_t StackAlignMask = StackAlign.value() - 1U; |
0 |
| 4136 |
// Round the size of the allocation up to the stack alignment size |
--- |
4136 |
// Round the size of the allocation up to the stack alignment size |
--- |
| 4137 |
// by add SA-1 to the size. This doesn't overflow because we're computing |
--- |
4137 |
// by add SA-1 to the size. This doesn't overflow because we're computing |
--- |
| 4138 |
// an address inside an alloca. |
--- |
4138 |
// an address inside an alloca. |
--- |
| 4139 |
SDNodeFlags Flags; |
0 |
4139 |
SDNodeFlags Flags; |
0 |
| 4140 |
Flags.setNoUnsignedWrap(true); |
0 |
4140 |
Flags.setNoUnsignedWrap(true); |
0 |
| 4141 |
AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize, |
0 |
4141 |
AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize, |
0 |
| 4142 |
DAG.getConstant(StackAlignMask, dl, IntPtr), Flags); |
0 |
4142 |
DAG.getConstant(StackAlignMask, dl, IntPtr), Flags); |
0 |
| 4143 |
|
--- |
4143 |
|
--- |
| 4144 |
// Mask out the low bits for alignment purposes. |
--- |
4144 |
// Mask out the low bits for alignment purposes. |
--- |
| 4145 |
AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize, |
0 |
4145 |
AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize, |
0 |
| 4146 |
DAG.getConstant(~StackAlignMask, dl, IntPtr)); |
0 |
4146 |
DAG.getConstant(~StackAlignMask, dl, IntPtr)); |
0 |
| 4147 |
|
--- |
4147 |
|
--- |
| 4148 |
SDValue Ops[] = { |
--- |
4148 |
SDValue Ops[] = { |
--- |
| 4149 |
getRoot(), AllocSize, |
0 |
4149 |
getRoot(), AllocSize, |
0 |
| 4150 |
DAG.getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)}; |
0 |
4150 |
DAG.getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)}; |
0 |
| 4151 |
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); |
0 |
4151 |
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); |
0 |
| 4152 |
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops); |
0 |
4152 |
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops); |
0 |
| 4153 |
setValue(&I, DSA); |
0 |
4153 |
setValue(&I, DSA); |
0 |
| 4154 |
DAG.setRoot(DSA.getValue(1)); |
0 |
4154 |
DAG.setRoot(DSA.getValue(1)); |
0 |
| 4155 |
|
--- |
4155 |
|
--- |
| 4156 |
assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects()); |
0 |
4156 |
assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects()); |
0 |
| 4157 |
} |
0 |
4157 |
} |
0 |
| 4158 |
|
--- |
4158 |
|
--- |
| 4159 |
void SelectionDAGBuilder::visitLoad(const LoadInst &I) { |
5 |
4159 |
void SelectionDAGBuilder::visitLoad(const LoadInst &I) { |
5 |
| 4160 |
if (I.isAtomic()) |
5 |
4160 |
if (I.isAtomic()) |
5 |
| 4161 |
return visitAtomicLoad(I); |
0 |
4161 |
return visitAtomicLoad(I); |
0 |
| 4162 |
|
--- |
4162 |
|
--- |
| 4163 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
5 |
4163 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
5 |
| 4164 |
const Value *SV = I.getOperand(0); |
5 |
4164 |
const Value *SV = I.getOperand(0); |
5 |
| 4165 |
if (TLI.supportSwiftError()) { |
5 |
4165 |
if (TLI.supportSwiftError()) { |
5 |
| 4166 |
// Swifterror values can come from either a function parameter with |
--- |
4166 |
// Swifterror values can come from either a function parameter with |
--- |
| 4167 |
// swifterror attribute or an alloca with swifterror attribute. |
--- |
4167 |
// swifterror attribute or an alloca with swifterror attribute. |
--- |
| 4168 |
if (const Argument *Arg = dyn_cast(SV)) { |
0 |
4168 |
if (const Argument *Arg = dyn_cast(SV)) { |
0 |
| 4169 |
if (Arg->hasSwiftErrorAttr()) |
0 |
4169 |
if (Arg->hasSwiftErrorAttr()) |
0 |
| 4170 |
return visitLoadFromSwiftError(I); |
0 |
4170 |
return visitLoadFromSwiftError(I); |
0 |
| 4171 |
} |
--- |
4171 |
} |
--- |
| 4172 |
|
--- |
4172 |
|
--- |
| 4173 |
if (const AllocaInst *Alloca = dyn_cast(SV)) { |
0 |
4173 |
if (const AllocaInst *Alloca = dyn_cast(SV)) { |
0 |
| 4174 |
if (Alloca->isSwiftError()) |
0 |
4174 |
if (Alloca->isSwiftError()) |
0 |
| 4175 |
return visitLoadFromSwiftError(I); |
0 |
4175 |
return visitLoadFromSwiftError(I); |
0 |
| 4176 |
} |
--- |
4176 |
} |
--- |
| 4177 |
} |
--- |
4177 |
} |
--- |
| 4178 |
|
--- |
4178 |
|
--- |
| 4179 |
SDValue Ptr = getValue(SV); |
5 |
4179 |
SDValue Ptr = getValue(SV); |
5 |
| 4180 |
|
--- |
4180 |
|
--- |
| 4181 |
Type *Ty = I.getType(); |
5 |
4181 |
Type *Ty = I.getType(); |
5 |
| 4182 |
SmallVector ValueVTs, MemVTs; |
5 |
4182 |
SmallVector ValueVTs, MemVTs; |
5 |
| 4183 |
SmallVector Offsets; |
5 |
4183 |
SmallVector Offsets; |
5 |
| 4184 |
ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets, 0); |
5 |
4184 |
ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets, 0); |
5 |
| 4185 |
unsigned NumValues = ValueVTs.size(); |
5 |
4185 |
unsigned NumValues = ValueVTs.size(); |
5 |
| 4186 |
if (NumValues == 0) |
5 |
4186 |
if (NumValues == 0) |
5 |
| 4187 |
return; |
0 |
4187 |
return; |
0 |
| 4188 |
|
--- |
4188 |
|
--- |
| 4189 |
Align Alignment = I.getAlign(); |
5 |
4189 |
Align Alignment = I.getAlign(); |
5 |
| 4190 |
AAMDNodes AAInfo = I.getAAMetadata(); |
5 |
4190 |
AAMDNodes AAInfo = I.getAAMetadata(); |
5 |
| 4191 |
const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); |
5 |
4191 |
const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); |
5 |
| 4192 |
bool isVolatile = I.isVolatile(); |
5 |
4192 |
bool isVolatile = I.isVolatile(); |
5 |
| 4193 |
MachineMemOperand::Flags MMOFlags = |
--- |
4193 |
MachineMemOperand::Flags MMOFlags = |
--- |
| 4194 |
TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo); |
5 |
4194 |
TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo); |
5 |
| 4195 |
|
--- |
4195 |
|
--- |
| 4196 |
SDValue Root; |
5 |
4196 |
SDValue Root; |
5 |
| 4197 |
bool ConstantMemory = false; |
5 |
4197 |
bool ConstantMemory = false; |
5 |
| 4198 |
if (isVolatile) |
5 |
4198 |
if (isVolatile) |
5 |
| 4199 |
// Serialize volatile loads with other side effects. |
--- |
4199 |
// Serialize volatile loads with other side effects. |
--- |
| 4200 |
Root = getRoot(); |
0 |
4200 |
Root = getRoot(); |
0 |
| 4201 |
else if (NumValues > MaxParallelChains) |
5 |
4201 |
else if (NumValues > MaxParallelChains) |
5 |
| 4202 |
Root = getMemoryRoot(); |
0 |
4202 |
Root = getMemoryRoot(); |
0 |
| 4203 |
else if (AA && |
5 |
4203 |
else if (AA && |
5 |
| 4204 |
AA->pointsToConstantMemory(MemoryLocation( |
5 |
4204 |
AA->pointsToConstantMemory(MemoryLocation( |
5 |
| 4205 |
SV, |
--- |
4205 |
SV, |
--- |
| 4206 |
LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), |
0 |
4206 |
LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), |
0 |
| 4207 |
AAInfo))) { |
--- |
4207 |
AAInfo))) { |
--- |
| 4208 |
// Do not serialize (non-volatile) loads of constant memory with anything. |
--- |
4208 |
// Do not serialize (non-volatile) loads of constant memory with anything. |
--- |
| 4209 |
Root = DAG.getEntryNode(); |
0 |
4209 |
Root = DAG.getEntryNode(); |
0 |
| 4210 |
ConstantMemory = true; |
0 |
4210 |
ConstantMemory = true; |
0 |
| 4211 |
MMOFlags |= MachineMemOperand::MOInvariant; |
0 |
4211 |
MMOFlags |= MachineMemOperand::MOInvariant; |
0 |
| 4212 |
} else { |
--- |
4212 |
} else { |
--- |
| 4213 |
// Do not serialize non-volatile loads against each other. |
--- |
4213 |
// Do not serialize non-volatile loads against each other. |
--- |
| 4214 |
Root = DAG.getRoot(); |
5 |
4214 |
Root = DAG.getRoot(); |
5 |
| 4215 |
} |
--- |
4215 |
} |
--- |
| 4216 |
|
--- |
4216 |
|
--- |
| 4217 |
SDLoc dl = getCurSDLoc(); |
5 |
4217 |
SDLoc dl = getCurSDLoc(); |
5 |
| 4218 |
|
--- |
4218 |
|
--- |
| 4219 |
if (isVolatile) |
5 |
4219 |
if (isVolatile) |
5 |
| 4220 |
Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG); |
0 |
4220 |
Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG); |
0 |
| 4221 |
|
--- |
4221 |
|
--- |
| 4222 |
// An aggregate load cannot wrap around the address space, so offsets to its |
--- |
4222 |
// An aggregate load cannot wrap around the address space, so offsets to its |
--- |
| 4223 |
// parts don't wrap either. |
--- |
4223 |
// parts don't wrap either. |
--- |
| 4224 |
SDNodeFlags Flags; |
5 |
4224 |
SDNodeFlags Flags; |
5 |
| 4225 |
Flags.setNoUnsignedWrap(true); |
5 |
4225 |
Flags.setNoUnsignedWrap(true); |
5 |
| 4226 |
|
--- |
4226 |
|
--- |
| 4227 |
SmallVector Values(NumValues); |
5 |
4227 |
SmallVector Values(NumValues); |
5 |
| 4228 |
SmallVector Chains(std::min(MaxParallelChains, NumValues)); |
5 |
4228 |
SmallVector Chains(std::min(MaxParallelChains, NumValues)); |
5 |
| 4229 |
EVT PtrVT = Ptr.getValueType(); |
5 |
4229 |
EVT PtrVT = Ptr.getValueType(); |
5 |
| 4230 |
|
--- |
4230 |
|
--- |
| 4231 |
unsigned ChainI = 0; |
5 |
4231 |
unsigned ChainI = 0; |
5 |
| 4232 |
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { |
10 |
4232 |
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { |
10 |
| 4233 |
// Serializing loads here may result in excessive register pressure, and |
--- |
4233 |
// Serializing loads here may result in excessive register pressure, and |
--- |
| 4234 |
// TokenFactor places arbitrary choke points on the scheduler. SD scheduling |
--- |
4234 |
// TokenFactor places arbitrary choke points on the scheduler. SD scheduling |
--- |
| 4235 |
// could recover a bit by hoisting nodes upward in the chain by recognizing |
--- |
4235 |
// could recover a bit by hoisting nodes upward in the chain by recognizing |
--- |
| 4236 |
// they are side-effect free or do not alias. The optimizer should really |
--- |
4236 |
// they are side-effect free or do not alias. The optimizer should really |
--- |
| 4237 |
// avoid this case by converting large object/array copies to llvm.memcpy |
--- |
4237 |
// avoid this case by converting large object/array copies to llvm.memcpy |
--- |
| 4238 |
// (MaxParallelChains should always remain as failsafe). |
--- |
4238 |
// (MaxParallelChains should always remain as failsafe). |
--- |
| 4239 |
if (ChainI == MaxParallelChains) { |
5 |
4239 |
if (ChainI == MaxParallelChains) { |
5 |
| 4240 |
assert(PendingLoads.empty() && "PendingLoads must be serialized first"); |
0 |
4240 |
assert(PendingLoads.empty() && "PendingLoads must be serialized first"); |
0 |
| 4241 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
0 |
4241 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
0 |
| 4242 |
ArrayRef(Chains.data(), ChainI)); |
0 |
4242 |
ArrayRef(Chains.data(), ChainI)); |
0 |
| 4243 |
Root = Chain; |
0 |
4243 |
Root = Chain; |
0 |
| 4244 |
ChainI = 0; |
0 |
4244 |
ChainI = 0; |
0 |
| 4245 |
} |
--- |
4245 |
} |
--- |
| 4246 |
SDValue A = DAG.getNode(ISD::ADD, dl, |
5 |
4246 |
SDValue A = DAG.getNode(ISD::ADD, dl, |
5 |
| 4247 |
PtrVT, Ptr, |
--- |
4247 |
PtrVT, Ptr, |
--- |
| 4248 |
DAG.getConstant(Offsets[i], dl, PtrVT), |
5 |
4248 |
DAG.getConstant(Offsets[i], dl, PtrVT), |
5 |
| 4249 |
Flags); |
--- |
4249 |
Flags); |
--- |
| 4250 |
|
--- |
4250 |
|
--- |
| 4251 |
SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A, |
10 |
4251 |
SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A, |
10 |
| 4252 |
MachinePointerInfo(SV, Offsets[i]), Alignment, |
5 |
4252 |
MachinePointerInfo(SV, Offsets[i]), Alignment, |
5 |
| 4253 |
MMOFlags, AAInfo, Ranges); |
--- |
4253 |
MMOFlags, AAInfo, Ranges); |
--- |
| 4254 |
Chains[ChainI] = L.getValue(1); |
5 |
4254 |
Chains[ChainI] = L.getValue(1); |
5 |
| 4255 |
|
--- |
4255 |
|
--- |
| 4256 |
if (MemVTs[i] != ValueVTs[i]) |
5 |
4256 |
if (MemVTs[i] != ValueVTs[i]) |
5 |
| 4257 |
L = DAG.getPtrExtOrTrunc(L, dl, ValueVTs[i]); |
0 |
4257 |
L = DAG.getPtrExtOrTrunc(L, dl, ValueVTs[i]); |
0 |
| 4258 |
|
--- |
4258 |
|
--- |
| 4259 |
Values[i] = L; |
5 |
4259 |
Values[i] = L; |
5 |
| 4260 |
} |
--- |
4260 |
} |
--- |
| 4261 |
|
--- |
4261 |
|
--- |
| 4262 |
if (!ConstantMemory) { |
5 |
4262 |
if (!ConstantMemory) { |
5 |
| 4263 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
5 |
4263 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
5 |
| 4264 |
ArrayRef(Chains.data(), ChainI)); |
5 |
4264 |
ArrayRef(Chains.data(), ChainI)); |
5 |
| 4265 |
if (isVolatile) |
5 |
4265 |
if (isVolatile) |
5 |
| 4266 |
DAG.setRoot(Chain); |
0 |
4266 |
DAG.setRoot(Chain); |
0 |
| 4267 |
else |
--- |
4267 |
else |
--- |
| 4268 |
PendingLoads.push_back(Chain); |
5 |
4268 |
PendingLoads.push_back(Chain); |
5 |
| 4269 |
} |
--- |
4269 |
} |
--- |
| 4270 |
|
--- |
4270 |
|
--- |
| 4271 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, |
10 |
4271 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, |
10 |
| 4272 |
DAG.getVTList(ValueVTs), Values)); |
5 |
4272 |
DAG.getVTList(ValueVTs), Values)); |
5 |
| 4273 |
} |
5 |
4273 |
} |
5 |
| 4274 |
|
--- |
4274 |
|
--- |
| 4275 |
void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) { |
0 |
4275 |
void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) { |
0 |
| 4276 |
assert(DAG.getTargetLoweringInfo().supportSwiftError() && |
0 |
4276 |
assert(DAG.getTargetLoweringInfo().supportSwiftError() && |
0 |
| 4277 |
"call visitStoreToSwiftError when backend supports swifterror"); |
--- |
4277 |
"call visitStoreToSwiftError when backend supports swifterror"); |
--- |
| 4278 |
|
--- |
4278 |
|
--- |
| 4279 |
SmallVector ValueVTs; |
0 |
4279 |
SmallVector ValueVTs; |
0 |
| 4280 |
SmallVector Offsets; |
0 |
4280 |
SmallVector Offsets; |
0 |
| 4281 |
const Value *SrcV = I.getOperand(0); |
0 |
4281 |
const Value *SrcV = I.getOperand(0); |
0 |
| 4282 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), |
0 |
4282 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), |
0 |
| 4283 |
SrcV->getType(), ValueVTs, &Offsets, 0); |
--- |
4283 |
SrcV->getType(), ValueVTs, &Offsets, 0); |
--- |
| 4284 |
assert(ValueVTs.size() == 1 && Offsets[0] == 0 && |
0 |
4284 |
assert(ValueVTs.size() == 1 && Offsets[0] == 0 && |
0 |
| 4285 |
"expect a single EVT for swifterror"); |
--- |
4285 |
"expect a single EVT for swifterror"); |
--- |
| 4286 |
|
--- |
4286 |
|
--- |
| 4287 |
SDValue Src = getValue(SrcV); |
0 |
4287 |
SDValue Src = getValue(SrcV); |
0 |
| 4288 |
// Create a virtual register, then update the virtual register. |
--- |
4288 |
// Create a virtual register, then update the virtual register. |
--- |
| 4289 |
Register VReg = |
--- |
4289 |
Register VReg = |
--- |
| 4290 |
SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand()); |
0 |
4290 |
SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand()); |
0 |
| 4291 |
// Chain, DL, Reg, N or Chain, DL, Reg, N, Glue |
--- |
4291 |
// Chain, DL, Reg, N or Chain, DL, Reg, N, Glue |
--- |
| 4292 |
// Chain can be getRoot or getControlRoot. |
--- |
4292 |
// Chain can be getRoot or getControlRoot. |
--- |
| 4293 |
SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg, |
0 |
4293 |
SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg, |
0 |
| 4294 |
SDValue(Src.getNode(), Src.getResNo())); |
--- |
4294 |
SDValue(Src.getNode(), Src.getResNo())); |
--- |
| 4295 |
DAG.setRoot(CopyNode); |
0 |
4295 |
DAG.setRoot(CopyNode); |
0 |
| 4296 |
} |
0 |
4296 |
} |
0 |
| 4297 |
|
--- |
4297 |
|
--- |
| 4298 |
void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) { |
0 |
4298 |
void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) { |
0 |
| 4299 |
assert(DAG.getTargetLoweringInfo().supportSwiftError() && |
0 |
4299 |
assert(DAG.getTargetLoweringInfo().supportSwiftError() && |
0 |
| 4300 |
"call visitLoadFromSwiftError when backend supports swifterror"); |
--- |
4300 |
"call visitLoadFromSwiftError when backend supports swifterror"); |
--- |
| 4301 |
|
--- |
4301 |
|
--- |
| 4302 |
assert(!I.isVolatile() && |
0 |
4302 |
assert(!I.isVolatile() && |
0 |
| 4303 |
!I.hasMetadata(LLVMContext::MD_nontemporal) && |
--- |
4303 |
!I.hasMetadata(LLVMContext::MD_nontemporal) && |
--- |
| 4304 |
!I.hasMetadata(LLVMContext::MD_invariant_load) && |
--- |
4304 |
!I.hasMetadata(LLVMContext::MD_invariant_load) && |
--- |
| 4305 |
"Support volatile, non temporal, invariant for load_from_swift_error"); |
--- |
4305 |
"Support volatile, non temporal, invariant for load_from_swift_error"); |
--- |
| 4306 |
|
--- |
4306 |
|
--- |
| 4307 |
const Value *SV = I.getOperand(0); |
0 |
4307 |
const Value *SV = I.getOperand(0); |
0 |
| 4308 |
Type *Ty = I.getType(); |
0 |
4308 |
Type *Ty = I.getType(); |
0 |
| 4309 |
assert( |
0 |
4309 |
assert( |
0 |
| 4310 |
(!AA || |
--- |
4310 |
(!AA || |
--- |
| 4311 |
!AA->pointsToConstantMemory(MemoryLocation( |
--- |
4311 |
!AA->pointsToConstantMemory(MemoryLocation( |
--- |
| 4312 |
SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), |
--- |
4312 |
SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), |
--- |
| 4313 |
I.getAAMetadata()))) && |
--- |
4313 |
I.getAAMetadata()))) && |
--- |
| 4314 |
"load_from_swift_error should not be constant memory"); |
--- |
4314 |
"load_from_swift_error should not be constant memory"); |
--- |
| 4315 |
|
--- |
4315 |
|
--- |
| 4316 |
SmallVector ValueVTs; |
0 |
4316 |
SmallVector ValueVTs; |
0 |
| 4317 |
SmallVector Offsets; |
0 |
4317 |
SmallVector Offsets; |
0 |
| 4318 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty, |
0 |
4318 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty, |
0 |
| 4319 |
ValueVTs, &Offsets, 0); |
--- |
4319 |
ValueVTs, &Offsets, 0); |
--- |
| 4320 |
assert(ValueVTs.size() == 1 && Offsets[0] == 0 && |
0 |
4320 |
assert(ValueVTs.size() == 1 && Offsets[0] == 0 && |
0 |
| 4321 |
"expect a single EVT for swifterror"); |
--- |
4321 |
"expect a single EVT for swifterror"); |
--- |
| 4322 |
|
--- |
4322 |
|
--- |
| 4323 |
// Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT |
--- |
4323 |
// Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT |
--- |
| 4324 |
SDValue L = DAG.getCopyFromReg( |
0 |
4324 |
SDValue L = DAG.getCopyFromReg( |
0 |
| 4325 |
getRoot(), getCurSDLoc(), |
0 |
4325 |
getRoot(), getCurSDLoc(), |
0 |
| 4326 |
SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), ValueVTs[0]); |
0 |
4326 |
SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), ValueVTs[0]); |
0 |
| 4327 |
|
--- |
4327 |
|
--- |
| 4328 |
setValue(&I, L); |
0 |
4328 |
setValue(&I, L); |
0 |
| 4329 |
} |
0 |
4329 |
} |
0 |
| 4330 |
|
--- |
4330 |
|
--- |
| 4331 |
void SelectionDAGBuilder::visitStore(const StoreInst &I) { |
4 |
4331 |
void SelectionDAGBuilder::visitStore(const StoreInst &I) { |
4 |
| 4332 |
if (I.isAtomic()) |
4 |
4332 |
if (I.isAtomic()) |
4 |
| 4333 |
return visitAtomicStore(I); |
0 |
4333 |
return visitAtomicStore(I); |
0 |
| 4334 |
|
--- |
4334 |
|
--- |
| 4335 |
const Value *SrcV = I.getOperand(0); |
4 |
4335 |
const Value *SrcV = I.getOperand(0); |
4 |
| 4336 |
const Value *PtrV = I.getOperand(1); |
4 |
4336 |
const Value *PtrV = I.getOperand(1); |
4 |
| 4337 |
|
--- |
4337 |
|
--- |
| 4338 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
4 |
4338 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
4 |
| 4339 |
if (TLI.supportSwiftError()) { |
4 |
4339 |
if (TLI.supportSwiftError()) { |
4 |
| 4340 |
// Swifterror values can come from either a function parameter with |
--- |
4340 |
// Swifterror values can come from either a function parameter with |
--- |
| 4341 |
// swifterror attribute or an alloca with swifterror attribute. |
--- |
4341 |
// swifterror attribute or an alloca with swifterror attribute. |
--- |
| 4342 |
if (const Argument *Arg = dyn_cast(PtrV)) { |
0 |
4342 |
if (const Argument *Arg = dyn_cast(PtrV)) { |
0 |
| 4343 |
if (Arg->hasSwiftErrorAttr()) |
0 |
4343 |
if (Arg->hasSwiftErrorAttr()) |
0 |
| 4344 |
return visitStoreToSwiftError(I); |
0 |
4344 |
return visitStoreToSwiftError(I); |
0 |
| 4345 |
} |
--- |
4345 |
} |
--- |
| 4346 |
|
--- |
4346 |
|
--- |
| 4347 |
if (const AllocaInst *Alloca = dyn_cast(PtrV)) { |
0 |
4347 |
if (const AllocaInst *Alloca = dyn_cast(PtrV)) { |
0 |
| 4348 |
if (Alloca->isSwiftError()) |
0 |
4348 |
if (Alloca->isSwiftError()) |
0 |
| 4349 |
return visitStoreToSwiftError(I); |
0 |
4349 |
return visitStoreToSwiftError(I); |
0 |
| 4350 |
} |
--- |
4350 |
} |
--- |
| 4351 |
} |
--- |
4351 |
} |
--- |
| 4352 |
|
--- |
4352 |
|
--- |
| 4353 |
SmallVector ValueVTs, MemVTs; |
4 |
4353 |
SmallVector ValueVTs, MemVTs; |
4 |
| 4354 |
SmallVector Offsets; |
4 |
4354 |
SmallVector Offsets; |
4 |
| 4355 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), |
4 |
4355 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), |
4 |
| 4356 |
SrcV->getType(), ValueVTs, &MemVTs, &Offsets, 0); |
--- |
4356 |
SrcV->getType(), ValueVTs, &MemVTs, &Offsets, 0); |
--- |
| 4357 |
unsigned NumValues = ValueVTs.size(); |
4 |
4357 |
unsigned NumValues = ValueVTs.size(); |
4 |
| 4358 |
if (NumValues == 0) |
4 |
4358 |
if (NumValues == 0) |
4 |
| 4359 |
return; |
0 |
4359 |
return; |
0 |
| 4360 |
|
--- |
4360 |
|
--- |
| 4361 |
// Get the lowered operands. Note that we do this after |
--- |
4361 |
// Get the lowered operands. Note that we do this after |
--- |
| 4362 |
// checking if NumResults is zero, because with zero results |
--- |
4362 |
// checking if NumResults is zero, because with zero results |
--- |
| 4363 |
// the operands won't have values in the map. |
--- |
4363 |
// the operands won't have values in the map. |
--- |
| 4364 |
SDValue Src = getValue(SrcV); |
4 |
4364 |
SDValue Src = getValue(SrcV); |
4 |
| 4365 |
SDValue Ptr = getValue(PtrV); |
4 |
4365 |
SDValue Ptr = getValue(PtrV); |
4 |
| 4366 |
|
--- |
4366 |
|
--- |
| 4367 |
SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot(); |
4 |
4367 |
SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot(); |
4 |
| 4368 |
SmallVector Chains(std::min(MaxParallelChains, NumValues)); |
4 |
4368 |
SmallVector Chains(std::min(MaxParallelChains, NumValues)); |
4 |
| 4369 |
SDLoc dl = getCurSDLoc(); |
4 |
4369 |
SDLoc dl = getCurSDLoc(); |
4 |
| 4370 |
Align Alignment = I.getAlign(); |
4 |
4370 |
Align Alignment = I.getAlign(); |
4 |
| 4371 |
AAMDNodes AAInfo = I.getAAMetadata(); |
4 |
4371 |
AAMDNodes AAInfo = I.getAAMetadata(); |
4 |
| 4372 |
|
--- |
4372 |
|
--- |
| 4373 |
auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); |
4 |
4373 |
auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); |
4 |
| 4374 |
|
--- |
4374 |
|
--- |
| 4375 |
// An aggregate load cannot wrap around the address space, so offsets to its |
--- |
4375 |
// An aggregate load cannot wrap around the address space, so offsets to its |
--- |
| 4376 |
// parts don't wrap either. |
--- |
4376 |
// parts don't wrap either. |
--- |
| 4377 |
SDNodeFlags Flags; |
4 |
4377 |
SDNodeFlags Flags; |
4 |
| 4378 |
Flags.setNoUnsignedWrap(true); |
4 |
4378 |
Flags.setNoUnsignedWrap(true); |
4 |
| 4379 |
|
--- |
4379 |
|
--- |
| 4380 |
unsigned ChainI = 0; |
4 |
4380 |
unsigned ChainI = 0; |
4 |
| 4381 |
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { |
8 |
4381 |
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { |
8 |
| 4382 |
// See visitLoad comments. |
--- |
4382 |
// See visitLoad comments. |
--- |
| 4383 |
if (ChainI == MaxParallelChains) { |
4 |
4383 |
if (ChainI == MaxParallelChains) { |
4 |
| 4384 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
0 |
4384 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
0 |
| 4385 |
ArrayRef(Chains.data(), ChainI)); |
0 |
4385 |
ArrayRef(Chains.data(), ChainI)); |
0 |
| 4386 |
Root = Chain; |
0 |
4386 |
Root = Chain; |
0 |
| 4387 |
ChainI = 0; |
0 |
4387 |
ChainI = 0; |
0 |
| 4388 |
} |
--- |
4388 |
} |
--- |
| 4389 |
SDValue Add = |
--- |
4389 |
SDValue Add = |
--- |
| 4390 |
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(Offsets[i]), dl, Flags); |
4 |
4390 |
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(Offsets[i]), dl, Flags); |
4 |
| 4391 |
SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i); |
4 |
4391 |
SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i); |
4 |
| 4392 |
if (MemVTs[i] != ValueVTs[i]) |
4 |
4392 |
if (MemVTs[i] != ValueVTs[i]) |
4 |
| 4393 |
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]); |
0 |
4393 |
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]); |
0 |
| 4394 |
SDValue St = |
--- |
4394 |
SDValue St = |
--- |
| 4395 |
DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]), |
4 |
4395 |
DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]), |
4 |
| 4396 |
Alignment, MMOFlags, AAInfo); |
--- |
4396 |
Alignment, MMOFlags, AAInfo); |
--- |
| 4397 |
Chains[ChainI] = St; |
4 |
4397 |
Chains[ChainI] = St; |
4 |
| 4398 |
} |
--- |
4398 |
} |
--- |
| 4399 |
|
--- |
4399 |
|
--- |
| 4400 |
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
4 |
4400 |
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, |
4 |
| 4401 |
ArrayRef(Chains.data(), ChainI)); |
4 |
4401 |
ArrayRef(Chains.data(), ChainI)); |
4 |
| 4402 |
setValue(&I, StoreNode); |
4 |
4402 |
setValue(&I, StoreNode); |
4 |
| 4403 |
DAG.setRoot(StoreNode); |
4 |
4403 |
DAG.setRoot(StoreNode); |
4 |
| 4404 |
} |
4 |
4404 |
} |
4 |
| 4405 |
|
--- |
4405 |
|
--- |
| 4406 |
void SelectionDAGBuilder::visitMaskedStore(const CallInst &I, |
0 |
4406 |
void SelectionDAGBuilder::visitMaskedStore(const CallInst &I, |
0 |
| 4407 |
bool IsCompressing) { |
--- |
4407 |
bool IsCompressing) { |
--- |
| 4408 |
SDLoc sdl = getCurSDLoc(); |
0 |
4408 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 4409 |
|
--- |
4409 |
|
--- |
| 4410 |
auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
4410 |
auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
| 4411 |
MaybeAlign &Alignment) { |
--- |
4411 |
MaybeAlign &Alignment) { |
--- |
| 4412 |
// llvm.masked.store.*(Src0, Ptr, alignment, Mask) |
--- |
4412 |
// llvm.masked.store.*(Src0, Ptr, alignment, Mask) |
--- |
| 4413 |
Src0 = I.getArgOperand(0); |
0 |
4413 |
Src0 = I.getArgOperand(0); |
0 |
| 4414 |
Ptr = I.getArgOperand(1); |
0 |
4414 |
Ptr = I.getArgOperand(1); |
0 |
| 4415 |
Alignment = cast(I.getArgOperand(2))->getMaybeAlignValue(); |
0 |
4415 |
Alignment = cast(I.getArgOperand(2))->getMaybeAlignValue(); |
0 |
| 4416 |
Mask = I.getArgOperand(3); |
0 |
4416 |
Mask = I.getArgOperand(3); |
0 |
| 4417 |
}; |
0 |
4417 |
}; |
0 |
| 4418 |
auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
4418 |
auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
| 4419 |
MaybeAlign &Alignment) { |
--- |
4419 |
MaybeAlign &Alignment) { |
--- |
| 4420 |
// llvm.masked.compressstore.*(Src0, Ptr, Mask) |
--- |
4420 |
// llvm.masked.compressstore.*(Src0, Ptr, Mask) |
--- |
| 4421 |
Src0 = I.getArgOperand(0); |
0 |
4421 |
Src0 = I.getArgOperand(0); |
0 |
| 4422 |
Ptr = I.getArgOperand(1); |
0 |
4422 |
Ptr = I.getArgOperand(1); |
0 |
| 4423 |
Mask = I.getArgOperand(2); |
0 |
4423 |
Mask = I.getArgOperand(2); |
0 |
| 4424 |
Alignment = std::nullopt; |
0 |
4424 |
Alignment = std::nullopt; |
0 |
| 4425 |
}; |
0 |
4425 |
}; |
0 |
| 4426 |
|
--- |
4426 |
|
--- |
| 4427 |
Value *PtrOperand, *MaskOperand, *Src0Operand; |
--- |
4427 |
Value *PtrOperand, *MaskOperand, *Src0Operand; |
--- |
| 4428 |
MaybeAlign Alignment; |
0 |
4428 |
MaybeAlign Alignment; |
0 |
| 4429 |
if (IsCompressing) |
0 |
4429 |
if (IsCompressing) |
0 |
| 4430 |
getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
4430 |
getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
| 4431 |
else |
--- |
4431 |
else |
--- |
| 4432 |
getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
4432 |
getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
| 4433 |
|
--- |
4433 |
|
--- |
| 4434 |
SDValue Ptr = getValue(PtrOperand); |
0 |
4434 |
SDValue Ptr = getValue(PtrOperand); |
0 |
| 4435 |
SDValue Src0 = getValue(Src0Operand); |
0 |
4435 |
SDValue Src0 = getValue(Src0Operand); |
0 |
| 4436 |
SDValue Mask = getValue(MaskOperand); |
0 |
4436 |
SDValue Mask = getValue(MaskOperand); |
0 |
| 4437 |
SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); |
0 |
4437 |
SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); |
0 |
| 4438 |
|
--- |
4438 |
|
--- |
| 4439 |
EVT VT = Src0.getValueType(); |
0 |
4439 |
EVT VT = Src0.getValueType(); |
0 |
| 4440 |
if (!Alignment) |
0 |
4440 |
if (!Alignment) |
0 |
| 4441 |
Alignment = DAG.getEVTAlign(VT); |
0 |
4441 |
Alignment = DAG.getEVTAlign(VT); |
0 |
| 4442 |
|
--- |
4442 |
|
--- |
| 4443 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
4443 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 4444 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, |
--- |
4444 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, |
--- |
| 4445 |
MemoryLocation::UnknownSize, *Alignment, I.getAAMetadata()); |
0 |
4445 |
MemoryLocation::UnknownSize, *Alignment, I.getAAMetadata()); |
0 |
| 4446 |
SDValue StoreNode = |
--- |
4446 |
SDValue StoreNode = |
--- |
| 4447 |
DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO, |
0 |
4447 |
DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO, |
0 |
| 4448 |
ISD::UNINDEXED, false /* Truncating */, IsCompressing); |
--- |
4448 |
ISD::UNINDEXED, false /* Truncating */, IsCompressing); |
--- |
| 4449 |
DAG.setRoot(StoreNode); |
0 |
4449 |
DAG.setRoot(StoreNode); |
0 |
| 4450 |
setValue(&I, StoreNode); |
0 |
4450 |
setValue(&I, StoreNode); |
0 |
| 4451 |
} |
0 |
4451 |
} |
0 |
| 4452 |
|
--- |
4452 |
|
--- |
| 4453 |
// Get a uniform base for the Gather/Scatter intrinsic. |
--- |
4453 |
// Get a uniform base for the Gather/Scatter intrinsic. |
--- |
| 4454 |
// The first argument of the Gather/Scatter intrinsic is a vector of pointers. |
--- |
4454 |
// The first argument of the Gather/Scatter intrinsic is a vector of pointers. |
--- |
| 4455 |
// We try to represent it as a base pointer + vector of indices. |
--- |
4455 |
// We try to represent it as a base pointer + vector of indices. |
--- |
| 4456 |
// Usually, the vector of pointers comes from a 'getelementptr' instruction. |
--- |
4456 |
// Usually, the vector of pointers comes from a 'getelementptr' instruction. |
--- |
| 4457 |
// The first operand of the GEP may be a single pointer or a vector of pointers |
--- |
4457 |
// The first operand of the GEP may be a single pointer or a vector of pointers |
--- |
| 4458 |
// Example: |
--- |
4458 |
// Example: |
--- |
| 4459 |
// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind |
--- |
4459 |
// %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind |
--- |
| 4460 |
// or |
--- |
4460 |
// or |
--- |
| 4461 |
// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind |
--- |
4461 |
// %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind |
--- |
| 4462 |
// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, .. |
--- |
4462 |
// %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, .. |
--- |
| 4463 |
// |
--- |
4463 |
// |
--- |
| 4464 |
// When the first GEP operand is a single pointer - it is the uniform base we |
--- |
4464 |
// When the first GEP operand is a single pointer - it is the uniform base we |
--- |
| 4465 |
// are looking for. If first operand of the GEP is a splat vector - we |
--- |
4465 |
// are looking for. If first operand of the GEP is a splat vector - we |
--- |
| 4466 |
// extract the splat value and use it as a uniform base. |
--- |
4466 |
// extract the splat value and use it as a uniform base. |
--- |
| 4467 |
// In all other cases the function returns 'false'. |
--- |
4467 |
// In all other cases the function returns 'false'. |
--- |
| 4468 |
static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index, |
0 |
4468 |
static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index, |
0 |
| 4469 |
ISD::MemIndexType &IndexType, SDValue &Scale, |
--- |
4469 |
ISD::MemIndexType &IndexType, SDValue &Scale, |
--- |
| 4470 |
SelectionDAGBuilder *SDB, const BasicBlock *CurBB, |
--- |
4470 |
SelectionDAGBuilder *SDB, const BasicBlock *CurBB, |
--- |
| 4471 |
uint64_t ElemSize) { |
--- |
4471 |
uint64_t ElemSize) { |
--- |
| 4472 |
SelectionDAG& DAG = SDB->DAG; |
0 |
4472 |
SelectionDAG& DAG = SDB->DAG; |
0 |
| 4473 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4473 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4474 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
4474 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
| 4475 |
|
--- |
4475 |
|
--- |
| 4476 |
assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type"); |
0 |
4476 |
assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type"); |
0 |
| 4477 |
|
--- |
4477 |
|
--- |
| 4478 |
// Handle splat constant pointer. |
--- |
4478 |
// Handle splat constant pointer. |
--- |
| 4479 |
if (auto *C = dyn_cast(Ptr)) { |
0 |
4479 |
if (auto *C = dyn_cast(Ptr)) { |
0 |
| 4480 |
C = C->getSplatValue(); |
0 |
4480 |
C = C->getSplatValue(); |
0 |
| 4481 |
if (!C) |
0 |
4481 |
if (!C) |
0 |
| 4482 |
return false; |
0 |
4482 |
return false; |
0 |
| 4483 |
|
--- |
4483 |
|
--- |
| 4484 |
Base = SDB->getValue(C); |
0 |
4484 |
Base = SDB->getValue(C); |
0 |
| 4485 |
|
--- |
4485 |
|
--- |
| 4486 |
ElementCount NumElts = cast(Ptr->getType())->getElementCount(); |
0 |
4486 |
ElementCount NumElts = cast(Ptr->getType())->getElementCount(); |
0 |
| 4487 |
EVT VT = EVT::getVectorVT(*DAG.getContext(), TLI.getPointerTy(DL), NumElts); |
0 |
4487 |
EVT VT = EVT::getVectorVT(*DAG.getContext(), TLI.getPointerTy(DL), NumElts); |
0 |
| 4488 |
Index = DAG.getConstant(0, SDB->getCurSDLoc(), VT); |
0 |
4488 |
Index = DAG.getConstant(0, SDB->getCurSDLoc(), VT); |
0 |
| 4489 |
IndexType = ISD::SIGNED_SCALED; |
0 |
4489 |
IndexType = ISD::SIGNED_SCALED; |
0 |
| 4490 |
Scale = DAG.getTargetConstant(1, SDB->getCurSDLoc(), TLI.getPointerTy(DL)); |
0 |
4490 |
Scale = DAG.getTargetConstant(1, SDB->getCurSDLoc(), TLI.getPointerTy(DL)); |
0 |
| 4491 |
return true; |
0 |
4491 |
return true; |
0 |
| 4492 |
} |
--- |
4492 |
} |
--- |
| 4493 |
|
--- |
4493 |
|
--- |
| 4494 |
const GetElementPtrInst *GEP = dyn_cast(Ptr); |
0 |
4494 |
const GetElementPtrInst *GEP = dyn_cast(Ptr); |
0 |
| 4495 |
if (!GEP || GEP->getParent() != CurBB) |
0 |
4495 |
if (!GEP || GEP->getParent() != CurBB) |
0 |
| 4496 |
return false; |
0 |
4496 |
return false; |
0 |
| 4497 |
|
--- |
4497 |
|
--- |
| 4498 |
if (GEP->getNumOperands() != 2) |
0 |
4498 |
if (GEP->getNumOperands() != 2) |
0 |
| 4499 |
return false; |
0 |
4499 |
return false; |
0 |
| 4500 |
|
--- |
4500 |
|
--- |
| 4501 |
const Value *BasePtr = GEP->getPointerOperand(); |
0 |
4501 |
const Value *BasePtr = GEP->getPointerOperand(); |
0 |
| 4502 |
const Value *IndexVal = GEP->getOperand(GEP->getNumOperands() - 1); |
0 |
4502 |
const Value *IndexVal = GEP->getOperand(GEP->getNumOperands() - 1); |
0 |
| 4503 |
|
--- |
4503 |
|
--- |
| 4504 |
// Make sure the base is scalar and the index is a vector. |
--- |
4504 |
// Make sure the base is scalar and the index is a vector. |
--- |
| 4505 |
if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy()) |
0 |
4505 |
if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy()) |
0 |
| 4506 |
return false; |
0 |
4506 |
return false; |
0 |
| 4507 |
|
--- |
4507 |
|
--- |
| 4508 |
TypeSize ScaleVal = DL.getTypeAllocSize(GEP->getResultElementType()); |
0 |
4508 |
TypeSize ScaleVal = DL.getTypeAllocSize(GEP->getResultElementType()); |
0 |
| 4509 |
if (ScaleVal.isScalable()) |
0 |
4509 |
if (ScaleVal.isScalable()) |
0 |
| 4510 |
return false; |
0 |
4510 |
return false; |
0 |
| 4511 |
|
--- |
4511 |
|
--- |
| 4512 |
// Target may not support the required addressing mode. |
--- |
4512 |
// Target may not support the required addressing mode. |
--- |
| 4513 |
if (ScaleVal != 1 && |
0 |
4513 |
if (ScaleVal != 1 && |
0 |
| 4514 |
!TLI.isLegalScaleForGatherScatter(ScaleVal.getFixedValue(), ElemSize)) |
0 |
4514 |
!TLI.isLegalScaleForGatherScatter(ScaleVal.getFixedValue(), ElemSize)) |
0 |
| 4515 |
return false; |
0 |
4515 |
return false; |
0 |
| 4516 |
|
--- |
4516 |
|
--- |
| 4517 |
Base = SDB->getValue(BasePtr); |
0 |
4517 |
Base = SDB->getValue(BasePtr); |
0 |
| 4518 |
Index = SDB->getValue(IndexVal); |
0 |
4518 |
Index = SDB->getValue(IndexVal); |
0 |
| 4519 |
IndexType = ISD::SIGNED_SCALED; |
0 |
4519 |
IndexType = ISD::SIGNED_SCALED; |
0 |
| 4520 |
|
--- |
4520 |
|
--- |
| 4521 |
Scale = |
0 |
4521 |
Scale = |
0 |
| 4522 |
DAG.getTargetConstant(ScaleVal, SDB->getCurSDLoc(), TLI.getPointerTy(DL)); |
0 |
4522 |
DAG.getTargetConstant(ScaleVal, SDB->getCurSDLoc(), TLI.getPointerTy(DL)); |
0 |
| 4523 |
return true; |
0 |
4523 |
return true; |
0 |
| 4524 |
} |
--- |
4524 |
} |
--- |
| 4525 |
|
--- |
4525 |
|
--- |
| 4526 |
void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) { |
0 |
4526 |
void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) { |
0 |
| 4527 |
SDLoc sdl = getCurSDLoc(); |
0 |
4527 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 4528 |
|
--- |
4528 |
|
--- |
| 4529 |
// llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask) |
--- |
4529 |
// llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask) |
--- |
| 4530 |
const Value *Ptr = I.getArgOperand(1); |
0 |
4530 |
const Value *Ptr = I.getArgOperand(1); |
0 |
| 4531 |
SDValue Src0 = getValue(I.getArgOperand(0)); |
0 |
4531 |
SDValue Src0 = getValue(I.getArgOperand(0)); |
0 |
| 4532 |
SDValue Mask = getValue(I.getArgOperand(3)); |
0 |
4532 |
SDValue Mask = getValue(I.getArgOperand(3)); |
0 |
| 4533 |
EVT VT = Src0.getValueType(); |
0 |
4533 |
EVT VT = Src0.getValueType(); |
0 |
| 4534 |
Align Alignment = cast(I.getArgOperand(2)) |
--- |
4534 |
Align Alignment = cast(I.getArgOperand(2)) |
--- |
| 4535 |
->getMaybeAlignValue() |
0 |
4535 |
->getMaybeAlignValue() |
0 |
| 4536 |
.value_or(DAG.getEVTAlign(VT.getScalarType())); |
0 |
4536 |
.value_or(DAG.getEVTAlign(VT.getScalarType())); |
0 |
| 4537 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4537 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4538 |
|
--- |
4538 |
|
--- |
| 4539 |
SDValue Base; |
0 |
4539 |
SDValue Base; |
0 |
| 4540 |
SDValue Index; |
0 |
4540 |
SDValue Index; |
0 |
| 4541 |
ISD::MemIndexType IndexType; |
--- |
4541 |
ISD::MemIndexType IndexType; |
--- |
| 4542 |
SDValue Scale; |
0 |
4542 |
SDValue Scale; |
0 |
| 4543 |
bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this, |
0 |
4543 |
bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this, |
0 |
| 4544 |
I.getParent(), VT.getScalarStoreSize()); |
--- |
4544 |
I.getParent(), VT.getScalarStoreSize()); |
--- |
| 4545 |
|
--- |
4545 |
|
--- |
| 4546 |
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
4546 |
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
| 4547 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
4547 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 4548 |
MachinePointerInfo(AS), MachineMemOperand::MOStore, |
--- |
4548 |
MachinePointerInfo(AS), MachineMemOperand::MOStore, |
--- |
| 4549 |
// TODO: Make MachineMemOperands aware of scalable |
--- |
4549 |
// TODO: Make MachineMemOperands aware of scalable |
--- |
| 4550 |
// vectors. |
--- |
4550 |
// vectors. |
--- |
| 4551 |
MemoryLocation::UnknownSize, Alignment, I.getAAMetadata()); |
0 |
4551 |
MemoryLocation::UnknownSize, Alignment, I.getAAMetadata()); |
0 |
| 4552 |
if (!UniformBase) { |
0 |
4552 |
if (!UniformBase) { |
0 |
| 4553 |
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
4553 |
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 4554 |
Index = getValue(Ptr); |
0 |
4554 |
Index = getValue(Ptr); |
0 |
| 4555 |
IndexType = ISD::SIGNED_SCALED; |
0 |
4555 |
IndexType = ISD::SIGNED_SCALED; |
0 |
| 4556 |
Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
4556 |
Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 4557 |
} |
--- |
4557 |
} |
--- |
| 4558 |
|
--- |
4558 |
|
--- |
| 4559 |
EVT IdxVT = Index.getValueType(); |
0 |
4559 |
EVT IdxVT = Index.getValueType(); |
0 |
| 4560 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
4560 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
| 4561 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
4561 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
| 4562 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
4562 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
| 4563 |
Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index); |
0 |
4563 |
Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index); |
0 |
| 4564 |
} |
--- |
4564 |
} |
--- |
| 4565 |
|
--- |
4565 |
|
--- |
| 4566 |
SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale }; |
0 |
4566 |
SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale }; |
0 |
| 4567 |
SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl, |
0 |
4567 |
SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl, |
0 |
| 4568 |
Ops, MMO, IndexType, false); |
--- |
4568 |
Ops, MMO, IndexType, false); |
--- |
| 4569 |
DAG.setRoot(Scatter); |
0 |
4569 |
DAG.setRoot(Scatter); |
0 |
| 4570 |
setValue(&I, Scatter); |
0 |
4570 |
setValue(&I, Scatter); |
0 |
| 4571 |
} |
0 |
4571 |
} |
0 |
| 4572 |
|
--- |
4572 |
|
--- |
| 4573 |
void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { |
0 |
4573 |
void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { |
0 |
| 4574 |
SDLoc sdl = getCurSDLoc(); |
0 |
4574 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 4575 |
|
--- |
4575 |
|
--- |
| 4576 |
auto getMaskedLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
4576 |
auto getMaskedLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
| 4577 |
MaybeAlign &Alignment) { |
--- |
4577 |
MaybeAlign &Alignment) { |
--- |
| 4578 |
// @llvm.masked.load.*(Ptr, alignment, Mask, Src0) |
--- |
4578 |
// @llvm.masked.load.*(Ptr, alignment, Mask, Src0) |
--- |
| 4579 |
Ptr = I.getArgOperand(0); |
0 |
4579 |
Ptr = I.getArgOperand(0); |
0 |
| 4580 |
Alignment = cast(I.getArgOperand(1))->getMaybeAlignValue(); |
0 |
4580 |
Alignment = cast(I.getArgOperand(1))->getMaybeAlignValue(); |
0 |
| 4581 |
Mask = I.getArgOperand(2); |
0 |
4581 |
Mask = I.getArgOperand(2); |
0 |
| 4582 |
Src0 = I.getArgOperand(3); |
0 |
4582 |
Src0 = I.getArgOperand(3); |
0 |
| 4583 |
}; |
0 |
4583 |
}; |
0 |
| 4584 |
auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
4584 |
auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, |
0 |
| 4585 |
MaybeAlign &Alignment) { |
--- |
4585 |
MaybeAlign &Alignment) { |
--- |
| 4586 |
// @llvm.masked.expandload.*(Ptr, Mask, Src0) |
--- |
4586 |
// @llvm.masked.expandload.*(Ptr, Mask, Src0) |
--- |
| 4587 |
Ptr = I.getArgOperand(0); |
0 |
4587 |
Ptr = I.getArgOperand(0); |
0 |
| 4588 |
Alignment = std::nullopt; |
0 |
4588 |
Alignment = std::nullopt; |
0 |
| 4589 |
Mask = I.getArgOperand(1); |
0 |
4589 |
Mask = I.getArgOperand(1); |
0 |
| 4590 |
Src0 = I.getArgOperand(2); |
0 |
4590 |
Src0 = I.getArgOperand(2); |
0 |
| 4591 |
}; |
0 |
4591 |
}; |
0 |
| 4592 |
|
--- |
4592 |
|
--- |
| 4593 |
Value *PtrOperand, *MaskOperand, *Src0Operand; |
--- |
4593 |
Value *PtrOperand, *MaskOperand, *Src0Operand; |
--- |
| 4594 |
MaybeAlign Alignment; |
0 |
4594 |
MaybeAlign Alignment; |
0 |
| 4595 |
if (IsExpanding) |
0 |
4595 |
if (IsExpanding) |
0 |
| 4596 |
getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
4596 |
getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
| 4597 |
else |
--- |
4597 |
else |
--- |
| 4598 |
getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
4598 |
getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); |
0 |
| 4599 |
|
--- |
4599 |
|
--- |
| 4600 |
SDValue Ptr = getValue(PtrOperand); |
0 |
4600 |
SDValue Ptr = getValue(PtrOperand); |
0 |
| 4601 |
SDValue Src0 = getValue(Src0Operand); |
0 |
4601 |
SDValue Src0 = getValue(Src0Operand); |
0 |
| 4602 |
SDValue Mask = getValue(MaskOperand); |
0 |
4602 |
SDValue Mask = getValue(MaskOperand); |
0 |
| 4603 |
SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); |
0 |
4603 |
SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); |
0 |
| 4604 |
|
--- |
4604 |
|
--- |
| 4605 |
EVT VT = Src0.getValueType(); |
0 |
4605 |
EVT VT = Src0.getValueType(); |
0 |
| 4606 |
if (!Alignment) |
0 |
4606 |
if (!Alignment) |
0 |
| 4607 |
Alignment = DAG.getEVTAlign(VT); |
0 |
4607 |
Alignment = DAG.getEVTAlign(VT); |
0 |
| 4608 |
|
--- |
4608 |
|
--- |
| 4609 |
AAMDNodes AAInfo = I.getAAMetadata(); |
0 |
4609 |
AAMDNodes AAInfo = I.getAAMetadata(); |
0 |
| 4610 |
const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); |
0 |
4610 |
const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); |
0 |
| 4611 |
|
--- |
4611 |
|
--- |
| 4612 |
// Do not serialize masked loads of constant memory with anything. |
--- |
4612 |
// Do not serialize masked loads of constant memory with anything. |
--- |
| 4613 |
MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); |
0 |
4613 |
MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); |
0 |
| 4614 |
bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); |
0 |
4614 |
bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); |
0 |
| 4615 |
|
--- |
4615 |
|
--- |
| 4616 |
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); |
0 |
4616 |
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); |
0 |
| 4617 |
|
--- |
4617 |
|
--- |
| 4618 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
4618 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 4619 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, |
--- |
4619 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, |
--- |
| 4620 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
4620 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
| 4621 |
|
--- |
4621 |
|
--- |
| 4622 |
SDValue Load = |
--- |
4622 |
SDValue Load = |
--- |
| 4623 |
DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Offset, Mask, Src0, VT, MMO, |
0 |
4623 |
DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Offset, Mask, Src0, VT, MMO, |
0 |
| 4624 |
ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding); |
--- |
4624 |
ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding); |
--- |
| 4625 |
if (AddToChain) |
0 |
4625 |
if (AddToChain) |
0 |
| 4626 |
PendingLoads.push_back(Load.getValue(1)); |
0 |
4626 |
PendingLoads.push_back(Load.getValue(1)); |
0 |
| 4627 |
setValue(&I, Load); |
0 |
4627 |
setValue(&I, Load); |
0 |
| 4628 |
} |
0 |
4628 |
} |
0 |
| 4629 |
|
--- |
4629 |
|
--- |
| 4630 |
void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) { |
0 |
4630 |
void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) { |
0 |
| 4631 |
SDLoc sdl = getCurSDLoc(); |
0 |
4631 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 4632 |
|
--- |
4632 |
|
--- |
| 4633 |
// @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0) |
--- |
4633 |
// @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0) |
--- |
| 4634 |
const Value *Ptr = I.getArgOperand(0); |
0 |
4634 |
const Value *Ptr = I.getArgOperand(0); |
0 |
| 4635 |
SDValue Src0 = getValue(I.getArgOperand(3)); |
0 |
4635 |
SDValue Src0 = getValue(I.getArgOperand(3)); |
0 |
| 4636 |
SDValue Mask = getValue(I.getArgOperand(2)); |
0 |
4636 |
SDValue Mask = getValue(I.getArgOperand(2)); |
0 |
| 4637 |
|
--- |
4637 |
|
--- |
| 4638 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4638 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4639 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
4639 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 4640 |
Align Alignment = cast(I.getArgOperand(1)) |
--- |
4640 |
Align Alignment = cast(I.getArgOperand(1)) |
--- |
| 4641 |
->getMaybeAlignValue() |
0 |
4641 |
->getMaybeAlignValue() |
0 |
| 4642 |
.value_or(DAG.getEVTAlign(VT.getScalarType())); |
0 |
4642 |
.value_or(DAG.getEVTAlign(VT.getScalarType())); |
0 |
| 4643 |
|
--- |
4643 |
|
--- |
| 4644 |
const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); |
0 |
4644 |
const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); |
0 |
| 4645 |
|
--- |
4645 |
|
--- |
| 4646 |
SDValue Root = DAG.getRoot(); |
0 |
4646 |
SDValue Root = DAG.getRoot(); |
0 |
| 4647 |
SDValue Base; |
0 |
4647 |
SDValue Base; |
0 |
| 4648 |
SDValue Index; |
0 |
4648 |
SDValue Index; |
0 |
| 4649 |
ISD::MemIndexType IndexType; |
--- |
4649 |
ISD::MemIndexType IndexType; |
--- |
| 4650 |
SDValue Scale; |
0 |
4650 |
SDValue Scale; |
0 |
| 4651 |
bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this, |
0 |
4651 |
bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this, |
0 |
| 4652 |
I.getParent(), VT.getScalarStoreSize()); |
--- |
4652 |
I.getParent(), VT.getScalarStoreSize()); |
--- |
| 4653 |
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
4653 |
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
| 4654 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
4654 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 4655 |
MachinePointerInfo(AS), MachineMemOperand::MOLoad, |
--- |
4655 |
MachinePointerInfo(AS), MachineMemOperand::MOLoad, |
--- |
| 4656 |
// TODO: Make MachineMemOperands aware of scalable |
--- |
4656 |
// TODO: Make MachineMemOperands aware of scalable |
--- |
| 4657 |
// vectors. |
--- |
4657 |
// vectors. |
--- |
| 4658 |
MemoryLocation::UnknownSize, Alignment, I.getAAMetadata(), Ranges); |
0 |
4658 |
MemoryLocation::UnknownSize, Alignment, I.getAAMetadata(), Ranges); |
0 |
| 4659 |
|
--- |
4659 |
|
--- |
| 4660 |
if (!UniformBase) { |
0 |
4660 |
if (!UniformBase) { |
0 |
| 4661 |
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
4661 |
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 4662 |
Index = getValue(Ptr); |
0 |
4662 |
Index = getValue(Ptr); |
0 |
| 4663 |
IndexType = ISD::SIGNED_SCALED; |
0 |
4663 |
IndexType = ISD::SIGNED_SCALED; |
0 |
| 4664 |
Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
4664 |
Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 4665 |
} |
--- |
4665 |
} |
--- |
| 4666 |
|
--- |
4666 |
|
--- |
| 4667 |
EVT IdxVT = Index.getValueType(); |
0 |
4667 |
EVT IdxVT = Index.getValueType(); |
0 |
| 4668 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
4668 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
| 4669 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
4669 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
| 4670 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
4670 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
| 4671 |
Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index); |
0 |
4671 |
Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index); |
0 |
| 4672 |
} |
--- |
4672 |
} |
--- |
| 4673 |
|
--- |
4673 |
|
--- |
| 4674 |
SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale }; |
0 |
4674 |
SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale }; |
0 |
| 4675 |
SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl, |
0 |
4675 |
SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl, |
0 |
| 4676 |
Ops, MMO, IndexType, ISD::NON_EXTLOAD); |
--- |
4676 |
Ops, MMO, IndexType, ISD::NON_EXTLOAD); |
--- |
| 4677 |
|
--- |
4677 |
|
--- |
| 4678 |
PendingLoads.push_back(Gather.getValue(1)); |
0 |
4678 |
PendingLoads.push_back(Gather.getValue(1)); |
0 |
| 4679 |
setValue(&I, Gather); |
0 |
4679 |
setValue(&I, Gather); |
0 |
| 4680 |
} |
0 |
4680 |
} |
0 |
| 4681 |
|
--- |
4681 |
|
--- |
| 4682 |
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { |
0 |
4682 |
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { |
0 |
| 4683 |
SDLoc dl = getCurSDLoc(); |
0 |
4683 |
SDLoc dl = getCurSDLoc(); |
0 |
| 4684 |
AtomicOrdering SuccessOrdering = I.getSuccessOrdering(); |
0 |
4684 |
AtomicOrdering SuccessOrdering = I.getSuccessOrdering(); |
0 |
| 4685 |
AtomicOrdering FailureOrdering = I.getFailureOrdering(); |
0 |
4685 |
AtomicOrdering FailureOrdering = I.getFailureOrdering(); |
0 |
| 4686 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
4686 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
| 4687 |
|
--- |
4687 |
|
--- |
| 4688 |
SDValue InChain = getRoot(); |
0 |
4688 |
SDValue InChain = getRoot(); |
0 |
| 4689 |
|
--- |
4689 |
|
--- |
| 4690 |
MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); |
0 |
4690 |
MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); |
0 |
| 4691 |
SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other); |
0 |
4691 |
SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other); |
0 |
| 4692 |
|
--- |
4692 |
|
--- |
| 4693 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4693 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4694 |
auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout()); |
0 |
4694 |
auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout()); |
0 |
| 4695 |
|
--- |
4695 |
|
--- |
| 4696 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
4696 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 4697 |
MachineMemOperand *MMO = MF.getMachineMemOperand( |
0 |
4697 |
MachineMemOperand *MMO = MF.getMachineMemOperand( |
0 |
| 4698 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
4698 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
| 4699 |
DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, SuccessOrdering, |
0 |
4699 |
DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, SuccessOrdering, |
0 |
| 4700 |
FailureOrdering); |
--- |
4700 |
FailureOrdering); |
--- |
| 4701 |
|
--- |
4701 |
|
--- |
| 4702 |
SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, |
0 |
4702 |
SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, |
0 |
| 4703 |
dl, MemVT, VTs, InChain, |
--- |
4703 |
dl, MemVT, VTs, InChain, |
--- |
| 4704 |
getValue(I.getPointerOperand()), |
--- |
4704 |
getValue(I.getPointerOperand()), |
--- |
| 4705 |
getValue(I.getCompareOperand()), |
--- |
4705 |
getValue(I.getCompareOperand()), |
--- |
| 4706 |
getValue(I.getNewValOperand()), MMO); |
--- |
4706 |
getValue(I.getNewValOperand()), MMO); |
--- |
| 4707 |
|
--- |
4707 |
|
--- |
| 4708 |
SDValue OutChain = L.getValue(2); |
0 |
4708 |
SDValue OutChain = L.getValue(2); |
0 |
| 4709 |
|
--- |
4709 |
|
--- |
| 4710 |
setValue(&I, L); |
0 |
4710 |
setValue(&I, L); |
0 |
| 4711 |
DAG.setRoot(OutChain); |
0 |
4711 |
DAG.setRoot(OutChain); |
0 |
| 4712 |
} |
0 |
4712 |
} |
0 |
| 4713 |
|
--- |
4713 |
|
--- |
| 4714 |
void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { |
0 |
4714 |
void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { |
0 |
| 4715 |
SDLoc dl = getCurSDLoc(); |
0 |
4715 |
SDLoc dl = getCurSDLoc(); |
0 |
| 4716 |
ISD::NodeType NT; |
--- |
4716 |
ISD::NodeType NT; |
--- |
| 4717 |
switch (I.getOperation()) { |
0 |
4717 |
switch (I.getOperation()) { |
0 |
| 4718 |
default: llvm_unreachable("Unknown atomicrmw operation"); |
0 |
4718 |
default: llvm_unreachable("Unknown atomicrmw operation"); |
0 |
| 4719 |
case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; |
0 |
4719 |
case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; |
0 |
| 4720 |
case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; |
0 |
4720 |
case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; |
0 |
| 4721 |
case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; |
0 |
4721 |
case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; |
0 |
| 4722 |
case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; |
0 |
4722 |
case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; |
0 |
| 4723 |
case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; |
0 |
4723 |
case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; |
0 |
| 4724 |
case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; |
0 |
4724 |
case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; |
0 |
| 4725 |
case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; |
0 |
4725 |
case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; |
0 |
| 4726 |
case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; |
0 |
4726 |
case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; |
0 |
| 4727 |
case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; |
0 |
4727 |
case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; |
0 |
| 4728 |
case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; |
0 |
4728 |
case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; |
0 |
| 4729 |
case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; |
0 |
4729 |
case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; |
0 |
| 4730 |
case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break; |
0 |
4730 |
case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break; |
0 |
| 4731 |
case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break; |
0 |
4731 |
case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break; |
0 |
| 4732 |
case AtomicRMWInst::FMax: NT = ISD::ATOMIC_LOAD_FMAX; break; |
0 |
4732 |
case AtomicRMWInst::FMax: NT = ISD::ATOMIC_LOAD_FMAX; break; |
0 |
| 4733 |
case AtomicRMWInst::FMin: NT = ISD::ATOMIC_LOAD_FMIN; break; |
0 |
4733 |
case AtomicRMWInst::FMin: NT = ISD::ATOMIC_LOAD_FMIN; break; |
0 |
| 4734 |
case AtomicRMWInst::UIncWrap: |
0 |
4734 |
case AtomicRMWInst::UIncWrap: |
0 |
| 4735 |
NT = ISD::ATOMIC_LOAD_UINC_WRAP; |
0 |
4735 |
NT = ISD::ATOMIC_LOAD_UINC_WRAP; |
0 |
| 4736 |
break; |
0 |
4736 |
break; |
0 |
| 4737 |
case AtomicRMWInst::UDecWrap: |
0 |
4737 |
case AtomicRMWInst::UDecWrap: |
0 |
| 4738 |
NT = ISD::ATOMIC_LOAD_UDEC_WRAP; |
0 |
4738 |
NT = ISD::ATOMIC_LOAD_UDEC_WRAP; |
0 |
| 4739 |
break; |
0 |
4739 |
break; |
0 |
| 4740 |
} |
--- |
4740 |
} |
--- |
| 4741 |
AtomicOrdering Ordering = I.getOrdering(); |
0 |
4741 |
AtomicOrdering Ordering = I.getOrdering(); |
0 |
| 4742 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
4742 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
| 4743 |
|
--- |
4743 |
|
--- |
| 4744 |
SDValue InChain = getRoot(); |
0 |
4744 |
SDValue InChain = getRoot(); |
0 |
| 4745 |
|
--- |
4745 |
|
--- |
| 4746 |
auto MemVT = getValue(I.getValOperand()).getSimpleValueType(); |
0 |
4746 |
auto MemVT = getValue(I.getValOperand()).getSimpleValueType(); |
0 |
| 4747 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4747 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4748 |
auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout()); |
0 |
4748 |
auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout()); |
0 |
| 4749 |
|
--- |
4749 |
|
--- |
| 4750 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
4750 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 4751 |
MachineMemOperand *MMO = MF.getMachineMemOperand( |
0 |
4751 |
MachineMemOperand *MMO = MF.getMachineMemOperand( |
0 |
| 4752 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
4752 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
| 4753 |
DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, Ordering); |
0 |
4753 |
DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, Ordering); |
0 |
| 4754 |
|
--- |
4754 |
|
--- |
| 4755 |
SDValue L = |
--- |
4755 |
SDValue L = |
--- |
| 4756 |
DAG.getAtomic(NT, dl, MemVT, InChain, |
0 |
4756 |
DAG.getAtomic(NT, dl, MemVT, InChain, |
0 |
| 4757 |
getValue(I.getPointerOperand()), getValue(I.getValOperand()), |
--- |
4757 |
getValue(I.getPointerOperand()), getValue(I.getValOperand()), |
--- |
| 4758 |
MMO); |
--- |
4758 |
MMO); |
--- |
| 4759 |
|
--- |
4759 |
|
--- |
| 4760 |
SDValue OutChain = L.getValue(1); |
0 |
4760 |
SDValue OutChain = L.getValue(1); |
0 |
| 4761 |
|
--- |
4761 |
|
--- |
| 4762 |
setValue(&I, L); |
0 |
4762 |
setValue(&I, L); |
0 |
| 4763 |
DAG.setRoot(OutChain); |
0 |
4763 |
DAG.setRoot(OutChain); |
0 |
| 4764 |
} |
0 |
4764 |
} |
0 |
| 4765 |
|
--- |
4765 |
|
--- |
| 4766 |
void SelectionDAGBuilder::visitFence(const FenceInst &I) { |
0 |
4766 |
void SelectionDAGBuilder::visitFence(const FenceInst &I) { |
0 |
| 4767 |
SDLoc dl = getCurSDLoc(); |
0 |
4767 |
SDLoc dl = getCurSDLoc(); |
0 |
| 4768 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4768 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4769 |
SDValue Ops[3]; |
0 |
4769 |
SDValue Ops[3]; |
0 |
| 4770 |
Ops[0] = getRoot(); |
0 |
4770 |
Ops[0] = getRoot(); |
0 |
| 4771 |
Ops[1] = DAG.getTargetConstant((unsigned)I.getOrdering(), dl, |
0 |
4771 |
Ops[1] = DAG.getTargetConstant((unsigned)I.getOrdering(), dl, |
0 |
| 4772 |
TLI.getFenceOperandTy(DAG.getDataLayout())); |
0 |
4772 |
TLI.getFenceOperandTy(DAG.getDataLayout())); |
0 |
| 4773 |
Ops[2] = DAG.getTargetConstant(I.getSyncScopeID(), dl, |
0 |
4773 |
Ops[2] = DAG.getTargetConstant(I.getSyncScopeID(), dl, |
0 |
| 4774 |
TLI.getFenceOperandTy(DAG.getDataLayout())); |
0 |
4774 |
TLI.getFenceOperandTy(DAG.getDataLayout())); |
0 |
| 4775 |
SDValue N = DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops); |
0 |
4775 |
SDValue N = DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops); |
0 |
| 4776 |
setValue(&I, N); |
0 |
4776 |
setValue(&I, N); |
0 |
| 4777 |
DAG.setRoot(N); |
0 |
4777 |
DAG.setRoot(N); |
0 |
| 4778 |
} |
0 |
4778 |
} |
0 |
| 4779 |
|
--- |
4779 |
|
--- |
| 4780 |
void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { |
0 |
4780 |
void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { |
0 |
| 4781 |
SDLoc dl = getCurSDLoc(); |
0 |
4781 |
SDLoc dl = getCurSDLoc(); |
0 |
| 4782 |
AtomicOrdering Order = I.getOrdering(); |
0 |
4782 |
AtomicOrdering Order = I.getOrdering(); |
0 |
| 4783 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
4783 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
| 4784 |
|
--- |
4784 |
|
--- |
| 4785 |
SDValue InChain = getRoot(); |
0 |
4785 |
SDValue InChain = getRoot(); |
0 |
| 4786 |
|
--- |
4786 |
|
--- |
| 4787 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4787 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4788 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
4788 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 4789 |
EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType()); |
0 |
4789 |
EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 4790 |
|
--- |
4790 |
|
--- |
| 4791 |
if (!TLI.supportsUnalignedAtomics() && |
0 |
4791 |
if (!TLI.supportsUnalignedAtomics() && |
0 |
| 4792 |
I.getAlign().value() < MemVT.getSizeInBits() / 8) |
0 |
4792 |
I.getAlign().value() < MemVT.getSizeInBits() / 8) |
0 |
| 4793 |
report_fatal_error("Cannot generate unaligned atomic load"); |
0 |
4793 |
report_fatal_error("Cannot generate unaligned atomic load"); |
0 |
| 4794 |
|
--- |
4794 |
|
--- |
| 4795 |
auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo); |
0 |
4795 |
auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo); |
0 |
| 4796 |
|
--- |
4796 |
|
--- |
| 4797 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
4797 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 4798 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
4798 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
| 4799 |
I.getAlign(), AAMDNodes(), nullptr, SSID, Order); |
0 |
4799 |
I.getAlign(), AAMDNodes(), nullptr, SSID, Order); |
0 |
| 4800 |
|
--- |
4800 |
|
--- |
| 4801 |
InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG); |
0 |
4801 |
InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG); |
0 |
| 4802 |
|
--- |
4802 |
|
--- |
| 4803 |
SDValue Ptr = getValue(I.getPointerOperand()); |
0 |
4803 |
SDValue Ptr = getValue(I.getPointerOperand()); |
0 |
| 4804 |
|
--- |
4804 |
|
--- |
| 4805 |
if (TLI.lowerAtomicLoadAsLoadSDNode(I)) { |
0 |
4805 |
if (TLI.lowerAtomicLoadAsLoadSDNode(I)) { |
0 |
| 4806 |
// TODO: Once this is better exercised by tests, it should be merged with |
--- |
4806 |
// TODO: Once this is better exercised by tests, it should be merged with |
--- |
| 4807 |
// the normal path for loads to prevent future divergence. |
--- |
4807 |
// the normal path for loads to prevent future divergence. |
--- |
| 4808 |
SDValue L = DAG.getLoad(MemVT, dl, InChain, Ptr, MMO); |
0 |
4808 |
SDValue L = DAG.getLoad(MemVT, dl, InChain, Ptr, MMO); |
0 |
| 4809 |
if (MemVT != VT) |
0 |
4809 |
if (MemVT != VT) |
0 |
| 4810 |
L = DAG.getPtrExtOrTrunc(L, dl, VT); |
0 |
4810 |
L = DAG.getPtrExtOrTrunc(L, dl, VT); |
0 |
| 4811 |
|
--- |
4811 |
|
--- |
| 4812 |
setValue(&I, L); |
0 |
4812 |
setValue(&I, L); |
0 |
| 4813 |
SDValue OutChain = L.getValue(1); |
0 |
4813 |
SDValue OutChain = L.getValue(1); |
0 |
| 4814 |
if (!I.isUnordered()) |
0 |
4814 |
if (!I.isUnordered()) |
0 |
| 4815 |
DAG.setRoot(OutChain); |
0 |
4815 |
DAG.setRoot(OutChain); |
0 |
| 4816 |
else |
--- |
4816 |
else |
--- |
| 4817 |
PendingLoads.push_back(OutChain); |
0 |
4817 |
PendingLoads.push_back(OutChain); |
0 |
| 4818 |
return; |
0 |
4818 |
return; |
0 |
| 4819 |
} |
--- |
4819 |
} |
--- |
| 4820 |
|
--- |
4820 |
|
--- |
| 4821 |
SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain, |
0 |
4821 |
SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain, |
0 |
| 4822 |
Ptr, MMO); |
--- |
4822 |
Ptr, MMO); |
--- |
| 4823 |
|
--- |
4823 |
|
--- |
| 4824 |
SDValue OutChain = L.getValue(1); |
0 |
4824 |
SDValue OutChain = L.getValue(1); |
0 |
| 4825 |
if (MemVT != VT) |
0 |
4825 |
if (MemVT != VT) |
0 |
| 4826 |
L = DAG.getPtrExtOrTrunc(L, dl, VT); |
0 |
4826 |
L = DAG.getPtrExtOrTrunc(L, dl, VT); |
0 |
| 4827 |
|
--- |
4827 |
|
--- |
| 4828 |
setValue(&I, L); |
0 |
4828 |
setValue(&I, L); |
0 |
| 4829 |
DAG.setRoot(OutChain); |
0 |
4829 |
DAG.setRoot(OutChain); |
0 |
| 4830 |
} |
0 |
4830 |
} |
0 |
| 4831 |
|
--- |
4831 |
|
--- |
| 4832 |
void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { |
0 |
4832 |
void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { |
0 |
| 4833 |
SDLoc dl = getCurSDLoc(); |
0 |
4833 |
SDLoc dl = getCurSDLoc(); |
0 |
| 4834 |
|
--- |
4834 |
|
--- |
| 4835 |
AtomicOrdering Ordering = I.getOrdering(); |
0 |
4835 |
AtomicOrdering Ordering = I.getOrdering(); |
0 |
| 4836 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
4836 |
SyncScope::ID SSID = I.getSyncScopeID(); |
0 |
| 4837 |
|
--- |
4837 |
|
--- |
| 4838 |
SDValue InChain = getRoot(); |
0 |
4838 |
SDValue InChain = getRoot(); |
0 |
| 4839 |
|
--- |
4839 |
|
--- |
| 4840 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4840 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4841 |
EVT MemVT = |
--- |
4841 |
EVT MemVT = |
--- |
| 4842 |
TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType()); |
0 |
4842 |
TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType()); |
0 |
| 4843 |
|
--- |
4843 |
|
--- |
| 4844 |
if (!TLI.supportsUnalignedAtomics() && |
0 |
4844 |
if (!TLI.supportsUnalignedAtomics() && |
0 |
| 4845 |
I.getAlign().value() < MemVT.getSizeInBits() / 8) |
0 |
4845 |
I.getAlign().value() < MemVT.getSizeInBits() / 8) |
0 |
| 4846 |
report_fatal_error("Cannot generate unaligned atomic store"); |
0 |
4846 |
report_fatal_error("Cannot generate unaligned atomic store"); |
0 |
| 4847 |
|
--- |
4847 |
|
--- |
| 4848 |
auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); |
0 |
4848 |
auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); |
0 |
| 4849 |
|
--- |
4849 |
|
--- |
| 4850 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
4850 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 4851 |
MachineMemOperand *MMO = MF.getMachineMemOperand( |
0 |
4851 |
MachineMemOperand *MMO = MF.getMachineMemOperand( |
0 |
| 4852 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
4852 |
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), |
0 |
| 4853 |
I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering); |
0 |
4853 |
I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering); |
0 |
| 4854 |
|
--- |
4854 |
|
--- |
| 4855 |
SDValue Val = getValue(I.getValueOperand()); |
0 |
4855 |
SDValue Val = getValue(I.getValueOperand()); |
0 |
| 4856 |
if (Val.getValueType() != MemVT) |
0 |
4856 |
if (Val.getValueType() != MemVT) |
0 |
| 4857 |
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT); |
0 |
4857 |
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT); |
0 |
| 4858 |
SDValue Ptr = getValue(I.getPointerOperand()); |
0 |
4858 |
SDValue Ptr = getValue(I.getPointerOperand()); |
0 |
| 4859 |
|
--- |
4859 |
|
--- |
| 4860 |
if (TLI.lowerAtomicStoreAsStoreSDNode(I)) { |
0 |
4860 |
if (TLI.lowerAtomicStoreAsStoreSDNode(I)) { |
0 |
| 4861 |
// TODO: Once this is better exercised by tests, it should be merged with |
--- |
4861 |
// TODO: Once this is better exercised by tests, it should be merged with |
--- |
| 4862 |
// the normal path for stores to prevent future divergence. |
--- |
4862 |
// the normal path for stores to prevent future divergence. |
--- |
| 4863 |
SDValue S = DAG.getStore(InChain, dl, Val, Ptr, MMO); |
0 |
4863 |
SDValue S = DAG.getStore(InChain, dl, Val, Ptr, MMO); |
0 |
| 4864 |
setValue(&I, S); |
0 |
4864 |
setValue(&I, S); |
0 |
| 4865 |
DAG.setRoot(S); |
0 |
4865 |
DAG.setRoot(S); |
0 |
| 4866 |
return; |
0 |
4866 |
return; |
0 |
| 4867 |
} |
--- |
4867 |
} |
--- |
| 4868 |
SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain, |
0 |
4868 |
SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain, |
0 |
| 4869 |
Ptr, Val, MMO); |
--- |
4869 |
Ptr, Val, MMO); |
--- |
| 4870 |
|
--- |
4870 |
|
--- |
| 4871 |
setValue(&I, OutChain); |
0 |
4871 |
setValue(&I, OutChain); |
0 |
| 4872 |
DAG.setRoot(OutChain); |
0 |
4872 |
DAG.setRoot(OutChain); |
0 |
| 4873 |
} |
0 |
4873 |
} |
0 |
| 4874 |
|
--- |
4874 |
|
--- |
| 4875 |
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC |
--- |
4875 |
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC |
--- |
| 4876 |
/// node. |
--- |
4876 |
/// node. |
--- |
| 4877 |
void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, |
0 |
4877 |
void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, |
0 |
| 4878 |
unsigned Intrinsic) { |
--- |
4878 |
unsigned Intrinsic) { |
--- |
| 4879 |
// Ignore the callsite's attributes. A specific call site may be marked with |
--- |
4879 |
// Ignore the callsite's attributes. A specific call site may be marked with |
--- |
| 4880 |
// readnone, but the lowering code will expect the chain based on the |
--- |
4880 |
// readnone, but the lowering code will expect the chain based on the |
--- |
| 4881 |
// definition. |
--- |
4881 |
// definition. |
--- |
| 4882 |
const Function *F = I.getCalledFunction(); |
0 |
4882 |
const Function *F = I.getCalledFunction(); |
0 |
| 4883 |
bool HasChain = !F->doesNotAccessMemory(); |
0 |
4883 |
bool HasChain = !F->doesNotAccessMemory(); |
0 |
| 4884 |
bool OnlyLoad = HasChain && F->onlyReadsMemory(); |
0 |
4884 |
bool OnlyLoad = HasChain && F->onlyReadsMemory(); |
0 |
| 4885 |
|
--- |
4885 |
|
--- |
| 4886 |
// Build the operand list. |
--- |
4886 |
// Build the operand list. |
--- |
| 4887 |
SmallVector Ops; |
0 |
4887 |
SmallVector Ops; |
0 |
| 4888 |
if (HasChain) { // If this intrinsic has side-effects, chainify it. |
0 |
4888 |
if (HasChain) { // If this intrinsic has side-effects, chainify it. |
0 |
| 4889 |
if (OnlyLoad) { |
0 |
4889 |
if (OnlyLoad) { |
0 |
| 4890 |
// We don't need to serialize loads against other loads. |
--- |
4890 |
// We don't need to serialize loads against other loads. |
--- |
| 4891 |
Ops.push_back(DAG.getRoot()); |
0 |
4891 |
Ops.push_back(DAG.getRoot()); |
0 |
| 4892 |
} else { |
--- |
4892 |
} else { |
--- |
| 4893 |
Ops.push_back(getRoot()); |
0 |
4893 |
Ops.push_back(getRoot()); |
0 |
| 4894 |
} |
--- |
4894 |
} |
--- |
| 4895 |
} |
--- |
4895 |
} |
--- |
| 4896 |
|
--- |
4896 |
|
--- |
| 4897 |
// Info is set by getTgtMemIntrinsic |
--- |
4897 |
// Info is set by getTgtMemIntrinsic |
--- |
| 4898 |
TargetLowering::IntrinsicInfo Info; |
0 |
4898 |
TargetLowering::IntrinsicInfo Info; |
0 |
| 4899 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
4899 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 4900 |
bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, |
0 |
4900 |
bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, |
0 |
| 4901 |
DAG.getMachineFunction(), |
0 |
4901 |
DAG.getMachineFunction(), |
0 |
| 4902 |
Intrinsic); |
--- |
4902 |
Intrinsic); |
--- |
| 4903 |
|
--- |
4903 |
|
--- |
| 4904 |
// Add the intrinsic ID as an integer operand if it's not a target intrinsic. |
--- |
4904 |
// Add the intrinsic ID as an integer operand if it's not a target intrinsic. |
--- |
| 4905 |
if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || |
0 |
4905 |
if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || |
0 |
| 4906 |
Info.opc == ISD::INTRINSIC_W_CHAIN) |
0 |
4906 |
Info.opc == ISD::INTRINSIC_W_CHAIN) |
0 |
| 4907 |
Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(), |
0 |
4907 |
Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(), |
0 |
| 4908 |
TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
4908 |
TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 4909 |
|
--- |
4909 |
|
--- |
| 4910 |
// Add all operands of the call to the operand list. |
--- |
4910 |
// Add all operands of the call to the operand list. |
--- |
| 4911 |
for (unsigned i = 0, e = I.arg_size(); i != e; ++i) { |
0 |
4911 |
for (unsigned i = 0, e = I.arg_size(); i != e; ++i) { |
0 |
| 4912 |
const Value *Arg = I.getArgOperand(i); |
0 |
4912 |
const Value *Arg = I.getArgOperand(i); |
0 |
| 4913 |
if (!I.paramHasAttr(i, Attribute::ImmArg)) { |
0 |
4913 |
if (!I.paramHasAttr(i, Attribute::ImmArg)) { |
0 |
| 4914 |
Ops.push_back(getValue(Arg)); |
0 |
4914 |
Ops.push_back(getValue(Arg)); |
0 |
| 4915 |
continue; |
0 |
4915 |
continue; |
0 |
| 4916 |
} |
--- |
4916 |
} |
--- |
| 4917 |
|
--- |
4917 |
|
--- |
| 4918 |
// Use TargetConstant instead of a regular constant for immarg. |
--- |
4918 |
// Use TargetConstant instead of a regular constant for immarg. |
--- |
| 4919 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), Arg->getType(), true); |
0 |
4919 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), Arg->getType(), true); |
0 |
| 4920 |
if (const ConstantInt *CI = dyn_cast(Arg)) { |
0 |
4920 |
if (const ConstantInt *CI = dyn_cast(Arg)) { |
0 |
| 4921 |
assert(CI->getBitWidth() <= 64 && |
0 |
4921 |
assert(CI->getBitWidth() <= 64 && |
0 |
| 4922 |
"large intrinsic immediates not handled"); |
--- |
4922 |
"large intrinsic immediates not handled"); |
--- |
| 4923 |
Ops.push_back(DAG.getTargetConstant(*CI, SDLoc(), VT)); |
0 |
4923 |
Ops.push_back(DAG.getTargetConstant(*CI, SDLoc(), VT)); |
0 |
| 4924 |
} else { |
--- |
4924 |
} else { |
--- |
| 4925 |
Ops.push_back( |
0 |
4925 |
Ops.push_back( |
0 |
| 4926 |
DAG.getTargetConstantFP(*cast(Arg), SDLoc(), VT)); |
0 |
4926 |
DAG.getTargetConstantFP(*cast(Arg), SDLoc(), VT)); |
0 |
| 4927 |
} |
--- |
4927 |
} |
--- |
| 4928 |
} |
--- |
4928 |
} |
--- |
| 4929 |
|
--- |
4929 |
|
--- |
| 4930 |
SmallVector ValueVTs; |
0 |
4930 |
SmallVector ValueVTs; |
0 |
| 4931 |
ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs); |
0 |
4931 |
ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs); |
0 |
| 4932 |
|
--- |
4932 |
|
--- |
| 4933 |
if (HasChain) |
0 |
4933 |
if (HasChain) |
0 |
| 4934 |
ValueVTs.push_back(MVT::Other); |
0 |
4934 |
ValueVTs.push_back(MVT::Other); |
0 |
| 4935 |
|
--- |
4935 |
|
--- |
| 4936 |
SDVTList VTs = DAG.getVTList(ValueVTs); |
0 |
4936 |
SDVTList VTs = DAG.getVTList(ValueVTs); |
0 |
| 4937 |
|
--- |
4937 |
|
--- |
| 4938 |
// Propagate fast-math-flags from IR to node(s). |
--- |
4938 |
// Propagate fast-math-flags from IR to node(s). |
--- |
| 4939 |
SDNodeFlags Flags; |
0 |
4939 |
SDNodeFlags Flags; |
0 |
| 4940 |
if (auto *FPMO = dyn_cast(&I)) |
0 |
4940 |
if (auto *FPMO = dyn_cast(&I)) |
0 |
| 4941 |
Flags.copyFMF(*FPMO); |
0 |
4941 |
Flags.copyFMF(*FPMO); |
0 |
| 4942 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
4942 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
| 4943 |
|
--- |
4943 |
|
--- |
| 4944 |
// Create the node. |
--- |
4944 |
// Create the node. |
--- |
| 4945 |
SDValue Result; |
0 |
4945 |
SDValue Result; |
0 |
| 4946 |
// In some cases, custom collection of operands from CallInst I may be needed. |
--- |
4946 |
// In some cases, custom collection of operands from CallInst I may be needed. |
--- |
| 4947 |
TLI.CollectTargetIntrinsicOperands(I, Ops, DAG); |
0 |
4947 |
TLI.CollectTargetIntrinsicOperands(I, Ops, DAG); |
0 |
| 4948 |
if (IsTgtIntrinsic) { |
0 |
4948 |
if (IsTgtIntrinsic) { |
0 |
| 4949 |
// This is target intrinsic that touches memory |
--- |
4949 |
// This is target intrinsic that touches memory |
--- |
| 4950 |
// |
--- |
4950 |
// |
--- |
| 4951 |
// TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic |
--- |
4951 |
// TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic |
--- |
| 4952 |
// didn't yield anything useful. |
--- |
4952 |
// didn't yield anything useful. |
--- |
| 4953 |
MachinePointerInfo MPI; |
0 |
4953 |
MachinePointerInfo MPI; |
0 |
| 4954 |
if (Info.ptrVal) |
0 |
4954 |
if (Info.ptrVal) |
0 |
| 4955 |
MPI = MachinePointerInfo(Info.ptrVal, Info.offset); |
0 |
4955 |
MPI = MachinePointerInfo(Info.ptrVal, Info.offset); |
0 |
| 4956 |
else if (Info.fallbackAddressSpace) |
0 |
4956 |
else if (Info.fallbackAddressSpace) |
0 |
| 4957 |
MPI = MachinePointerInfo(*Info.fallbackAddressSpace); |
0 |
4957 |
MPI = MachinePointerInfo(*Info.fallbackAddressSpace); |
0 |
| 4958 |
Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, |
0 |
4958 |
Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, |
0 |
| 4959 |
Info.memVT, MPI, Info.align, Info.flags, |
0 |
4959 |
Info.memVT, MPI, Info.align, Info.flags, |
0 |
| 4960 |
Info.size, I.getAAMetadata()); |
0 |
4960 |
Info.size, I.getAAMetadata()); |
0 |
| 4961 |
} else if (!HasChain) { |
0 |
4961 |
} else if (!HasChain) { |
0 |
| 4962 |
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops); |
0 |
4962 |
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops); |
0 |
| 4963 |
} else if (!I.getType()->isVoidTy()) { |
0 |
4963 |
} else if (!I.getType()->isVoidTy()) { |
0 |
| 4964 |
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops); |
0 |
4964 |
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops); |
0 |
| 4965 |
} else { |
--- |
4965 |
} else { |
--- |
| 4966 |
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops); |
0 |
4966 |
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops); |
0 |
| 4967 |
} |
--- |
4967 |
} |
--- |
| 4968 |
|
--- |
4968 |
|
--- |
| 4969 |
if (HasChain) { |
0 |
4969 |
if (HasChain) { |
0 |
| 4970 |
SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); |
0 |
4970 |
SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); |
0 |
| 4971 |
if (OnlyLoad) |
0 |
4971 |
if (OnlyLoad) |
0 |
| 4972 |
PendingLoads.push_back(Chain); |
0 |
4972 |
PendingLoads.push_back(Chain); |
0 |
| 4973 |
else |
--- |
4973 |
else |
--- |
| 4974 |
DAG.setRoot(Chain); |
0 |
4974 |
DAG.setRoot(Chain); |
0 |
| 4975 |
} |
--- |
4975 |
} |
--- |
| 4976 |
|
--- |
4976 |
|
--- |
| 4977 |
if (!I.getType()->isVoidTy()) { |
0 |
4977 |
if (!I.getType()->isVoidTy()) { |
0 |
| 4978 |
if (!isa(I.getType())) |
0 |
4978 |
if (!isa(I.getType())) |
0 |
| 4979 |
Result = lowerRangeToAssertZExt(DAG, I, Result); |
0 |
4979 |
Result = lowerRangeToAssertZExt(DAG, I, Result); |
0 |
| 4980 |
|
--- |
4980 |
|
--- |
| 4981 |
MaybeAlign Alignment = I.getRetAlign(); |
0 |
4981 |
MaybeAlign Alignment = I.getRetAlign(); |
0 |
| 4982 |
|
--- |
4982 |
|
--- |
| 4983 |
// Insert `assertalign` node if there's an alignment. |
--- |
4983 |
// Insert `assertalign` node if there's an alignment. |
--- |
| 4984 |
if (InsertAssertAlign && Alignment) { |
0 |
4984 |
if (InsertAssertAlign && Alignment) { |
0 |
| 4985 |
Result = |
0 |
4985 |
Result = |
0 |
| 4986 |
DAG.getAssertAlign(getCurSDLoc(), Result, Alignment.valueOrOne()); |
0 |
4986 |
DAG.getAssertAlign(getCurSDLoc(), Result, Alignment.valueOrOne()); |
0 |
| 4987 |
} |
--- |
4987 |
} |
--- |
| 4988 |
|
--- |
4988 |
|
--- |
| 4989 |
setValue(&I, Result); |
0 |
4989 |
setValue(&I, Result); |
0 |
| 4990 |
} |
--- |
4990 |
} |
--- |
| 4991 |
} |
0 |
4991 |
} |
0 |
| 4992 |
|
--- |
4992 |
|
--- |
| 4993 |
/// GetSignificand - Get the significand and build it into a floating-point |
--- |
4993 |
/// GetSignificand - Get the significand and build it into a floating-point |
--- |
| 4994 |
/// number with exponent of 1: |
--- |
4994 |
/// number with exponent of 1: |
--- |
| 4995 |
/// |
--- |
4995 |
/// |
--- |
| 4996 |
/// Op = (Op & 0x007fffff) | 0x3f800000; |
--- |
4996 |
/// Op = (Op & 0x007fffff) | 0x3f800000; |
--- |
| 4997 |
/// |
--- |
4997 |
/// |
--- |
| 4998 |
/// where Op is the hexadecimal representation of floating point value. |
--- |
4998 |
/// where Op is the hexadecimal representation of floating point value. |
--- |
| 4999 |
static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) { |
0 |
4999 |
static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) { |
0 |
| 5000 |
SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, |
0 |
5000 |
SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, |
0 |
| 5001 |
DAG.getConstant(0x007fffff, dl, MVT::i32)); |
0 |
5001 |
DAG.getConstant(0x007fffff, dl, MVT::i32)); |
0 |
| 5002 |
SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, |
0 |
5002 |
SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, |
0 |
| 5003 |
DAG.getConstant(0x3f800000, dl, MVT::i32)); |
0 |
5003 |
DAG.getConstant(0x3f800000, dl, MVT::i32)); |
0 |
| 5004 |
return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); |
0 |
5004 |
return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); |
0 |
| 5005 |
} |
--- |
5005 |
} |
--- |
| 5006 |
|
--- |
5006 |
|
--- |
| 5007 |
/// GetExponent - Get the exponent: |
--- |
5007 |
/// GetExponent - Get the exponent: |
--- |
| 5008 |
/// |
--- |
5008 |
/// |
--- |
| 5009 |
/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); |
--- |
5009 |
/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); |
--- |
| 5010 |
/// |
--- |
5010 |
/// |
--- |
| 5011 |
/// where Op is the hexadecimal representation of floating point value. |
--- |
5011 |
/// where Op is the hexadecimal representation of floating point value. |
--- |
| 5012 |
static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, |
0 |
5012 |
static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, |
0 |
| 5013 |
const TargetLowering &TLI, const SDLoc &dl) { |
--- |
5013 |
const TargetLowering &TLI, const SDLoc &dl) { |
--- |
| 5014 |
SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, |
0 |
5014 |
SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, |
0 |
| 5015 |
DAG.getConstant(0x7f800000, dl, MVT::i32)); |
0 |
5015 |
DAG.getConstant(0x7f800000, dl, MVT::i32)); |
0 |
| 5016 |
SDValue t1 = DAG.getNode( |
0 |
5016 |
SDValue t1 = DAG.getNode( |
0 |
| 5017 |
ISD::SRL, dl, MVT::i32, t0, |
--- |
5017 |
ISD::SRL, dl, MVT::i32, t0, |
--- |
| 5018 |
DAG.getConstant(23, dl, |
--- |
5018 |
DAG.getConstant(23, dl, |
--- |
| 5019 |
TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout()))); |
0 |
5019 |
TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout()))); |
0 |
| 5020 |
SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, |
0 |
5020 |
SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, |
0 |
| 5021 |
DAG.getConstant(127, dl, MVT::i32)); |
0 |
5021 |
DAG.getConstant(127, dl, MVT::i32)); |
0 |
| 5022 |
return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); |
0 |
5022 |
return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); |
0 |
| 5023 |
} |
--- |
5023 |
} |
--- |
| 5024 |
|
--- |
5024 |
|
--- |
| 5025 |
/// getF32Constant - Get 32-bit floating point constant. |
--- |
5025 |
/// getF32Constant - Get 32-bit floating point constant. |
--- |
| 5026 |
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, |
0 |
5026 |
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, |
0 |
| 5027 |
const SDLoc &dl) { |
--- |
5027 |
const SDLoc &dl) { |
--- |
| 5028 |
return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl, |
0 |
5028 |
return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl, |
0 |
| 5029 |
MVT::f32); |
0 |
5029 |
MVT::f32); |
0 |
| 5030 |
} |
--- |
5030 |
} |
--- |
| 5031 |
|
--- |
5031 |
|
--- |
| 5032 |
static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, |
0 |
5032 |
static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, |
0 |
| 5033 |
SelectionDAG &DAG) { |
--- |
5033 |
SelectionDAG &DAG) { |
--- |
| 5034 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
5034 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
| 5035 |
|
--- |
5035 |
|
--- |
| 5036 |
// IntegerPartOfX = ((int32_t)(t0); |
--- |
5036 |
// IntegerPartOfX = ((int32_t)(t0); |
--- |
| 5037 |
SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); |
0 |
5037 |
SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); |
0 |
| 5038 |
|
--- |
5038 |
|
--- |
| 5039 |
// FractionalPartOfX = t0 - (float)IntegerPartOfX; |
--- |
5039 |
// FractionalPartOfX = t0 - (float)IntegerPartOfX; |
--- |
| 5040 |
SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); |
0 |
5040 |
SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); |
0 |
| 5041 |
SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); |
0 |
5041 |
SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); |
0 |
| 5042 |
|
--- |
5042 |
|
--- |
| 5043 |
// IntegerPartOfX <<= 23; |
--- |
5043 |
// IntegerPartOfX <<= 23; |
--- |
| 5044 |
IntegerPartOfX = |
0 |
5044 |
IntegerPartOfX = |
0 |
| 5045 |
DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, |
0 |
5045 |
DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, |
0 |
| 5046 |
DAG.getConstant(23, dl, |
--- |
5046 |
DAG.getConstant(23, dl, |
--- |
| 5047 |
DAG.getTargetLoweringInfo().getShiftAmountTy( |
0 |
5047 |
DAG.getTargetLoweringInfo().getShiftAmountTy( |
0 |
| 5048 |
MVT::i32, DAG.getDataLayout()))); |
--- |
5048 |
MVT::i32, DAG.getDataLayout()))); |
--- |
| 5049 |
|
--- |
5049 |
|
--- |
| 5050 |
SDValue TwoToFractionalPartOfX; |
0 |
5050 |
SDValue TwoToFractionalPartOfX; |
0 |
| 5051 |
if (LimitFloatPrecision <= 6) { |
0 |
5051 |
if (LimitFloatPrecision <= 6) { |
0 |
| 5052 |
// For floating-point precision of 6: |
--- |
5052 |
// For floating-point precision of 6: |
--- |
| 5053 |
// |
--- |
5053 |
// |
--- |
| 5054 |
// TwoToFractionalPartOfX = |
--- |
5054 |
// TwoToFractionalPartOfX = |
--- |
| 5055 |
// 0.997535578f + |
--- |
5055 |
// 0.997535578f + |
--- |
| 5056 |
// (0.735607626f + 0.252464424f * x) * x; |
--- |
5056 |
// (0.735607626f + 0.252464424f * x) * x; |
--- |
| 5057 |
// |
--- |
5057 |
// |
--- |
| 5058 |
// error 0.0144103317, which is 6 bits |
--- |
5058 |
// error 0.0144103317, which is 6 bits |
--- |
| 5059 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5059 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5060 |
getF32Constant(DAG, 0x3e814304, dl)); |
--- |
5060 |
getF32Constant(DAG, 0x3e814304, dl)); |
--- |
| 5061 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
5061 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
| 5062 |
getF32Constant(DAG, 0x3f3c50c8, dl)); |
--- |
5062 |
getF32Constant(DAG, 0x3f3c50c8, dl)); |
--- |
| 5063 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5063 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5064 |
TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5064 |
TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5065 |
getF32Constant(DAG, 0x3f7f5e7e, dl)); |
--- |
5065 |
getF32Constant(DAG, 0x3f7f5e7e, dl)); |
--- |
| 5066 |
} else if (LimitFloatPrecision <= 12) { |
0 |
5066 |
} else if (LimitFloatPrecision <= 12) { |
0 |
| 5067 |
// For floating-point precision of 12: |
--- |
5067 |
// For floating-point precision of 12: |
--- |
| 5068 |
// |
--- |
5068 |
// |
--- |
| 5069 |
// TwoToFractionalPartOfX = |
--- |
5069 |
// TwoToFractionalPartOfX = |
--- |
| 5070 |
// 0.999892986f + |
--- |
5070 |
// 0.999892986f + |
--- |
| 5071 |
// (0.696457318f + |
--- |
5071 |
// (0.696457318f + |
--- |
| 5072 |
// (0.224338339f + 0.792043434e-1f * x) * x) * x; |
--- |
5072 |
// (0.224338339f + 0.792043434e-1f * x) * x) * x; |
--- |
| 5073 |
// |
--- |
5073 |
// |
--- |
| 5074 |
// error 0.000107046256, which is 13 to 14 bits |
--- |
5074 |
// error 0.000107046256, which is 13 to 14 bits |
--- |
| 5075 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5075 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5076 |
getF32Constant(DAG, 0x3da235e3, dl)); |
--- |
5076 |
getF32Constant(DAG, 0x3da235e3, dl)); |
--- |
| 5077 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
5077 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
| 5078 |
getF32Constant(DAG, 0x3e65b8f3, dl)); |
--- |
5078 |
getF32Constant(DAG, 0x3e65b8f3, dl)); |
--- |
| 5079 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5079 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5080 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5080 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5081 |
getF32Constant(DAG, 0x3f324b07, dl)); |
--- |
5081 |
getF32Constant(DAG, 0x3f324b07, dl)); |
--- |
| 5082 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5082 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5083 |
TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, |
0 |
5083 |
TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, |
0 |
| 5084 |
getF32Constant(DAG, 0x3f7ff8fd, dl)); |
--- |
5084 |
getF32Constant(DAG, 0x3f7ff8fd, dl)); |
--- |
| 5085 |
} else { // LimitFloatPrecision <= 18 |
--- |
5085 |
} else { // LimitFloatPrecision <= 18 |
--- |
| 5086 |
// For floating-point precision of 18: |
--- |
5086 |
// For floating-point precision of 18: |
--- |
| 5087 |
// |
--- |
5087 |
// |
--- |
| 5088 |
// TwoToFractionalPartOfX = |
--- |
5088 |
// TwoToFractionalPartOfX = |
--- |
| 5089 |
// 0.999999982f + |
--- |
5089 |
// 0.999999982f + |
--- |
| 5090 |
// (0.693148872f + |
--- |
5090 |
// (0.693148872f + |
--- |
| 5091 |
// (0.240227044f + |
--- |
5091 |
// (0.240227044f + |
--- |
| 5092 |
// (0.554906021e-1f + |
--- |
5092 |
// (0.554906021e-1f + |
--- |
| 5093 |
// (0.961591928e-2f + |
--- |
5093 |
// (0.961591928e-2f + |
--- |
| 5094 |
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; |
--- |
5094 |
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; |
--- |
| 5095 |
// error 2.47208000*10^(-7), which is better than 18 bits |
--- |
5095 |
// error 2.47208000*10^(-7), which is better than 18 bits |
--- |
| 5096 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5096 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5097 |
getF32Constant(DAG, 0x3924b03e, dl)); |
--- |
5097 |
getF32Constant(DAG, 0x3924b03e, dl)); |
--- |
| 5098 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
5098 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
| 5099 |
getF32Constant(DAG, 0x3ab24b87, dl)); |
--- |
5099 |
getF32Constant(DAG, 0x3ab24b87, dl)); |
--- |
| 5100 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5100 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5101 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5101 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5102 |
getF32Constant(DAG, 0x3c1d8c17, dl)); |
--- |
5102 |
getF32Constant(DAG, 0x3c1d8c17, dl)); |
--- |
| 5103 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5103 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5104 |
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, |
0 |
5104 |
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, |
0 |
| 5105 |
getF32Constant(DAG, 0x3d634a1d, dl)); |
--- |
5105 |
getF32Constant(DAG, 0x3d634a1d, dl)); |
--- |
| 5106 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
5106 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
| 5107 |
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, |
0 |
5107 |
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, |
0 |
| 5108 |
getF32Constant(DAG, 0x3e75fe14, dl)); |
--- |
5108 |
getF32Constant(DAG, 0x3e75fe14, dl)); |
--- |
| 5109 |
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); |
0 |
5109 |
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); |
0 |
| 5110 |
SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, |
0 |
5110 |
SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, |
0 |
| 5111 |
getF32Constant(DAG, 0x3f317234, dl)); |
--- |
5111 |
getF32Constant(DAG, 0x3f317234, dl)); |
--- |
| 5112 |
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); |
0 |
5112 |
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); |
0 |
| 5113 |
TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, |
0 |
5113 |
TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, |
0 |
| 5114 |
getF32Constant(DAG, 0x3f800000, dl)); |
--- |
5114 |
getF32Constant(DAG, 0x3f800000, dl)); |
--- |
| 5115 |
} |
--- |
5115 |
} |
--- |
| 5116 |
|
--- |
5116 |
|
--- |
| 5117 |
// Add the exponent into the result in integer domain. |
--- |
5117 |
// Add the exponent into the result in integer domain. |
--- |
| 5118 |
SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX); |
0 |
5118 |
SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX); |
0 |
| 5119 |
return DAG.getNode(ISD::BITCAST, dl, MVT::f32, |
0 |
5119 |
return DAG.getNode(ISD::BITCAST, dl, MVT::f32, |
0 |
| 5120 |
DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX)); |
0 |
5120 |
DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX)); |
0 |
| 5121 |
} |
--- |
5121 |
} |
--- |
| 5122 |
|
--- |
5122 |
|
--- |
| 5123 |
/// expandExp - Lower an exp intrinsic. Handles the special sequences for |
--- |
5123 |
/// expandExp - Lower an exp intrinsic. Handles the special sequences for |
--- |
| 5124 |
/// limited-precision mode. |
--- |
5124 |
/// limited-precision mode. |
--- |
| 5125 |
static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
5125 |
static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
| 5126 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
5126 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
| 5127 |
if (Op.getValueType() == MVT::f32 && |
0 |
5127 |
if (Op.getValueType() == MVT::f32 && |
0 |
| 5128 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
5128 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
| 5129 |
|
--- |
5129 |
|
--- |
| 5130 |
// Put the exponent in the right bit position for later addition to the |
--- |
5130 |
// Put the exponent in the right bit position for later addition to the |
--- |
| 5131 |
// final result: |
--- |
5131 |
// final result: |
--- |
| 5132 |
// |
--- |
5132 |
// |
--- |
| 5133 |
// t0 = Op * log2(e) |
--- |
5133 |
// t0 = Op * log2(e) |
--- |
| 5134 |
|
--- |
5134 |
|
--- |
| 5135 |
// TODO: What fast-math-flags should be set here? |
--- |
5135 |
// TODO: What fast-math-flags should be set here? |
--- |
| 5136 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, |
0 |
5136 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, |
0 |
| 5137 |
DAG.getConstantFP(numbers::log2ef, dl, MVT::f32)); |
0 |
5137 |
DAG.getConstantFP(numbers::log2ef, dl, MVT::f32)); |
0 |
| 5138 |
return getLimitedPrecisionExp2(t0, dl, DAG); |
0 |
5138 |
return getLimitedPrecisionExp2(t0, dl, DAG); |
0 |
| 5139 |
} |
--- |
5139 |
} |
--- |
| 5140 |
|
--- |
5140 |
|
--- |
| 5141 |
// No special expansion. |
--- |
5141 |
// No special expansion. |
--- |
| 5142 |
return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags); |
0 |
5142 |
return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags); |
0 |
| 5143 |
} |
--- |
5143 |
} |
--- |
| 5144 |
|
--- |
5144 |
|
--- |
| 5145 |
/// expandLog - Lower a log intrinsic. Handles the special sequences for |
--- |
5145 |
/// expandLog - Lower a log intrinsic. Handles the special sequences for |
--- |
| 5146 |
/// limited-precision mode. |
--- |
5146 |
/// limited-precision mode. |
--- |
| 5147 |
static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
5147 |
static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
| 5148 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
5148 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
| 5149 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
5149 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
| 5150 |
|
--- |
5150 |
|
--- |
| 5151 |
if (Op.getValueType() == MVT::f32 && |
0 |
5151 |
if (Op.getValueType() == MVT::f32 && |
0 |
| 5152 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
5152 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
| 5153 |
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); |
0 |
5153 |
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); |
0 |
| 5154 |
|
--- |
5154 |
|
--- |
| 5155 |
// Scale the exponent by log(2). |
--- |
5155 |
// Scale the exponent by log(2). |
--- |
| 5156 |
SDValue Exp = GetExponent(DAG, Op1, TLI, dl); |
0 |
5156 |
SDValue Exp = GetExponent(DAG, Op1, TLI, dl); |
0 |
| 5157 |
SDValue LogOfExponent = |
--- |
5157 |
SDValue LogOfExponent = |
--- |
| 5158 |
DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, |
0 |
5158 |
DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, |
0 |
| 5159 |
DAG.getConstantFP(numbers::ln2f, dl, MVT::f32)); |
0 |
5159 |
DAG.getConstantFP(numbers::ln2f, dl, MVT::f32)); |
0 |
| 5160 |
|
--- |
5160 |
|
--- |
| 5161 |
// Get the significand and build it into a floating-point number with |
--- |
5161 |
// Get the significand and build it into a floating-point number with |
--- |
| 5162 |
// exponent of 1. |
--- |
5162 |
// exponent of 1. |
--- |
| 5163 |
SDValue X = GetSignificand(DAG, Op1, dl); |
0 |
5163 |
SDValue X = GetSignificand(DAG, Op1, dl); |
0 |
| 5164 |
|
--- |
5164 |
|
--- |
| 5165 |
SDValue LogOfMantissa; |
0 |
5165 |
SDValue LogOfMantissa; |
0 |
| 5166 |
if (LimitFloatPrecision <= 6) { |
0 |
5166 |
if (LimitFloatPrecision <= 6) { |
0 |
| 5167 |
// For floating-point precision of 6: |
--- |
5167 |
// For floating-point precision of 6: |
--- |
| 5168 |
// |
--- |
5168 |
// |
--- |
| 5169 |
// LogofMantissa = |
--- |
5169 |
// LogofMantissa = |
--- |
| 5170 |
// -1.1609546f + |
--- |
5170 |
// -1.1609546f + |
--- |
| 5171 |
// (1.4034025f - 0.23903021f * x) * x; |
--- |
5171 |
// (1.4034025f - 0.23903021f * x) * x; |
--- |
| 5172 |
// |
--- |
5172 |
// |
--- |
| 5173 |
// error 0.0034276066, which is better than 8 bits |
--- |
5173 |
// error 0.0034276066, which is better than 8 bits |
--- |
| 5174 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5174 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5175 |
getF32Constant(DAG, 0xbe74c456, dl)); |
--- |
5175 |
getF32Constant(DAG, 0xbe74c456, dl)); |
--- |
| 5176 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5176 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5177 |
getF32Constant(DAG, 0x3fb3a2b1, dl)); |
--- |
5177 |
getF32Constant(DAG, 0x3fb3a2b1, dl)); |
--- |
| 5178 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5178 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5179 |
LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5179 |
LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5180 |
getF32Constant(DAG, 0x3f949a29, dl)); |
--- |
5180 |
getF32Constant(DAG, 0x3f949a29, dl)); |
--- |
| 5181 |
} else if (LimitFloatPrecision <= 12) { |
0 |
5181 |
} else if (LimitFloatPrecision <= 12) { |
0 |
| 5182 |
// For floating-point precision of 12: |
--- |
5182 |
// For floating-point precision of 12: |
--- |
| 5183 |
// |
--- |
5183 |
// |
--- |
| 5184 |
// LogOfMantissa = |
--- |
5184 |
// LogOfMantissa = |
--- |
| 5185 |
// -1.7417939f + |
--- |
5185 |
// -1.7417939f + |
--- |
| 5186 |
// (2.8212026f + |
--- |
5186 |
// (2.8212026f + |
--- |
| 5187 |
// (-1.4699568f + |
--- |
5187 |
// (-1.4699568f + |
--- |
| 5188 |
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; |
--- |
5188 |
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; |
--- |
| 5189 |
// |
--- |
5189 |
// |
--- |
| 5190 |
// error 0.000061011436, which is 14 bits |
--- |
5190 |
// error 0.000061011436, which is 14 bits |
--- |
| 5191 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5191 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5192 |
getF32Constant(DAG, 0xbd67b6d6, dl)); |
--- |
5192 |
getF32Constant(DAG, 0xbd67b6d6, dl)); |
--- |
| 5193 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5193 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5194 |
getF32Constant(DAG, 0x3ee4f4b8, dl)); |
--- |
5194 |
getF32Constant(DAG, 0x3ee4f4b8, dl)); |
--- |
| 5195 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5195 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5196 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5196 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5197 |
getF32Constant(DAG, 0x3fbc278b, dl)); |
--- |
5197 |
getF32Constant(DAG, 0x3fbc278b, dl)); |
--- |
| 5198 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5198 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5199 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5199 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5200 |
getF32Constant(DAG, 0x40348e95, dl)); |
--- |
5200 |
getF32Constant(DAG, 0x40348e95, dl)); |
--- |
| 5201 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5201 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5202 |
LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
5202 |
LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
| 5203 |
getF32Constant(DAG, 0x3fdef31a, dl)); |
--- |
5203 |
getF32Constant(DAG, 0x3fdef31a, dl)); |
--- |
| 5204 |
} else { // LimitFloatPrecision <= 18 |
--- |
5204 |
} else { // LimitFloatPrecision <= 18 |
--- |
| 5205 |
// For floating-point precision of 18: |
--- |
5205 |
// For floating-point precision of 18: |
--- |
| 5206 |
// |
--- |
5206 |
// |
--- |
| 5207 |
// LogOfMantissa = |
--- |
5207 |
// LogOfMantissa = |
--- |
| 5208 |
// -2.1072184f + |
--- |
5208 |
// -2.1072184f + |
--- |
| 5209 |
// (4.2372794f + |
--- |
5209 |
// (4.2372794f + |
--- |
| 5210 |
// (-3.7029485f + |
--- |
5210 |
// (-3.7029485f + |
--- |
| 5211 |
// (2.2781945f + |
--- |
5211 |
// (2.2781945f + |
--- |
| 5212 |
// (-0.87823314f + |
--- |
5212 |
// (-0.87823314f + |
--- |
| 5213 |
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; |
--- |
5213 |
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; |
--- |
| 5214 |
// |
--- |
5214 |
// |
--- |
| 5215 |
// error 0.0000023660568, which is better than 18 bits |
--- |
5215 |
// error 0.0000023660568, which is better than 18 bits |
--- |
| 5216 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5216 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5217 |
getF32Constant(DAG, 0xbc91e5ac, dl)); |
--- |
5217 |
getF32Constant(DAG, 0xbc91e5ac, dl)); |
--- |
| 5218 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5218 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5219 |
getF32Constant(DAG, 0x3e4350aa, dl)); |
--- |
5219 |
getF32Constant(DAG, 0x3e4350aa, dl)); |
--- |
| 5220 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5220 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5221 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5221 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5222 |
getF32Constant(DAG, 0x3f60d3e3, dl)); |
--- |
5222 |
getF32Constant(DAG, 0x3f60d3e3, dl)); |
--- |
| 5223 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5223 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5224 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5224 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5225 |
getF32Constant(DAG, 0x4011cdf0, dl)); |
--- |
5225 |
getF32Constant(DAG, 0x4011cdf0, dl)); |
--- |
| 5226 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5226 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5227 |
SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
5227 |
SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
| 5228 |
getF32Constant(DAG, 0x406cfd1c, dl)); |
--- |
5228 |
getF32Constant(DAG, 0x406cfd1c, dl)); |
--- |
| 5229 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
5229 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
| 5230 |
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, |
0 |
5230 |
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, |
0 |
| 5231 |
getF32Constant(DAG, 0x408797cb, dl)); |
--- |
5231 |
getF32Constant(DAG, 0x408797cb, dl)); |
--- |
| 5232 |
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); |
0 |
5232 |
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); |
0 |
| 5233 |
LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, |
0 |
5233 |
LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, |
0 |
| 5234 |
getF32Constant(DAG, 0x4006dcab, dl)); |
--- |
5234 |
getF32Constant(DAG, 0x4006dcab, dl)); |
--- |
| 5235 |
} |
--- |
5235 |
} |
--- |
| 5236 |
|
--- |
5236 |
|
--- |
| 5237 |
return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); |
0 |
5237 |
return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); |
0 |
| 5238 |
} |
--- |
5238 |
} |
--- |
| 5239 |
|
--- |
5239 |
|
--- |
| 5240 |
// No special expansion. |
--- |
5240 |
// No special expansion. |
--- |
| 5241 |
return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op, Flags); |
0 |
5241 |
return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op, Flags); |
0 |
| 5242 |
} |
--- |
5242 |
} |
--- |
| 5243 |
|
--- |
5243 |
|
--- |
| 5244 |
/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for |
--- |
5244 |
/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for |
--- |
| 5245 |
/// limited-precision mode. |
--- |
5245 |
/// limited-precision mode. |
--- |
| 5246 |
static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
5246 |
static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
| 5247 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
5247 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
| 5248 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
5248 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
| 5249 |
|
--- |
5249 |
|
--- |
| 5250 |
if (Op.getValueType() == MVT::f32 && |
0 |
5250 |
if (Op.getValueType() == MVT::f32 && |
0 |
| 5251 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
5251 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
| 5252 |
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); |
0 |
5252 |
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); |
0 |
| 5253 |
|
--- |
5253 |
|
--- |
| 5254 |
// Get the exponent. |
--- |
5254 |
// Get the exponent. |
--- |
| 5255 |
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); |
0 |
5255 |
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); |
0 |
| 5256 |
|
--- |
5256 |
|
--- |
| 5257 |
// Get the significand and build it into a floating-point number with |
--- |
5257 |
// Get the significand and build it into a floating-point number with |
--- |
| 5258 |
// exponent of 1. |
--- |
5258 |
// exponent of 1. |
--- |
| 5259 |
SDValue X = GetSignificand(DAG, Op1, dl); |
0 |
5259 |
SDValue X = GetSignificand(DAG, Op1, dl); |
0 |
| 5260 |
|
--- |
5260 |
|
--- |
| 5261 |
// Different possible minimax approximations of significand in |
--- |
5261 |
// Different possible minimax approximations of significand in |
--- |
| 5262 |
// floating-point for various degrees of accuracy over [1,2]. |
--- |
5262 |
// floating-point for various degrees of accuracy over [1,2]. |
--- |
| 5263 |
SDValue Log2ofMantissa; |
0 |
5263 |
SDValue Log2ofMantissa; |
0 |
| 5264 |
if (LimitFloatPrecision <= 6) { |
0 |
5264 |
if (LimitFloatPrecision <= 6) { |
0 |
| 5265 |
// For floating-point precision of 6: |
--- |
5265 |
// For floating-point precision of 6: |
--- |
| 5266 |
// |
--- |
5266 |
// |
--- |
| 5267 |
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; |
--- |
5267 |
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; |
--- |
| 5268 |
// |
--- |
5268 |
// |
--- |
| 5269 |
// error 0.0049451742, which is more than 7 bits |
--- |
5269 |
// error 0.0049451742, which is more than 7 bits |
--- |
| 5270 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5270 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5271 |
getF32Constant(DAG, 0xbeb08fe0, dl)); |
--- |
5271 |
getF32Constant(DAG, 0xbeb08fe0, dl)); |
--- |
| 5272 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5272 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5273 |
getF32Constant(DAG, 0x40019463, dl)); |
--- |
5273 |
getF32Constant(DAG, 0x40019463, dl)); |
--- |
| 5274 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5274 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5275 |
Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5275 |
Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5276 |
getF32Constant(DAG, 0x3fd6633d, dl)); |
--- |
5276 |
getF32Constant(DAG, 0x3fd6633d, dl)); |
--- |
| 5277 |
} else if (LimitFloatPrecision <= 12) { |
0 |
5277 |
} else if (LimitFloatPrecision <= 12) { |
0 |
| 5278 |
// For floating-point precision of 12: |
--- |
5278 |
// For floating-point precision of 12: |
--- |
| 5279 |
// |
--- |
5279 |
// |
--- |
| 5280 |
// Log2ofMantissa = |
--- |
5280 |
// Log2ofMantissa = |
--- |
| 5281 |
// -2.51285454f + |
--- |
5281 |
// -2.51285454f + |
--- |
| 5282 |
// (4.07009056f + |
--- |
5282 |
// (4.07009056f + |
--- |
| 5283 |
// (-2.12067489f + |
--- |
5283 |
// (-2.12067489f + |
--- |
| 5284 |
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x; |
--- |
5284 |
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x; |
--- |
| 5285 |
// |
--- |
5285 |
// |
--- |
| 5286 |
// error 0.0000876136000, which is better than 13 bits |
--- |
5286 |
// error 0.0000876136000, which is better than 13 bits |
--- |
| 5287 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5287 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5288 |
getF32Constant(DAG, 0xbda7262e, dl)); |
--- |
5288 |
getF32Constant(DAG, 0xbda7262e, dl)); |
--- |
| 5289 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5289 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5290 |
getF32Constant(DAG, 0x3f25280b, dl)); |
--- |
5290 |
getF32Constant(DAG, 0x3f25280b, dl)); |
--- |
| 5291 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5291 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5292 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5292 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5293 |
getF32Constant(DAG, 0x4007b923, dl)); |
--- |
5293 |
getF32Constant(DAG, 0x4007b923, dl)); |
--- |
| 5294 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5294 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5295 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5295 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5296 |
getF32Constant(DAG, 0x40823e2f, dl)); |
--- |
5296 |
getF32Constant(DAG, 0x40823e2f, dl)); |
--- |
| 5297 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5297 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5298 |
Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
5298 |
Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
| 5299 |
getF32Constant(DAG, 0x4020d29c, dl)); |
--- |
5299 |
getF32Constant(DAG, 0x4020d29c, dl)); |
--- |
| 5300 |
} else { // LimitFloatPrecision <= 18 |
--- |
5300 |
} else { // LimitFloatPrecision <= 18 |
--- |
| 5301 |
// For floating-point precision of 18: |
--- |
5301 |
// For floating-point precision of 18: |
--- |
| 5302 |
// |
--- |
5302 |
// |
--- |
| 5303 |
// Log2ofMantissa = |
--- |
5303 |
// Log2ofMantissa = |
--- |
| 5304 |
// -3.0400495f + |
--- |
5304 |
// -3.0400495f + |
--- |
| 5305 |
// (6.1129976f + |
--- |
5305 |
// (6.1129976f + |
--- |
| 5306 |
// (-5.3420409f + |
--- |
5306 |
// (-5.3420409f + |
--- |
| 5307 |
// (3.2865683f + |
--- |
5307 |
// (3.2865683f + |
--- |
| 5308 |
// (-1.2669343f + |
--- |
5308 |
// (-1.2669343f + |
--- |
| 5309 |
// (0.27515199f - |
--- |
5309 |
// (0.27515199f - |
--- |
| 5310 |
// 0.25691327e-1f * x) * x) * x) * x) * x) * x; |
--- |
5310 |
// 0.25691327e-1f * x) * x) * x) * x) * x) * x; |
--- |
| 5311 |
// |
--- |
5311 |
// |
--- |
| 5312 |
// error 0.0000018516, which is better than 18 bits |
--- |
5312 |
// error 0.0000018516, which is better than 18 bits |
--- |
| 5313 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5313 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5314 |
getF32Constant(DAG, 0xbcd2769e, dl)); |
--- |
5314 |
getF32Constant(DAG, 0xbcd2769e, dl)); |
--- |
| 5315 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5315 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5316 |
getF32Constant(DAG, 0x3e8ce0b9, dl)); |
--- |
5316 |
getF32Constant(DAG, 0x3e8ce0b9, dl)); |
--- |
| 5317 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5317 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5318 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5318 |
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5319 |
getF32Constant(DAG, 0x3fa22ae7, dl)); |
--- |
5319 |
getF32Constant(DAG, 0x3fa22ae7, dl)); |
--- |
| 5320 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5320 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5321 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
5321 |
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, |
0 |
| 5322 |
getF32Constant(DAG, 0x40525723, dl)); |
--- |
5322 |
getF32Constant(DAG, 0x40525723, dl)); |
--- |
| 5323 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5323 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5324 |
SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
5324 |
SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, |
0 |
| 5325 |
getF32Constant(DAG, 0x40aaf200, dl)); |
--- |
5325 |
getF32Constant(DAG, 0x40aaf200, dl)); |
--- |
| 5326 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
5326 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
| 5327 |
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, |
0 |
5327 |
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, |
0 |
| 5328 |
getF32Constant(DAG, 0x40c39dad, dl)); |
--- |
5328 |
getF32Constant(DAG, 0x40c39dad, dl)); |
--- |
| 5329 |
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); |
0 |
5329 |
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); |
0 |
| 5330 |
Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, |
0 |
5330 |
Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, |
0 |
| 5331 |
getF32Constant(DAG, 0x4042902c, dl)); |
--- |
5331 |
getF32Constant(DAG, 0x4042902c, dl)); |
--- |
| 5332 |
} |
--- |
5332 |
} |
--- |
| 5333 |
|
--- |
5333 |
|
--- |
| 5334 |
return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); |
0 |
5334 |
return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); |
0 |
| 5335 |
} |
--- |
5335 |
} |
--- |
| 5336 |
|
--- |
5336 |
|
--- |
| 5337 |
// No special expansion. |
--- |
5337 |
// No special expansion. |
--- |
| 5338 |
return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags); |
0 |
5338 |
return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags); |
0 |
| 5339 |
} |
--- |
5339 |
} |
--- |
| 5340 |
|
--- |
5340 |
|
--- |
| 5341 |
/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for |
--- |
5341 |
/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for |
--- |
| 5342 |
/// limited-precision mode. |
--- |
5342 |
/// limited-precision mode. |
--- |
| 5343 |
static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
5343 |
static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
| 5344 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
5344 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
| 5345 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
5345 |
// TODO: What fast-math-flags should be set on the floating-point nodes? |
--- |
| 5346 |
|
--- |
5346 |
|
--- |
| 5347 |
if (Op.getValueType() == MVT::f32 && |
0 |
5347 |
if (Op.getValueType() == MVT::f32 && |
0 |
| 5348 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
5348 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
| 5349 |
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); |
0 |
5349 |
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); |
0 |
| 5350 |
|
--- |
5350 |
|
--- |
| 5351 |
// Scale the exponent by log10(2) [0.30102999f]. |
--- |
5351 |
// Scale the exponent by log10(2) [0.30102999f]. |
--- |
| 5352 |
SDValue Exp = GetExponent(DAG, Op1, TLI, dl); |
0 |
5352 |
SDValue Exp = GetExponent(DAG, Op1, TLI, dl); |
0 |
| 5353 |
SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, |
0 |
5353 |
SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, |
0 |
| 5354 |
getF32Constant(DAG, 0x3e9a209a, dl)); |
--- |
5354 |
getF32Constant(DAG, 0x3e9a209a, dl)); |
--- |
| 5355 |
|
--- |
5355 |
|
--- |
| 5356 |
// Get the significand and build it into a floating-point number with |
--- |
5356 |
// Get the significand and build it into a floating-point number with |
--- |
| 5357 |
// exponent of 1. |
--- |
5357 |
// exponent of 1. |
--- |
| 5358 |
SDValue X = GetSignificand(DAG, Op1, dl); |
0 |
5358 |
SDValue X = GetSignificand(DAG, Op1, dl); |
0 |
| 5359 |
|
--- |
5359 |
|
--- |
| 5360 |
SDValue Log10ofMantissa; |
0 |
5360 |
SDValue Log10ofMantissa; |
0 |
| 5361 |
if (LimitFloatPrecision <= 6) { |
0 |
5361 |
if (LimitFloatPrecision <= 6) { |
0 |
| 5362 |
// For floating-point precision of 6: |
--- |
5362 |
// For floating-point precision of 6: |
--- |
| 5363 |
// |
--- |
5363 |
// |
--- |
| 5364 |
// Log10ofMantissa = |
--- |
5364 |
// Log10ofMantissa = |
--- |
| 5365 |
// -0.50419619f + |
--- |
5365 |
// -0.50419619f + |
--- |
| 5366 |
// (0.60948995f - 0.10380950f * x) * x; |
--- |
5366 |
// (0.60948995f - 0.10380950f * x) * x; |
--- |
| 5367 |
// |
--- |
5367 |
// |
--- |
| 5368 |
// error 0.0014886165, which is 6 bits |
--- |
5368 |
// error 0.0014886165, which is 6 bits |
--- |
| 5369 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5369 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5370 |
getF32Constant(DAG, 0xbdd49a13, dl)); |
--- |
5370 |
getF32Constant(DAG, 0xbdd49a13, dl)); |
--- |
| 5371 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
5371 |
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, |
0 |
| 5372 |
getF32Constant(DAG, 0x3f1c0789, dl)); |
--- |
5372 |
getF32Constant(DAG, 0x3f1c0789, dl)); |
--- |
| 5373 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5373 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5374 |
Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
5374 |
Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, |
0 |
| 5375 |
getF32Constant(DAG, 0x3f011300, dl)); |
--- |
5375 |
getF32Constant(DAG, 0x3f011300, dl)); |
--- |
| 5376 |
} else if (LimitFloatPrecision <= 12) { |
0 |
5376 |
} else if (LimitFloatPrecision <= 12) { |
0 |
| 5377 |
// For floating-point precision of 12: |
--- |
5377 |
// For floating-point precision of 12: |
--- |
| 5378 |
// |
--- |
5378 |
// |
--- |
| 5379 |
// Log10ofMantissa = |
--- |
5379 |
// Log10ofMantissa = |
--- |
| 5380 |
// -0.64831180f + |
--- |
5380 |
// -0.64831180f + |
--- |
| 5381 |
// (0.91751397f + |
--- |
5381 |
// (0.91751397f + |
--- |
| 5382 |
// (-0.31664806f + 0.47637168e-1f * x) * x) * x; |
--- |
5382 |
// (-0.31664806f + 0.47637168e-1f * x) * x) * x; |
--- |
| 5383 |
// |
--- |
5383 |
// |
--- |
| 5384 |
// error 0.00019228036, which is better than 12 bits |
--- |
5384 |
// error 0.00019228036, which is better than 12 bits |
--- |
| 5385 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5385 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5386 |
getF32Constant(DAG, 0x3d431f31, dl)); |
--- |
5386 |
getF32Constant(DAG, 0x3d431f31, dl)); |
--- |
| 5387 |
SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, |
0 |
5387 |
SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, |
0 |
| 5388 |
getF32Constant(DAG, 0x3ea21fb2, dl)); |
--- |
5388 |
getF32Constant(DAG, 0x3ea21fb2, dl)); |
--- |
| 5389 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5389 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5390 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
5390 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
| 5391 |
getF32Constant(DAG, 0x3f6ae232, dl)); |
--- |
5391 |
getF32Constant(DAG, 0x3f6ae232, dl)); |
--- |
| 5392 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5392 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5393 |
Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, |
0 |
5393 |
Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, |
0 |
| 5394 |
getF32Constant(DAG, 0x3f25f7c3, dl)); |
--- |
5394 |
getF32Constant(DAG, 0x3f25f7c3, dl)); |
--- |
| 5395 |
} else { // LimitFloatPrecision <= 18 |
--- |
5395 |
} else { // LimitFloatPrecision <= 18 |
--- |
| 5396 |
// For floating-point precision of 18: |
--- |
5396 |
// For floating-point precision of 18: |
--- |
| 5397 |
// |
--- |
5397 |
// |
--- |
| 5398 |
// Log10ofMantissa = |
--- |
5398 |
// Log10ofMantissa = |
--- |
| 5399 |
// -0.84299375f + |
--- |
5399 |
// -0.84299375f + |
--- |
| 5400 |
// (1.5327582f + |
--- |
5400 |
// (1.5327582f + |
--- |
| 5401 |
// (-1.0688956f + |
--- |
5401 |
// (-1.0688956f + |
--- |
| 5402 |
// (0.49102474f + |
--- |
5402 |
// (0.49102474f + |
--- |
| 5403 |
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; |
--- |
5403 |
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; |
--- |
| 5404 |
// |
--- |
5404 |
// |
--- |
| 5405 |
// error 0.0000037995730, which is better than 18 bits |
--- |
5405 |
// error 0.0000037995730, which is better than 18 bits |
--- |
| 5406 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
5406 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, |
0 |
| 5407 |
getF32Constant(DAG, 0x3c5d51ce, dl)); |
--- |
5407 |
getF32Constant(DAG, 0x3c5d51ce, dl)); |
--- |
| 5408 |
SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, |
0 |
5408 |
SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, |
0 |
| 5409 |
getF32Constant(DAG, 0x3e00685a, dl)); |
--- |
5409 |
getF32Constant(DAG, 0x3e00685a, dl)); |
--- |
| 5410 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
5410 |
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); |
0 |
| 5411 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
5411 |
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, |
0 |
| 5412 |
getF32Constant(DAG, 0x3efb6798, dl)); |
--- |
5412 |
getF32Constant(DAG, 0x3efb6798, dl)); |
--- |
| 5413 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
5413 |
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); |
0 |
| 5414 |
SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, |
0 |
5414 |
SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, |
0 |
| 5415 |
getF32Constant(DAG, 0x3f88d192, dl)); |
--- |
5415 |
getF32Constant(DAG, 0x3f88d192, dl)); |
--- |
| 5416 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
5416 |
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); |
0 |
| 5417 |
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, |
0 |
5417 |
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, |
0 |
| 5418 |
getF32Constant(DAG, 0x3fc4316c, dl)); |
--- |
5418 |
getF32Constant(DAG, 0x3fc4316c, dl)); |
--- |
| 5419 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
5419 |
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); |
0 |
| 5420 |
Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, |
0 |
5420 |
Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, |
0 |
| 5421 |
getF32Constant(DAG, 0x3f57ce70, dl)); |
--- |
5421 |
getF32Constant(DAG, 0x3f57ce70, dl)); |
--- |
| 5422 |
} |
--- |
5422 |
} |
--- |
| 5423 |
|
--- |
5423 |
|
--- |
| 5424 |
return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); |
0 |
5424 |
return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); |
0 |
| 5425 |
} |
--- |
5425 |
} |
--- |
| 5426 |
|
--- |
5426 |
|
--- |
| 5427 |
// No special expansion. |
--- |
5427 |
// No special expansion. |
--- |
| 5428 |
return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op, Flags); |
0 |
5428 |
return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op, Flags); |
0 |
| 5429 |
} |
--- |
5429 |
} |
--- |
| 5430 |
|
--- |
5430 |
|
--- |
| 5431 |
/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for |
--- |
5431 |
/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for |
--- |
| 5432 |
/// limited-precision mode. |
--- |
5432 |
/// limited-precision mode. |
--- |
| 5433 |
static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
5433 |
static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, |
0 |
| 5434 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
5434 |
const TargetLowering &TLI, SDNodeFlags Flags) { |
--- |
| 5435 |
if (Op.getValueType() == MVT::f32 && |
0 |
5435 |
if (Op.getValueType() == MVT::f32 && |
0 |
| 5436 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) |
0 |
5436 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) |
0 |
| 5437 |
return getLimitedPrecisionExp2(Op, dl, DAG); |
0 |
5437 |
return getLimitedPrecisionExp2(Op, dl, DAG); |
0 |
| 5438 |
|
--- |
5438 |
|
--- |
| 5439 |
// No special expansion. |
--- |
5439 |
// No special expansion. |
--- |
| 5440 |
return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags); |
0 |
5440 |
return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags); |
0 |
| 5441 |
} |
--- |
5441 |
} |
--- |
| 5442 |
|
--- |
5442 |
|
--- |
| 5443 |
/// visitPow - Lower a pow intrinsic. Handles the special sequences for |
--- |
5443 |
/// visitPow - Lower a pow intrinsic. Handles the special sequences for |
--- |
| 5444 |
/// limited-precision mode with x == 10.0f. |
--- |
5444 |
/// limited-precision mode with x == 10.0f. |
--- |
| 5445 |
static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, |
0 |
5445 |
static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, |
0 |
| 5446 |
SelectionDAG &DAG, const TargetLowering &TLI, |
--- |
5446 |
SelectionDAG &DAG, const TargetLowering &TLI, |
--- |
| 5447 |
SDNodeFlags Flags) { |
--- |
5447 |
SDNodeFlags Flags) { |
--- |
| 5448 |
bool IsExp10 = false; |
0 |
5448 |
bool IsExp10 = false; |
0 |
| 5449 |
if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 && |
0 |
5449 |
if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 && |
0 |
| 5450 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
5450 |
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { |
0 |
| 5451 |
if (ConstantFPSDNode *LHSC = dyn_cast(LHS)) { |
0 |
5451 |
if (ConstantFPSDNode *LHSC = dyn_cast(LHS)) { |
0 |
| 5452 |
APFloat Ten(10.0f); |
0 |
5452 |
APFloat Ten(10.0f); |
0 |
| 5453 |
IsExp10 = LHSC->isExactlyValue(Ten); |
0 |
5453 |
IsExp10 = LHSC->isExactlyValue(Ten); |
0 |
| 5454 |
} |
0 |
5454 |
} |
0 |
| 5455 |
} |
--- |
5455 |
} |
--- |
| 5456 |
|
--- |
5456 |
|
--- |
| 5457 |
// TODO: What fast-math-flags should be set on the FMUL node? |
--- |
5457 |
// TODO: What fast-math-flags should be set on the FMUL node? |
--- |
| 5458 |
if (IsExp10) { |
0 |
5458 |
if (IsExp10) { |
0 |
| 5459 |
// Put the exponent in the right bit position for later addition to the |
--- |
5459 |
// Put the exponent in the right bit position for later addition to the |
--- |
| 5460 |
// final result: |
--- |
5460 |
// final result: |
--- |
| 5461 |
// |
--- |
5461 |
// |
--- |
| 5462 |
// #define LOG2OF10 3.3219281f |
--- |
5462 |
// #define LOG2OF10 3.3219281f |
--- |
| 5463 |
// t0 = Op * LOG2OF10; |
--- |
5463 |
// t0 = Op * LOG2OF10; |
--- |
| 5464 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, |
0 |
5464 |
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, |
0 |
| 5465 |
getF32Constant(DAG, 0x40549a78, dl)); |
--- |
5465 |
getF32Constant(DAG, 0x40549a78, dl)); |
--- |
| 5466 |
return getLimitedPrecisionExp2(t0, dl, DAG); |
0 |
5466 |
return getLimitedPrecisionExp2(t0, dl, DAG); |
0 |
| 5467 |
} |
--- |
5467 |
} |
--- |
| 5468 |
|
--- |
5468 |
|
--- |
| 5469 |
// No special expansion. |
--- |
5469 |
// No special expansion. |
--- |
| 5470 |
return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS, Flags); |
0 |
5470 |
return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS, Flags); |
0 |
| 5471 |
} |
--- |
5471 |
} |
--- |
| 5472 |
|
--- |
5472 |
|
--- |
| 5473 |
/// ExpandPowI - Expand a llvm.powi intrinsic. |
--- |
5473 |
/// ExpandPowI - Expand a llvm.powi intrinsic. |
--- |
| 5474 |
static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, |
0 |
5474 |
static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, |
0 |
| 5475 |
SelectionDAG &DAG) { |
--- |
5475 |
SelectionDAG &DAG) { |
--- |
| 5476 |
// If RHS is a constant, we can expand this out to a multiplication tree if |
--- |
5476 |
// If RHS is a constant, we can expand this out to a multiplication tree if |
--- |
| 5477 |
// it's beneficial on the target, otherwise we end up lowering to a call to |
--- |
5477 |
// it's beneficial on the target, otherwise we end up lowering to a call to |
--- |
| 5478 |
// __powidf2 (for example). |
--- |
5478 |
// __powidf2 (for example). |
--- |
| 5479 |
if (ConstantSDNode *RHSC = dyn_cast(RHS)) { |
0 |
5479 |
if (ConstantSDNode *RHSC = dyn_cast(RHS)) { |
0 |
| 5480 |
unsigned Val = RHSC->getSExtValue(); |
0 |
5480 |
unsigned Val = RHSC->getSExtValue(); |
0 |
| 5481 |
|
--- |
5481 |
|
--- |
| 5482 |
// powi(x, 0) -> 1.0 |
--- |
5482 |
// powi(x, 0) -> 1.0 |
--- |
| 5483 |
if (Val == 0) |
0 |
5483 |
if (Val == 0) |
0 |
| 5484 |
return DAG.getConstantFP(1.0, DL, LHS.getValueType()); |
0 |
5484 |
return DAG.getConstantFP(1.0, DL, LHS.getValueType()); |
0 |
| 5485 |
|
--- |
5485 |
|
--- |
| 5486 |
if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI( |
0 |
5486 |
if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI( |
0 |
| 5487 |
Val, DAG.shouldOptForSize())) { |
0 |
5487 |
Val, DAG.shouldOptForSize())) { |
0 |
| 5488 |
// Get the exponent as a positive value. |
--- |
5488 |
// Get the exponent as a positive value. |
--- |
| 5489 |
if ((int)Val < 0) |
0 |
5489 |
if ((int)Val < 0) |
0 |
| 5490 |
Val = -Val; |
0 |
5490 |
Val = -Val; |
0 |
| 5491 |
// We use the simple binary decomposition method to generate the multiply |
--- |
5491 |
// We use the simple binary decomposition method to generate the multiply |
--- |
| 5492 |
// sequence. There are more optimal ways to do this (for example, |
--- |
5492 |
// sequence. There are more optimal ways to do this (for example, |
--- |
| 5493 |
// powi(x,15) generates one more multiply than it should), but this has |
--- |
5493 |
// powi(x,15) generates one more multiply than it should), but this has |
--- |
| 5494 |
// the benefit of being both really simple and much better than a libcall. |
--- |
5494 |
// the benefit of being both really simple and much better than a libcall. |
--- |
| 5495 |
SDValue Res; // Logically starts equal to 1.0 |
0 |
5495 |
SDValue Res; // Logically starts equal to 1.0 |
0 |
| 5496 |
SDValue CurSquare = LHS; |
0 |
5496 |
SDValue CurSquare = LHS; |
0 |
| 5497 |
// TODO: Intrinsics should have fast-math-flags that propagate to these |
--- |
5497 |
// TODO: Intrinsics should have fast-math-flags that propagate to these |
--- |
| 5498 |
// nodes. |
--- |
5498 |
// nodes. |
--- |
| 5499 |
while (Val) { |
0 |
5499 |
while (Val) { |
0 |
| 5500 |
if (Val & 1) { |
0 |
5500 |
if (Val & 1) { |
0 |
| 5501 |
if (Res.getNode()) |
0 |
5501 |
if (Res.getNode()) |
0 |
| 5502 |
Res = |
0 |
5502 |
Res = |
0 |
| 5503 |
DAG.getNode(ISD::FMUL, DL, Res.getValueType(), Res, CurSquare); |
0 |
5503 |
DAG.getNode(ISD::FMUL, DL, Res.getValueType(), Res, CurSquare); |
0 |
| 5504 |
else |
--- |
5504 |
else |
--- |
| 5505 |
Res = CurSquare; // 1.0*CurSquare. |
0 |
5505 |
Res = CurSquare; // 1.0*CurSquare. |
0 |
| 5506 |
} |
--- |
5506 |
} |
--- |
| 5507 |
|
--- |
5507 |
|
--- |
| 5508 |
CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), |
0 |
5508 |
CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), |
0 |
| 5509 |
CurSquare, CurSquare); |
--- |
5509 |
CurSquare, CurSquare); |
--- |
| 5510 |
Val >>= 1; |
0 |
5510 |
Val >>= 1; |
0 |
| 5511 |
} |
--- |
5511 |
} |
--- |
| 5512 |
|
--- |
5512 |
|
--- |
| 5513 |
// If the original was negative, invert the result, producing 1/(x*x*x). |
--- |
5513 |
// If the original was negative, invert the result, producing 1/(x*x*x). |
--- |
| 5514 |
if (RHSC->getSExtValue() < 0) |
0 |
5514 |
if (RHSC->getSExtValue() < 0) |
0 |
| 5515 |
Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), |
0 |
5515 |
Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), |
0 |
| 5516 |
DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res); |
--- |
5516 |
DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res); |
--- |
| 5517 |
return Res; |
0 |
5517 |
return Res; |
0 |
| 5518 |
} |
--- |
5518 |
} |
--- |
| 5519 |
} |
--- |
5519 |
} |
--- |
| 5520 |
|
--- |
5520 |
|
--- |
| 5521 |
// Otherwise, expand to a libcall. |
--- |
5521 |
// Otherwise, expand to a libcall. |
--- |
| 5522 |
return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); |
0 |
5522 |
return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); |
0 |
| 5523 |
} |
--- |
5523 |
} |
--- |
| 5524 |
|
--- |
5524 |
|
--- |
| 5525 |
static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, |
0 |
5525 |
static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, |
0 |
| 5526 |
SDValue LHS, SDValue RHS, SDValue Scale, |
--- |
5526 |
SDValue LHS, SDValue RHS, SDValue Scale, |
--- |
| 5527 |
SelectionDAG &DAG, const TargetLowering &TLI) { |
--- |
5527 |
SelectionDAG &DAG, const TargetLowering &TLI) { |
--- |
| 5528 |
EVT VT = LHS.getValueType(); |
0 |
5528 |
EVT VT = LHS.getValueType(); |
0 |
| 5529 |
bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT; |
0 |
5529 |
bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT; |
0 |
| 5530 |
bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT; |
0 |
5530 |
bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT; |
0 |
| 5531 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
5531 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
| 5532 |
|
--- |
5532 |
|
--- |
| 5533 |
// If the type is legal but the operation isn't, this node might survive all |
--- |
5533 |
// If the type is legal but the operation isn't, this node might survive all |
--- |
| 5534 |
// the way to operation legalization. If we end up there and we do not have |
--- |
5534 |
// the way to operation legalization. If we end up there and we do not have |
--- |
| 5535 |
// the ability to widen the type (if VT*2 is not legal), we cannot expand the |
--- |
5535 |
// the ability to widen the type (if VT*2 is not legal), we cannot expand the |
--- |
| 5536 |
// node. |
--- |
5536 |
// node. |
--- |
| 5537 |
|
--- |
5537 |
|
--- |
| 5538 |
// Coax the legalizer into expanding the node during type legalization instead |
--- |
5538 |
// Coax the legalizer into expanding the node during type legalization instead |
--- |
| 5539 |
// by bumping the size by one bit. This will force it to Promote, enabling the |
--- |
5539 |
// by bumping the size by one bit. This will force it to Promote, enabling the |
--- |
| 5540 |
// early expansion and avoiding the need to expand later. |
--- |
5540 |
// early expansion and avoiding the need to expand later. |
--- |
| 5541 |
|
--- |
5541 |
|
--- |
| 5542 |
// We don't have to do this if Scale is 0; that can always be expanded, unless |
--- |
5542 |
// We don't have to do this if Scale is 0; that can always be expanded, unless |
--- |
| 5543 |
// it's a saturating signed operation. Those can experience true integer |
--- |
5543 |
// it's a saturating signed operation. Those can experience true integer |
--- |
| 5544 |
// division overflow, a case which we must avoid. |
--- |
5544 |
// division overflow, a case which we must avoid. |
--- |
| 5545 |
|
--- |
5545 |
|
--- |
| 5546 |
// FIXME: We wouldn't have to do this (or any of the early |
--- |
5546 |
// FIXME: We wouldn't have to do this (or any of the early |
--- |
| 5547 |
// expansion/promotion) if it was possible to expand a libcall of an |
--- |
5547 |
// expansion/promotion) if it was possible to expand a libcall of an |
--- |
| 5548 |
// illegal type during operation legalization. But it's not, so things |
--- |
5548 |
// illegal type during operation legalization. But it's not, so things |
--- |
| 5549 |
// get a bit hacky. |
--- |
5549 |
// get a bit hacky. |
--- |
| 5550 |
unsigned ScaleInt = cast(Scale)->getZExtValue(); |
0 |
5550 |
unsigned ScaleInt = cast(Scale)->getZExtValue(); |
0 |
| 5551 |
if ((ScaleInt > 0 || (Saturating && Signed)) && |
0 |
5551 |
if ((ScaleInt > 0 || (Saturating && Signed)) && |
0 |
| 5552 |
(TLI.isTypeLegal(VT) || |
0 |
5552 |
(TLI.isTypeLegal(VT) || |
0 |
| 5553 |
(VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) { |
0 |
5553 |
(VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) { |
0 |
| 5554 |
TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction( |
0 |
5554 |
TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction( |
0 |
| 5555 |
Opcode, VT, ScaleInt); |
--- |
5555 |
Opcode, VT, ScaleInt); |
--- |
| 5556 |
if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) { |
0 |
5556 |
if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) { |
0 |
| 5557 |
EVT PromVT; |
0 |
5557 |
EVT PromVT; |
0 |
| 5558 |
if (VT.isScalarInteger()) |
0 |
5558 |
if (VT.isScalarInteger()) |
0 |
| 5559 |
PromVT = EVT::getIntegerVT(Ctx, VT.getSizeInBits() + 1); |
0 |
5559 |
PromVT = EVT::getIntegerVT(Ctx, VT.getSizeInBits() + 1); |
0 |
| 5560 |
else if (VT.isVector()) { |
0 |
5560 |
else if (VT.isVector()) { |
0 |
| 5561 |
PromVT = VT.getVectorElementType(); |
0 |
5561 |
PromVT = VT.getVectorElementType(); |
0 |
| 5562 |
PromVT = EVT::getIntegerVT(Ctx, PromVT.getSizeInBits() + 1); |
0 |
5562 |
PromVT = EVT::getIntegerVT(Ctx, PromVT.getSizeInBits() + 1); |
0 |
| 5563 |
PromVT = EVT::getVectorVT(Ctx, PromVT, VT.getVectorElementCount()); |
0 |
5563 |
PromVT = EVT::getVectorVT(Ctx, PromVT, VT.getVectorElementCount()); |
0 |
| 5564 |
} else |
--- |
5564 |
} else |
--- |
| 5565 |
llvm_unreachable("Wrong VT for DIVFIX?"); |
0 |
5565 |
llvm_unreachable("Wrong VT for DIVFIX?"); |
0 |
| 5566 |
LHS = DAG.getExtOrTrunc(Signed, LHS, DL, PromVT); |
0 |
5566 |
LHS = DAG.getExtOrTrunc(Signed, LHS, DL, PromVT); |
0 |
| 5567 |
RHS = DAG.getExtOrTrunc(Signed, RHS, DL, PromVT); |
0 |
5567 |
RHS = DAG.getExtOrTrunc(Signed, RHS, DL, PromVT); |
0 |
| 5568 |
EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); |
0 |
5568 |
EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); |
0 |
| 5569 |
// For saturating operations, we need to shift up the LHS to get the |
--- |
5569 |
// For saturating operations, we need to shift up the LHS to get the |
--- |
| 5570 |
// proper saturation width, and then shift down again afterwards. |
--- |
5570 |
// proper saturation width, and then shift down again afterwards. |
--- |
| 5571 |
if (Saturating) |
0 |
5571 |
if (Saturating) |
0 |
| 5572 |
LHS = DAG.getNode(ISD::SHL, DL, PromVT, LHS, |
0 |
5572 |
LHS = DAG.getNode(ISD::SHL, DL, PromVT, LHS, |
0 |
| 5573 |
DAG.getConstant(1, DL, ShiftTy)); |
--- |
5573 |
DAG.getConstant(1, DL, ShiftTy)); |
--- |
| 5574 |
SDValue Res = DAG.getNode(Opcode, DL, PromVT, LHS, RHS, Scale); |
0 |
5574 |
SDValue Res = DAG.getNode(Opcode, DL, PromVT, LHS, RHS, Scale); |
0 |
| 5575 |
if (Saturating) |
0 |
5575 |
if (Saturating) |
0 |
| 5576 |
Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, PromVT, Res, |
0 |
5576 |
Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, PromVT, Res, |
0 |
| 5577 |
DAG.getConstant(1, DL, ShiftTy)); |
--- |
5577 |
DAG.getConstant(1, DL, ShiftTy)); |
--- |
| 5578 |
return DAG.getZExtOrTrunc(Res, DL, VT); |
0 |
5578 |
return DAG.getZExtOrTrunc(Res, DL, VT); |
0 |
| 5579 |
} |
--- |
5579 |
} |
--- |
| 5580 |
} |
--- |
5580 |
} |
--- |
| 5581 |
|
--- |
5581 |
|
--- |
| 5582 |
return DAG.getNode(Opcode, DL, VT, LHS, RHS, Scale); |
0 |
5582 |
return DAG.getNode(Opcode, DL, VT, LHS, RHS, Scale); |
0 |
| 5583 |
} |
--- |
5583 |
} |
--- |
| 5584 |
|
--- |
5584 |
|
--- |
| 5585 |
// getUnderlyingArgRegs - Find underlying registers used for a truncated, |
--- |
5585 |
// getUnderlyingArgRegs - Find underlying registers used for a truncated, |
--- |
| 5586 |
// bitcasted, or split argument. Returns a list of |
--- |
5586 |
// bitcasted, or split argument. Returns a list of |
--- |
| 5587 |
static void |
--- |
5587 |
static void |
--- |
| 5588 |
getUnderlyingArgRegs(SmallVectorImpl> &Regs, |
0 |
5588 |
getUnderlyingArgRegs(SmallVectorImpl> &Regs, |
0 |
| 5589 |
const SDValue &N) { |
--- |
5589 |
const SDValue &N) { |
--- |
| 5590 |
switch (N.getOpcode()) { |
0 |
5590 |
switch (N.getOpcode()) { |
0 |
| 5591 |
case ISD::CopyFromReg: { |
0 |
5591 |
case ISD::CopyFromReg: { |
0 |
| 5592 |
SDValue Op = N.getOperand(1); |
0 |
5592 |
SDValue Op = N.getOperand(1); |
0 |
| 5593 |
Regs.emplace_back(cast(Op)->getReg(), |
0 |
5593 |
Regs.emplace_back(cast(Op)->getReg(), |
0 |
| 5594 |
Op.getValueType().getSizeInBits()); |
0 |
5594 |
Op.getValueType().getSizeInBits()); |
0 |
| 5595 |
return; |
0 |
5595 |
return; |
0 |
| 5596 |
} |
--- |
5596 |
} |
--- |
| 5597 |
case ISD::BITCAST: |
0 |
5597 |
case ISD::BITCAST: |
0 |
| 5598 |
case ISD::AssertZext: |
--- |
5598 |
case ISD::AssertZext: |
--- |
| 5599 |
case ISD::AssertSext: |
--- |
5599 |
case ISD::AssertSext: |
--- |
| 5600 |
case ISD::TRUNCATE: |
--- |
5600 |
case ISD::TRUNCATE: |
--- |
| 5601 |
getUnderlyingArgRegs(Regs, N.getOperand(0)); |
0 |
5601 |
getUnderlyingArgRegs(Regs, N.getOperand(0)); |
0 |
| 5602 |
return; |
0 |
5602 |
return; |
0 |
| 5603 |
case ISD::BUILD_PAIR: |
0 |
5603 |
case ISD::BUILD_PAIR: |
0 |
| 5604 |
case ISD::BUILD_VECTOR: |
--- |
5604 |
case ISD::BUILD_VECTOR: |
--- |
| 5605 |
case ISD::CONCAT_VECTORS: |
--- |
5605 |
case ISD::CONCAT_VECTORS: |
--- |
| 5606 |
for (SDValue Op : N->op_values()) |
0 |
5606 |
for (SDValue Op : N->op_values()) |
0 |
| 5607 |
getUnderlyingArgRegs(Regs, Op); |
0 |
5607 |
getUnderlyingArgRegs(Regs, Op); |
0 |
| 5608 |
return; |
0 |
5608 |
return; |
0 |
| 5609 |
default: |
0 |
5609 |
default: |
0 |
| 5610 |
return; |
0 |
5610 |
return; |
0 |
| 5611 |
} |
--- |
5611 |
} |
--- |
| 5612 |
} |
--- |
5612 |
} |
--- |
| 5613 |
|
--- |
5613 |
|
--- |
| 5614 |
/// If the DbgValueInst is a dbg_value of a function argument, create the |
--- |
5614 |
/// If the DbgValueInst is a dbg_value of a function argument, create the |
--- |
| 5615 |
/// corresponding DBG_VALUE machine instruction for it now. At the end of |
--- |
5615 |
/// corresponding DBG_VALUE machine instruction for it now. At the end of |
--- |
| 5616 |
/// instruction selection, they will be inserted to the entry BB. |
--- |
5616 |
/// instruction selection, they will be inserted to the entry BB. |
--- |
| 5617 |
/// We don't currently support this for variadic dbg_values, as they shouldn't |
--- |
5617 |
/// We don't currently support this for variadic dbg_values, as they shouldn't |
--- |
| 5618 |
/// appear for function arguments or in the prologue. |
--- |
5618 |
/// appear for function arguments or in the prologue. |
--- |
| 5619 |
bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( |
0 |
5619 |
bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( |
0 |
| 5620 |
const Value *V, DILocalVariable *Variable, DIExpression *Expr, |
--- |
5620 |
const Value *V, DILocalVariable *Variable, DIExpression *Expr, |
--- |
| 5621 |
DILocation *DL, FuncArgumentDbgValueKind Kind, const SDValue &N) { |
--- |
5621 |
DILocation *DL, FuncArgumentDbgValueKind Kind, const SDValue &N) { |
--- |
| 5622 |
const Argument *Arg = dyn_cast(V); |
0 |
5622 |
const Argument *Arg = dyn_cast(V); |
0 |
| 5623 |
if (!Arg) |
0 |
5623 |
if (!Arg) |
0 |
| 5624 |
return false; |
0 |
5624 |
return false; |
0 |
| 5625 |
|
--- |
5625 |
|
--- |
| 5626 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
5626 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 5627 |
const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); |
0 |
5627 |
const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); |
0 |
| 5628 |
|
--- |
5628 |
|
--- |
| 5629 |
// Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind |
--- |
5629 |
// Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind |
--- |
| 5630 |
// we've been asked to pursue. |
--- |
5630 |
// we've been asked to pursue. |
--- |
| 5631 |
auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr, |
0 |
5631 |
auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr, |
0 |
| 5632 |
bool Indirect) { |
--- |
5632 |
bool Indirect) { |
--- |
| 5633 |
if (Reg.isVirtual() && MF.useDebugInstrRef()) { |
0 |
5633 |
if (Reg.isVirtual() && MF.useDebugInstrRef()) { |
0 |
| 5634 |
// For VRegs, in instruction referencing mode, create a DBG_INSTR_REF |
--- |
5634 |
// For VRegs, in instruction referencing mode, create a DBG_INSTR_REF |
--- |
| 5635 |
// pointing at the VReg, which will be patched up later. |
--- |
5635 |
// pointing at the VReg, which will be patched up later. |
--- |
| 5636 |
auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF); |
0 |
5636 |
auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF); |
0 |
| 5637 |
SmallVector MOs({MachineOperand::CreateReg( |
0 |
5637 |
SmallVector MOs({MachineOperand::CreateReg( |
0 |
| 5638 |
/* Reg */ Reg, /* isDef */ false, /* isImp */ false, |
--- |
5638 |
/* Reg */ Reg, /* isDef */ false, /* isImp */ false, |
--- |
| 5639 |
/* isKill */ false, /* isDead */ false, |
--- |
5639 |
/* isKill */ false, /* isDead */ false, |
--- |
| 5640 |
/* isUndef */ false, /* isEarlyClobber */ false, |
--- |
5640 |
/* isUndef */ false, /* isEarlyClobber */ false, |
--- |
| 5641 |
/* SubReg */ 0, /* isDebug */ true)}); |
0 |
5641 |
/* SubReg */ 0, /* isDebug */ true)}); |
0 |
| 5642 |
|
--- |
5642 |
|
--- |
| 5643 |
auto *NewDIExpr = FragExpr; |
0 |
5643 |
auto *NewDIExpr = FragExpr; |
0 |
| 5644 |
// We don't have an "Indirect" field in DBG_INSTR_REF, fold that into |
--- |
5644 |
// We don't have an "Indirect" field in DBG_INSTR_REF, fold that into |
--- |
| 5645 |
// the DIExpression. |
--- |
5645 |
// the DIExpression. |
--- |
| 5646 |
if (Indirect) |
0 |
5646 |
if (Indirect) |
0 |
| 5647 |
NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore); |
0 |
5647 |
NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore); |
0 |
| 5648 |
SmallVector Ops({dwarf::DW_OP_LLVM_arg, 0}); |
0 |
5648 |
SmallVector Ops({dwarf::DW_OP_LLVM_arg, 0}); |
0 |
| 5649 |
NewDIExpr = DIExpression::prependOpcodes(NewDIExpr, Ops); |
0 |
5649 |
NewDIExpr = DIExpression::prependOpcodes(NewDIExpr, Ops); |
0 |
| 5650 |
return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr); |
0 |
5650 |
return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr); |
0 |
| 5651 |
} else { |
0 |
5651 |
} else { |
0 |
| 5652 |
// Create a completely standard DBG_VALUE. |
--- |
5652 |
// Create a completely standard DBG_VALUE. |
--- |
| 5653 |
auto &Inst = TII->get(TargetOpcode::DBG_VALUE); |
0 |
5653 |
auto &Inst = TII->get(TargetOpcode::DBG_VALUE); |
0 |
| 5654 |
return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr); |
0 |
5654 |
return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr); |
0 |
| 5655 |
} |
--- |
5655 |
} |
--- |
| 5656 |
}; |
0 |
5656 |
}; |
0 |
| 5657 |
|
--- |
5657 |
|
--- |
| 5658 |
if (Kind == FuncArgumentDbgValueKind::Value) { |
0 |
5658 |
if (Kind == FuncArgumentDbgValueKind::Value) { |
0 |
| 5659 |
// ArgDbgValues are hoisted to the beginning of the entry block. So we |
--- |
5659 |
// ArgDbgValues are hoisted to the beginning of the entry block. So we |
--- |
| 5660 |
// should only emit as ArgDbgValue if the dbg.value intrinsic is found in |
--- |
5660 |
// should only emit as ArgDbgValue if the dbg.value intrinsic is found in |
--- |
| 5661 |
// the entry block. |
--- |
5661 |
// the entry block. |
--- |
| 5662 |
bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front(); |
0 |
5662 |
bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front(); |
0 |
| 5663 |
if (!IsInEntryBlock) |
0 |
5663 |
if (!IsInEntryBlock) |
0 |
| 5664 |
return false; |
0 |
5664 |
return false; |
0 |
| 5665 |
|
--- |
5665 |
|
--- |
| 5666 |
// ArgDbgValues are hoisted to the beginning of the entry block. So we |
--- |
5666 |
// ArgDbgValues are hoisted to the beginning of the entry block. So we |
--- |
| 5667 |
// should only emit as ArgDbgValue if the dbg.value intrinsic describes a |
--- |
5667 |
// should only emit as ArgDbgValue if the dbg.value intrinsic describes a |
--- |
| 5668 |
// variable that also is a param. |
--- |
5668 |
// variable that also is a param. |
--- |
| 5669 |
// |
--- |
5669 |
// |
--- |
| 5670 |
// Although, if we are at the top of the entry block already, we can still |
--- |
5670 |
// Although, if we are at the top of the entry block already, we can still |
--- |
| 5671 |
// emit using ArgDbgValue. This might catch some situations when the |
--- |
5671 |
// emit using ArgDbgValue. This might catch some situations when the |
--- |
| 5672 |
// dbg.value refers to an argument that isn't used in the entry block, so |
--- |
5672 |
// dbg.value refers to an argument that isn't used in the entry block, so |
--- |
| 5673 |
// any CopyToReg node would be optimized out and the only way to express |
--- |
5673 |
// any CopyToReg node would be optimized out and the only way to express |
--- |
| 5674 |
// this DBG_VALUE is by using the physical reg (or FI) as done in this |
--- |
5674 |
// this DBG_VALUE is by using the physical reg (or FI) as done in this |
--- |
| 5675 |
// method. ArgDbgValues are hoisted to the beginning of the entry block. So |
--- |
5675 |
// method. ArgDbgValues are hoisted to the beginning of the entry block. So |
--- |
| 5676 |
// we should only emit as ArgDbgValue if the Variable is an argument to the |
--- |
5676 |
// we should only emit as ArgDbgValue if the Variable is an argument to the |
--- |
| 5677 |
// current function, and the dbg.value intrinsic is found in the entry |
--- |
5677 |
// current function, and the dbg.value intrinsic is found in the entry |
--- |
| 5678 |
// block. |
--- |
5678 |
// block. |
--- |
| 5679 |
bool VariableIsFunctionInputArg = Variable->isParameter() && |
0 |
5679 |
bool VariableIsFunctionInputArg = Variable->isParameter() && |
0 |
| 5680 |
!DL->getInlinedAt(); |
0 |
5680 |
!DL->getInlinedAt(); |
0 |
| 5681 |
bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder; |
0 |
5681 |
bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder; |
0 |
| 5682 |
if (!IsInPrologue && !VariableIsFunctionInputArg) |
0 |
5682 |
if (!IsInPrologue && !VariableIsFunctionInputArg) |
0 |
| 5683 |
return false; |
0 |
5683 |
return false; |
0 |
| 5684 |
|
--- |
5684 |
|
--- |
| 5685 |
// Here we assume that a function argument on IR level only can be used to |
--- |
5685 |
// Here we assume that a function argument on IR level only can be used to |
--- |
| 5686 |
// describe one input parameter on source level. If we for example have |
--- |
5686 |
// describe one input parameter on source level. If we for example have |
--- |
| 5687 |
// source code like this |
--- |
5687 |
// source code like this |
--- |
| 5688 |
// |
--- |
5688 |
// |
--- |
| 5689 |
// struct A { long x, y; }; |
--- |
5689 |
// struct A { long x, y; }; |
--- |
| 5690 |
// void foo(struct A a, long b) { |
--- |
5690 |
// void foo(struct A a, long b) { |
--- |
| 5691 |
// ... |
--- |
5691 |
// ... |
--- |
| 5692 |
// b = a.x; |
--- |
5692 |
// b = a.x; |
--- |
| 5693 |
// ... |
--- |
5693 |
// ... |
--- |
| 5694 |
// } |
--- |
5694 |
// } |
--- |
| 5695 |
// |
--- |
5695 |
// |
--- |
| 5696 |
// and IR like this |
--- |
5696 |
// and IR like this |
--- |
| 5697 |
// |
--- |
5697 |
// |
--- |
| 5698 |
// define void @foo(i32 %a1, i32 %a2, i32 %b) { |
--- |
5698 |
// define void @foo(i32 %a1, i32 %a2, i32 %b) { |
--- |
| 5699 |
// entry: |
--- |
5699 |
// entry: |
--- |
| 5700 |
// call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment |
--- |
5700 |
// call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment |
--- |
| 5701 |
// call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment |
--- |
5701 |
// call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment |
--- |
| 5702 |
// call void @llvm.dbg.value(metadata i32 %b, "b", |
--- |
5702 |
// call void @llvm.dbg.value(metadata i32 %b, "b", |
--- |
| 5703 |
// ... |
--- |
5703 |
// ... |
--- |
| 5704 |
// call void @llvm.dbg.value(metadata i32 %a1, "b" |
--- |
5704 |
// call void @llvm.dbg.value(metadata i32 %a1, "b" |
--- |
| 5705 |
// ... |
--- |
5705 |
// ... |
--- |
| 5706 |
// |
--- |
5706 |
// |
--- |
| 5707 |
// then the last dbg.value is describing a parameter "b" using a value that |
--- |
5707 |
// then the last dbg.value is describing a parameter "b" using a value that |
--- |
| 5708 |
// is an argument. But since we already has used %a1 to describe a parameter |
--- |
5708 |
// is an argument. But since we already has used %a1 to describe a parameter |
--- |
| 5709 |
// we should not handle that last dbg.value here (that would result in an |
--- |
5709 |
// we should not handle that last dbg.value here (that would result in an |
--- |
| 5710 |
// incorrect hoisting of the DBG_VALUE to the function entry). |
--- |
5710 |
// incorrect hoisting of the DBG_VALUE to the function entry). |
--- |
| 5711 |
// Notice that we allow one dbg.value per IR level argument, to accommodate |
--- |
5711 |
// Notice that we allow one dbg.value per IR level argument, to accommodate |
--- |
| 5712 |
// for the situation with fragments above. |
--- |
5712 |
// for the situation with fragments above. |
--- |
| 5713 |
if (VariableIsFunctionInputArg) { |
0 |
5713 |
if (VariableIsFunctionInputArg) { |
0 |
| 5714 |
unsigned ArgNo = Arg->getArgNo(); |
0 |
5714 |
unsigned ArgNo = Arg->getArgNo(); |
0 |
| 5715 |
if (ArgNo >= FuncInfo.DescribedArgs.size()) |
0 |
5715 |
if (ArgNo >= FuncInfo.DescribedArgs.size()) |
0 |
| 5716 |
FuncInfo.DescribedArgs.resize(ArgNo + 1, false); |
0 |
5716 |
FuncInfo.DescribedArgs.resize(ArgNo + 1, false); |
0 |
| 5717 |
else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo)) |
0 |
5717 |
else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo)) |
0 |
| 5718 |
return false; |
0 |
5718 |
return false; |
0 |
| 5719 |
FuncInfo.DescribedArgs.set(ArgNo); |
0 |
5719 |
FuncInfo.DescribedArgs.set(ArgNo); |
0 |
| 5720 |
} |
--- |
5720 |
} |
--- |
| 5721 |
} |
--- |
5721 |
} |
--- |
| 5722 |
|
--- |
5722 |
|
--- |
| 5723 |
bool IsIndirect = false; |
0 |
5723 |
bool IsIndirect = false; |
0 |
| 5724 |
std::optional Op; |
0 |
5724 |
std::optional Op; |
0 |
| 5725 |
// Some arguments' frame index is recorded during argument lowering. |
--- |
5725 |
// Some arguments' frame index is recorded during argument lowering. |
--- |
| 5726 |
int FI = FuncInfo.getArgumentFrameIndex(Arg); |
0 |
5726 |
int FI = FuncInfo.getArgumentFrameIndex(Arg); |
0 |
| 5727 |
if (FI != std::numeric_limits::max()) |
0 |
5727 |
if (FI != std::numeric_limits::max()) |
0 |
| 5728 |
Op = MachineOperand::CreateFI(FI); |
0 |
5728 |
Op = MachineOperand::CreateFI(FI); |
0 |
| 5729 |
|
--- |
5729 |
|
--- |
| 5730 |
SmallVector, 8> ArgRegsAndSizes; |
0 |
5730 |
SmallVector, 8> ArgRegsAndSizes; |
0 |
| 5731 |
if (!Op && N.getNode()) { |
0 |
5731 |
if (!Op && N.getNode()) { |
0 |
| 5732 |
getUnderlyingArgRegs(ArgRegsAndSizes, N); |
0 |
5732 |
getUnderlyingArgRegs(ArgRegsAndSizes, N); |
0 |
| 5733 |
Register Reg; |
0 |
5733 |
Register Reg; |
0 |
| 5734 |
if (ArgRegsAndSizes.size() == 1) |
0 |
5734 |
if (ArgRegsAndSizes.size() == 1) |
0 |
| 5735 |
Reg = ArgRegsAndSizes.front().first; |
0 |
5735 |
Reg = ArgRegsAndSizes.front().first; |
0 |
| 5736 |
|
--- |
5736 |
|
--- |
| 5737 |
if (Reg && Reg.isVirtual()) { |
0 |
5737 |
if (Reg && Reg.isVirtual()) { |
0 |
| 5738 |
MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
0 |
5738 |
MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
0 |
| 5739 |
Register PR = RegInfo.getLiveInPhysReg(Reg); |
0 |
5739 |
Register PR = RegInfo.getLiveInPhysReg(Reg); |
0 |
| 5740 |
if (PR) |
0 |
5740 |
if (PR) |
0 |
| 5741 |
Reg = PR; |
0 |
5741 |
Reg = PR; |
0 |
| 5742 |
} |
--- |
5742 |
} |
--- |
| 5743 |
if (Reg) { |
0 |
5743 |
if (Reg) { |
0 |
| 5744 |
Op = MachineOperand::CreateReg(Reg, false); |
0 |
5744 |
Op = MachineOperand::CreateReg(Reg, false); |
0 |
| 5745 |
IsIndirect = Kind != FuncArgumentDbgValueKind::Value; |
0 |
5745 |
IsIndirect = Kind != FuncArgumentDbgValueKind::Value; |
0 |
| 5746 |
} |
--- |
5746 |
} |
--- |
| 5747 |
} |
--- |
5747 |
} |
--- |
| 5748 |
|
--- |
5748 |
|
--- |
| 5749 |
if (!Op && N.getNode()) { |
0 |
5749 |
if (!Op && N.getNode()) { |
0 |
| 5750 |
// Check if frame index is available. |
--- |
5750 |
// Check if frame index is available. |
--- |
| 5751 |
SDValue LCandidate = peekThroughBitcasts(N); |
0 |
5751 |
SDValue LCandidate = peekThroughBitcasts(N); |
0 |
| 5752 |
if (LoadSDNode *LNode = dyn_cast(LCandidate.getNode())) |
0 |
5752 |
if (LoadSDNode *LNode = dyn_cast(LCandidate.getNode())) |
0 |
| 5753 |
if (FrameIndexSDNode *FINode = |
0 |
5753 |
if (FrameIndexSDNode *FINode = |
0 |
| 5754 |
dyn_cast(LNode->getBasePtr().getNode())) |
0 |
5754 |
dyn_cast(LNode->getBasePtr().getNode())) |
0 |
| 5755 |
Op = MachineOperand::CreateFI(FINode->getIndex()); |
0 |
5755 |
Op = MachineOperand::CreateFI(FINode->getIndex()); |
0 |
| 5756 |
} |
--- |
5756 |
} |
--- |
| 5757 |
|
--- |
5757 |
|
--- |
| 5758 |
if (!Op) { |
0 |
5758 |
if (!Op) { |
0 |
| 5759 |
// Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg |
--- |
5759 |
// Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg |
--- |
| 5760 |
auto splitMultiRegDbgValue = [&](ArrayRef> |
0 |
5760 |
auto splitMultiRegDbgValue = [&](ArrayRef> |
0 |
| 5761 |
SplitRegs) { |
--- |
5761 |
SplitRegs) { |
--- |
| 5762 |
unsigned Offset = 0; |
0 |
5762 |
unsigned Offset = 0; |
0 |
| 5763 |
for (const auto &RegAndSize : SplitRegs) { |
0 |
5763 |
for (const auto &RegAndSize : SplitRegs) { |
0 |
| 5764 |
// If the expression is already a fragment, the current register |
--- |
5764 |
// If the expression is already a fragment, the current register |
--- |
| 5765 |
// offset+size might extend beyond the fragment. In this case, only |
--- |
5765 |
// offset+size might extend beyond the fragment. In this case, only |
--- |
| 5766 |
// the register bits that are inside the fragment are relevant. |
--- |
5766 |
// the register bits that are inside the fragment are relevant. |
--- |
| 5767 |
int RegFragmentSizeInBits = RegAndSize.second; |
0 |
5767 |
int RegFragmentSizeInBits = RegAndSize.second; |
0 |
| 5768 |
if (auto ExprFragmentInfo = Expr->getFragmentInfo()) { |
0 |
5768 |
if (auto ExprFragmentInfo = Expr->getFragmentInfo()) { |
0 |
| 5769 |
uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits; |
0 |
5769 |
uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits; |
0 |
| 5770 |
// The register is entirely outside the expression fragment, |
--- |
5770 |
// The register is entirely outside the expression fragment, |
--- |
| 5771 |
// so is irrelevant for debug info. |
--- |
5771 |
// so is irrelevant for debug info. |
--- |
| 5772 |
if (Offset >= ExprFragmentSizeInBits) |
0 |
5772 |
if (Offset >= ExprFragmentSizeInBits) |
0 |
| 5773 |
break; |
0 |
5773 |
break; |
0 |
| 5774 |
// The register is partially outside the expression fragment, only |
--- |
5774 |
// The register is partially outside the expression fragment, only |
--- |
| 5775 |
// the low bits within the fragment are relevant for debug info. |
--- |
5775 |
// the low bits within the fragment are relevant for debug info. |
--- |
| 5776 |
if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) { |
0 |
5776 |
if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) { |
0 |
| 5777 |
RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset; |
0 |
5777 |
RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset; |
0 |
| 5778 |
} |
--- |
5778 |
} |
--- |
| 5779 |
} |
--- |
5779 |
} |
--- |
| 5780 |
|
--- |
5780 |
|
--- |
| 5781 |
auto FragmentExpr = DIExpression::createFragmentExpression( |
0 |
5781 |
auto FragmentExpr = DIExpression::createFragmentExpression( |
0 |
| 5782 |
Expr, Offset, RegFragmentSizeInBits); |
--- |
5782 |
Expr, Offset, RegFragmentSizeInBits); |
--- |
| 5783 |
Offset += RegAndSize.second; |
0 |
5783 |
Offset += RegAndSize.second; |
0 |
| 5784 |
// If a valid fragment expression cannot be created, the variable's |
--- |
5784 |
// If a valid fragment expression cannot be created, the variable's |
--- |
| 5785 |
// correct value cannot be determined and so it is set as Undef. |
--- |
5785 |
// correct value cannot be determined and so it is set as Undef. |
--- |
| 5786 |
if (!FragmentExpr) { |
0 |
5786 |
if (!FragmentExpr) { |
0 |
| 5787 |
SDDbgValue *SDV = DAG.getConstantDbgValue( |
0 |
5787 |
SDDbgValue *SDV = DAG.getConstantDbgValue( |
0 |
| 5788 |
Variable, Expr, UndefValue::get(V->getType()), DL, SDNodeOrder); |
0 |
5788 |
Variable, Expr, UndefValue::get(V->getType()), DL, SDNodeOrder); |
0 |
| 5789 |
DAG.AddDbgValue(SDV, false); |
0 |
5789 |
DAG.AddDbgValue(SDV, false); |
0 |
| 5790 |
continue; |
0 |
5790 |
continue; |
0 |
| 5791 |
} |
0 |
5791 |
} |
0 |
| 5792 |
MachineInstr *NewMI = |
--- |
5792 |
MachineInstr *NewMI = |
--- |
| 5793 |
MakeVRegDbgValue(RegAndSize.first, *FragmentExpr, |
0 |
5793 |
MakeVRegDbgValue(RegAndSize.first, *FragmentExpr, |
0 |
| 5794 |
Kind != FuncArgumentDbgValueKind::Value); |
0 |
5794 |
Kind != FuncArgumentDbgValueKind::Value); |
0 |
| 5795 |
FuncInfo.ArgDbgValues.push_back(NewMI); |
0 |
5795 |
FuncInfo.ArgDbgValues.push_back(NewMI); |
0 |
| 5796 |
} |
--- |
5796 |
} |
--- |
| 5797 |
}; |
0 |
5797 |
}; |
0 |
| 5798 |
|
--- |
5798 |
|
--- |
| 5799 |
// Check if ValueMap has reg number. |
--- |
5799 |
// Check if ValueMap has reg number. |
--- |
| 5800 |
DenseMap::const_iterator |
--- |
5800 |
DenseMap::const_iterator |
--- |
| 5801 |
VMI = FuncInfo.ValueMap.find(V); |
0 |
5801 |
VMI = FuncInfo.ValueMap.find(V); |
0 |
| 5802 |
if (VMI != FuncInfo.ValueMap.end()) { |
0 |
5802 |
if (VMI != FuncInfo.ValueMap.end()) { |
0 |
| 5803 |
const auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
5803 |
const auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 5804 |
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second, |
0 |
5804 |
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second, |
0 |
| 5805 |
V->getType(), std::nullopt); |
0 |
5805 |
V->getType(), std::nullopt); |
0 |
| 5806 |
if (RFV.occupiesMultipleRegs()) { |
0 |
5806 |
if (RFV.occupiesMultipleRegs()) { |
0 |
| 5807 |
splitMultiRegDbgValue(RFV.getRegsAndSizes()); |
0 |
5807 |
splitMultiRegDbgValue(RFV.getRegsAndSizes()); |
0 |
| 5808 |
return true; |
0 |
5808 |
return true; |
0 |
| 5809 |
} |
--- |
5809 |
} |
--- |
| 5810 |
|
--- |
5810 |
|
--- |
| 5811 |
Op = MachineOperand::CreateReg(VMI->second, false); |
0 |
5811 |
Op = MachineOperand::CreateReg(VMI->second, false); |
0 |
| 5812 |
IsIndirect = Kind != FuncArgumentDbgValueKind::Value; |
0 |
5812 |
IsIndirect = Kind != FuncArgumentDbgValueKind::Value; |
0 |
| 5813 |
} else if (ArgRegsAndSizes.size() > 1) { |
0 |
5813 |
} else if (ArgRegsAndSizes.size() > 1) { |
0 |
| 5814 |
// This was split due to the calling convention, and no virtual register |
--- |
5814 |
// This was split due to the calling convention, and no virtual register |
--- |
| 5815 |
// mapping exists for the value. |
--- |
5815 |
// mapping exists for the value. |
--- |
| 5816 |
splitMultiRegDbgValue(ArgRegsAndSizes); |
0 |
5816 |
splitMultiRegDbgValue(ArgRegsAndSizes); |
0 |
| 5817 |
return true; |
0 |
5817 |
return true; |
0 |
| 5818 |
} |
--- |
5818 |
} |
--- |
| 5819 |
} |
--- |
5819 |
} |
--- |
| 5820 |
|
--- |
5820 |
|
--- |
| 5821 |
if (!Op) |
0 |
5821 |
if (!Op) |
0 |
| 5822 |
return false; |
0 |
5822 |
return false; |
0 |
| 5823 |
|
--- |
5823 |
|
--- |
| 5824 |
// If the expression refers to the entry value of an Argument, use the |
--- |
5824 |
// If the expression refers to the entry value of an Argument, use the |
--- |
| 5825 |
// corresponding livein physical register. As per the Verifier, this is only |
--- |
5825 |
// corresponding livein physical register. As per the Verifier, this is only |
--- |
| 5826 |
// allowed for swiftasync Arguments. |
--- |
5826 |
// allowed for swiftasync Arguments. |
--- |
| 5827 |
if (Op->isReg() && Expr->isEntryValue()) { |
0 |
5827 |
if (Op->isReg() && Expr->isEntryValue()) { |
0 |
| 5828 |
assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync)); |
0 |
5828 |
assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync)); |
0 |
| 5829 |
auto OpReg = Op->getReg(); |
0 |
5829 |
auto OpReg = Op->getReg(); |
0 |
| 5830 |
for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins()) |
0 |
5830 |
for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins()) |
0 |
| 5831 |
if (OpReg == VirtReg || OpReg == PhysReg) { |
0 |
5831 |
if (OpReg == VirtReg || OpReg == PhysReg) { |
0 |
| 5832 |
SDDbgValue *SDV = DAG.getVRegDbgValue( |
0 |
5832 |
SDDbgValue *SDV = DAG.getVRegDbgValue( |
0 |
| 5833 |
Variable, Expr, PhysReg, |
--- |
5833 |
Variable, Expr, PhysReg, |
--- |
| 5834 |
Kind != FuncArgumentDbgValueKind::Value /*is indirect*/, DL, |
--- |
5834 |
Kind != FuncArgumentDbgValueKind::Value /*is indirect*/, DL, |
--- |
| 5835 |
SDNodeOrder); |
--- |
5835 |
SDNodeOrder); |
--- |
| 5836 |
DAG.AddDbgValue(SDV, false /*treat as dbg.declare byval parameter*/); |
0 |
5836 |
DAG.AddDbgValue(SDV, false /*treat as dbg.declare byval parameter*/); |
0 |
| 5837 |
return true; |
0 |
5837 |
return true; |
0 |
| 5838 |
} |
--- |
5838 |
} |
--- |
| 5839 |
LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but " |
0 |
5839 |
LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but " |
0 |
| 5840 |
"couldn't find a physical register\n"); |
--- |
5840 |
"couldn't find a physical register\n"); |
--- |
| 5841 |
return true; |
0 |
5841 |
return true; |
0 |
| 5842 |
} |
--- |
5842 |
} |
--- |
| 5843 |
|
--- |
5843 |
|
--- |
| 5844 |
assert(Variable->isValidLocationForIntrinsic(DL) && |
0 |
5844 |
assert(Variable->isValidLocationForIntrinsic(DL) && |
0 |
| 5845 |
"Expected inlined-at fields to agree"); |
--- |
5845 |
"Expected inlined-at fields to agree"); |
--- |
| 5846 |
MachineInstr *NewMI = nullptr; |
0 |
5846 |
MachineInstr *NewMI = nullptr; |
0 |
| 5847 |
|
--- |
5847 |
|
--- |
| 5848 |
if (Op->isReg()) |
0 |
5848 |
if (Op->isReg()) |
0 |
| 5849 |
NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect); |
0 |
5849 |
NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect); |
0 |
| 5850 |
else |
--- |
5850 |
else |
--- |
| 5851 |
NewMI = BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), true, *Op, |
0 |
5851 |
NewMI = BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), true, *Op, |
0 |
| 5852 |
Variable, Expr); |
0 |
5852 |
Variable, Expr); |
0 |
| 5853 |
|
--- |
5853 |
|
--- |
| 5854 |
// Otherwise, use ArgDbgValues. |
--- |
5854 |
// Otherwise, use ArgDbgValues. |
--- |
| 5855 |
FuncInfo.ArgDbgValues.push_back(NewMI); |
0 |
5855 |
FuncInfo.ArgDbgValues.push_back(NewMI); |
0 |
| 5856 |
return true; |
0 |
5856 |
return true; |
0 |
| 5857 |
} |
0 |
5857 |
} |
0 |
| 5858 |
|
--- |
5858 |
|
--- |
| 5859 |
/// Return the appropriate SDDbgValue based on N. |
--- |
5859 |
/// Return the appropriate SDDbgValue based on N. |
--- |
| 5860 |
SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N, |
0 |
5860 |
SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N, |
0 |
| 5861 |
DILocalVariable *Variable, |
--- |
5861 |
DILocalVariable *Variable, |
--- |
| 5862 |
DIExpression *Expr, |
--- |
5862 |
DIExpression *Expr, |
--- |
| 5863 |
const DebugLoc &dl, |
--- |
5863 |
const DebugLoc &dl, |
--- |
| 5864 |
unsigned DbgSDNodeOrder) { |
--- |
5864 |
unsigned DbgSDNodeOrder) { |
--- |
| 5865 |
if (auto *FISDN = dyn_cast(N.getNode())) { |
0 |
5865 |
if (auto *FISDN = dyn_cast(N.getNode())) { |
0 |
| 5866 |
// Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe |
--- |
5866 |
// Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe |
--- |
| 5867 |
// stack slot locations. |
--- |
5867 |
// stack slot locations. |
--- |
| 5868 |
// |
--- |
5868 |
// |
--- |
| 5869 |
// Consider "int x = 0; int *px = &x;". There are two kinds of interesting |
--- |
5869 |
// Consider "int x = 0; int *px = &x;". There are two kinds of interesting |
--- |
| 5870 |
// debug values here after optimization: |
--- |
5870 |
// debug values here after optimization: |
--- |
| 5871 |
// |
--- |
5871 |
// |
--- |
| 5872 |
// dbg.value(i32* %px, !"int *px", !DIExpression()), and |
--- |
5872 |
// dbg.value(i32* %px, !"int *px", !DIExpression()), and |
--- |
| 5873 |
// dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref)) |
--- |
5873 |
// dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref)) |
--- |
| 5874 |
// |
--- |
5874 |
// |
--- |
| 5875 |
// Both describe the direct values of their associated variables. |
--- |
5875 |
// Both describe the direct values of their associated variables. |
--- |
| 5876 |
return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(), |
0 |
5876 |
return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(), |
0 |
| 5877 |
/*IsIndirect*/ false, dl, DbgSDNodeOrder); |
0 |
5877 |
/*IsIndirect*/ false, dl, DbgSDNodeOrder); |
0 |
| 5878 |
} |
--- |
5878 |
} |
--- |
| 5879 |
return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(), |
0 |
5879 |
return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(), |
0 |
| 5880 |
/*IsIndirect*/ false, dl, DbgSDNodeOrder); |
0 |
5880 |
/*IsIndirect*/ false, dl, DbgSDNodeOrder); |
0 |
| 5881 |
} |
--- |
5881 |
} |
--- |
| 5882 |
|
--- |
5882 |
|
--- |
| 5883 |
static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) { |
0 |
5883 |
static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) { |
0 |
| 5884 |
switch (Intrinsic) { |
0 |
5884 |
switch (Intrinsic) { |
0 |
| 5885 |
case Intrinsic::smul_fix: |
0 |
5885 |
case Intrinsic::smul_fix: |
0 |
| 5886 |
return ISD::SMULFIX; |
0 |
5886 |
return ISD::SMULFIX; |
0 |
| 5887 |
case Intrinsic::umul_fix: |
0 |
5887 |
case Intrinsic::umul_fix: |
0 |
| 5888 |
return ISD::UMULFIX; |
0 |
5888 |
return ISD::UMULFIX; |
0 |
| 5889 |
case Intrinsic::smul_fix_sat: |
0 |
5889 |
case Intrinsic::smul_fix_sat: |
0 |
| 5890 |
return ISD::SMULFIXSAT; |
0 |
5890 |
return ISD::SMULFIXSAT; |
0 |
| 5891 |
case Intrinsic::umul_fix_sat: |
0 |
5891 |
case Intrinsic::umul_fix_sat: |
0 |
| 5892 |
return ISD::UMULFIXSAT; |
0 |
5892 |
return ISD::UMULFIXSAT; |
0 |
| 5893 |
case Intrinsic::sdiv_fix: |
0 |
5893 |
case Intrinsic::sdiv_fix: |
0 |
| 5894 |
return ISD::SDIVFIX; |
0 |
5894 |
return ISD::SDIVFIX; |
0 |
| 5895 |
case Intrinsic::udiv_fix: |
0 |
5895 |
case Intrinsic::udiv_fix: |
0 |
| 5896 |
return ISD::UDIVFIX; |
0 |
5896 |
return ISD::UDIVFIX; |
0 |
| 5897 |
case Intrinsic::sdiv_fix_sat: |
0 |
5897 |
case Intrinsic::sdiv_fix_sat: |
0 |
| 5898 |
return ISD::SDIVFIXSAT; |
0 |
5898 |
return ISD::SDIVFIXSAT; |
0 |
| 5899 |
case Intrinsic::udiv_fix_sat: |
0 |
5899 |
case Intrinsic::udiv_fix_sat: |
0 |
| 5900 |
return ISD::UDIVFIXSAT; |
0 |
5900 |
return ISD::UDIVFIXSAT; |
0 |
| 5901 |
default: |
0 |
5901 |
default: |
0 |
| 5902 |
llvm_unreachable("Unhandled fixed point intrinsic"); |
0 |
5902 |
llvm_unreachable("Unhandled fixed point intrinsic"); |
0 |
| 5903 |
} |
--- |
5903 |
} |
--- |
| 5904 |
} |
--- |
5904 |
} |
--- |
| 5905 |
|
--- |
5905 |
|
--- |
| 5906 |
void SelectionDAGBuilder::lowerCallToExternalSymbol(const CallInst &I, |
0 |
5906 |
void SelectionDAGBuilder::lowerCallToExternalSymbol(const CallInst &I, |
0 |
| 5907 |
const char *FunctionName) { |
--- |
5907 |
const char *FunctionName) { |
--- |
| 5908 |
assert(FunctionName && "FunctionName must not be nullptr"); |
0 |
5908 |
assert(FunctionName && "FunctionName must not be nullptr"); |
0 |
| 5909 |
SDValue Callee = DAG.getExternalSymbol( |
0 |
5909 |
SDValue Callee = DAG.getExternalSymbol( |
0 |
| 5910 |
FunctionName, |
--- |
5910 |
FunctionName, |
--- |
| 5911 |
DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout())); |
0 |
5911 |
DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout())); |
0 |
| 5912 |
LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall()); |
0 |
5912 |
LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall()); |
0 |
| 5913 |
} |
0 |
5913 |
} |
0 |
| 5914 |
|
--- |
5914 |
|
--- |
| 5915 |
/// Given a @llvm.call.preallocated.setup, return the corresponding |
--- |
5915 |
/// Given a @llvm.call.preallocated.setup, return the corresponding |
--- |
| 5916 |
/// preallocated call. |
--- |
5916 |
/// preallocated call. |
--- |
| 5917 |
static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) { |
0 |
5917 |
static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) { |
0 |
| 5918 |
assert(cast(PreallocatedSetup) |
0 |
5918 |
assert(cast(PreallocatedSetup) |
0 |
| 5919 |
->getCalledFunction() |
--- |
5919 |
->getCalledFunction() |
--- |
| 5920 |
->getIntrinsicID() == Intrinsic::call_preallocated_setup && |
--- |
5920 |
->getIntrinsicID() == Intrinsic::call_preallocated_setup && |
--- |
| 5921 |
"expected call_preallocated_setup Value"); |
--- |
5921 |
"expected call_preallocated_setup Value"); |
--- |
| 5922 |
for (const auto *U : PreallocatedSetup->users()) { |
0 |
5922 |
for (const auto *U : PreallocatedSetup->users()) { |
0 |
| 5923 |
auto *UseCall = cast(U); |
0 |
5923 |
auto *UseCall = cast(U); |
0 |
| 5924 |
const Function *Fn = UseCall->getCalledFunction(); |
0 |
5924 |
const Function *Fn = UseCall->getCalledFunction(); |
0 |
| 5925 |
if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) { |
0 |
5925 |
if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) { |
0 |
| 5926 |
return UseCall; |
0 |
5926 |
return UseCall; |
0 |
| 5927 |
} |
--- |
5927 |
} |
--- |
| 5928 |
} |
--- |
5928 |
} |
--- |
| 5929 |
llvm_unreachable("expected corresponding call to preallocated setup/arg"); |
0 |
5929 |
llvm_unreachable("expected corresponding call to preallocated setup/arg"); |
0 |
| 5930 |
} |
--- |
5930 |
} |
--- |
| 5931 |
|
--- |
5931 |
|
--- |
| 5932 |
/// Lower the call to the specified intrinsic function. |
--- |
5932 |
/// Lower the call to the specified intrinsic function. |
--- |
| 5933 |
void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, |
3 |
5933 |
void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, |
0 |
| 5934 |
unsigned Intrinsic) { |
--- |
5934 |
unsigned Intrinsic) { |
--- |
| 5935 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
3 |
5935 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 5936 |
SDLoc sdl = getCurSDLoc(); |
3 |
5936 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 5937 |
DebugLoc dl = getCurDebugLoc(); |
3 |
5937 |
DebugLoc dl = getCurDebugLoc(); |
0 |
| 5938 |
SDValue Res; |
3 |
5938 |
SDValue Res; |
0 |
| 5939 |
|
--- |
5939 |
|
--- |
| 5940 |
SDNodeFlags Flags; |
3 |
5940 |
SDNodeFlags Flags; |
0 |
| 5941 |
if (auto *FPOp = dyn_cast(&I)) |
3 |
5941 |
if (auto *FPOp = dyn_cast(&I)) |
0 |
| 5942 |
Flags.copyFMF(*FPOp); |
0 |
5942 |
Flags.copyFMF(*FPOp); |
0 |
| 5943 |
|
--- |
5943 |
|
--- |
| 5944 |
switch (Intrinsic) { |
3 |
5944 |
switch (Intrinsic) { |
0 |
| 5945 |
default: |
0 |
5945 |
default: |
0 |
| 5946 |
// By default, turn this into a target intrinsic node. |
--- |
5946 |
// By default, turn this into a target intrinsic node. |
--- |
| 5947 |
visitTargetIntrinsic(I, Intrinsic); |
0 |
5947 |
visitTargetIntrinsic(I, Intrinsic); |
0 |
| 5948 |
return; |
0 |
5948 |
return; |
0 |
| 5949 |
case Intrinsic::vscale: { |
0 |
5949 |
case Intrinsic::vscale: { |
0 |
| 5950 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
5950 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 5951 |
setValue(&I, DAG.getVScale(sdl, VT, APInt(VT.getSizeInBits(), 1))); |
0 |
5951 |
setValue(&I, DAG.getVScale(sdl, VT, APInt(VT.getSizeInBits(), 1))); |
0 |
| 5952 |
return; |
0 |
5952 |
return; |
0 |
| 5953 |
} |
--- |
5953 |
} |
--- |
| 5954 |
case Intrinsic::vastart: visitVAStart(I); return; |
0 |
5954 |
case Intrinsic::vastart: visitVAStart(I); return; |
0 |
| 5955 |
case Intrinsic::vaend: visitVAEnd(I); return; |
0 |
5955 |
case Intrinsic::vaend: visitVAEnd(I); return; |
0 |
| 5956 |
case Intrinsic::vacopy: visitVACopy(I); return; |
0 |
5956 |
case Intrinsic::vacopy: visitVACopy(I); return; |
0 |
| 5957 |
case Intrinsic::returnaddress: |
0 |
5957 |
case Intrinsic::returnaddress: |
0 |
| 5958 |
setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, |
0 |
5958 |
setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, |
0 |
| 5959 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
5959 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
| 5960 |
getValue(I.getArgOperand(0)))); |
0 |
5960 |
getValue(I.getArgOperand(0)))); |
0 |
| 5961 |
return; |
0 |
5961 |
return; |
0 |
| 5962 |
case Intrinsic::addressofreturnaddress: |
0 |
5962 |
case Intrinsic::addressofreturnaddress: |
0 |
| 5963 |
setValue(&I, |
0 |
5963 |
setValue(&I, |
0 |
| 5964 |
DAG.getNode(ISD::ADDROFRETURNADDR, sdl, |
0 |
5964 |
DAG.getNode(ISD::ADDROFRETURNADDR, sdl, |
0 |
| 5965 |
TLI.getValueType(DAG.getDataLayout(), I.getType()))); |
0 |
5965 |
TLI.getValueType(DAG.getDataLayout(), I.getType()))); |
0 |
| 5966 |
return; |
0 |
5966 |
return; |
0 |
| 5967 |
case Intrinsic::sponentry: |
0 |
5967 |
case Intrinsic::sponentry: |
0 |
| 5968 |
setValue(&I, |
0 |
5968 |
setValue(&I, |
0 |
| 5969 |
DAG.getNode(ISD::SPONENTRY, sdl, |
0 |
5969 |
DAG.getNode(ISD::SPONENTRY, sdl, |
0 |
| 5970 |
TLI.getValueType(DAG.getDataLayout(), I.getType()))); |
0 |
5970 |
TLI.getValueType(DAG.getDataLayout(), I.getType()))); |
0 |
| 5971 |
return; |
0 |
5971 |
return; |
0 |
| 5972 |
case Intrinsic::frameaddress: |
0 |
5972 |
case Intrinsic::frameaddress: |
0 |
| 5973 |
setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, |
0 |
5973 |
setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, |
0 |
| 5974 |
TLI.getFrameIndexTy(DAG.getDataLayout()), |
0 |
5974 |
TLI.getFrameIndexTy(DAG.getDataLayout()), |
0 |
| 5975 |
getValue(I.getArgOperand(0)))); |
0 |
5975 |
getValue(I.getArgOperand(0)))); |
0 |
| 5976 |
return; |
0 |
5976 |
return; |
0 |
| 5977 |
case Intrinsic::read_volatile_register: |
0 |
5977 |
case Intrinsic::read_volatile_register: |
0 |
| 5978 |
case Intrinsic::read_register: { |
--- |
5978 |
case Intrinsic::read_register: { |
--- |
| 5979 |
Value *Reg = I.getArgOperand(0); |
0 |
5979 |
Value *Reg = I.getArgOperand(0); |
0 |
| 5980 |
SDValue Chain = getRoot(); |
0 |
5980 |
SDValue Chain = getRoot(); |
0 |
| 5981 |
SDValue RegName = |
--- |
5981 |
SDValue RegName = |
--- |
| 5982 |
DAG.getMDNode(cast(cast(Reg)->getMetadata())); |
0 |
5982 |
DAG.getMDNode(cast(cast(Reg)->getMetadata())); |
0 |
| 5983 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
5983 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 5984 |
Res = DAG.getNode(ISD::READ_REGISTER, sdl, |
0 |
5984 |
Res = DAG.getNode(ISD::READ_REGISTER, sdl, |
0 |
| 5985 |
DAG.getVTList(VT, MVT::Other), Chain, RegName); |
0 |
5985 |
DAG.getVTList(VT, MVT::Other), Chain, RegName); |
0 |
| 5986 |
setValue(&I, Res); |
0 |
5986 |
setValue(&I, Res); |
0 |
| 5987 |
DAG.setRoot(Res.getValue(1)); |
0 |
5987 |
DAG.setRoot(Res.getValue(1)); |
0 |
| 5988 |
return; |
0 |
5988 |
return; |
0 |
| 5989 |
} |
--- |
5989 |
} |
--- |
| 5990 |
case Intrinsic::write_register: { |
0 |
5990 |
case Intrinsic::write_register: { |
0 |
| 5991 |
Value *Reg = I.getArgOperand(0); |
0 |
5991 |
Value *Reg = I.getArgOperand(0); |
0 |
| 5992 |
Value *RegValue = I.getArgOperand(1); |
0 |
5992 |
Value *RegValue = I.getArgOperand(1); |
0 |
| 5993 |
SDValue Chain = getRoot(); |
0 |
5993 |
SDValue Chain = getRoot(); |
0 |
| 5994 |
SDValue RegName = |
--- |
5994 |
SDValue RegName = |
--- |
| 5995 |
DAG.getMDNode(cast(cast(Reg)->getMetadata())); |
0 |
5995 |
DAG.getMDNode(cast(cast(Reg)->getMetadata())); |
0 |
| 5996 |
DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain, |
0 |
5996 |
DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain, |
0 |
| 5997 |
RegName, getValue(RegValue))); |
--- |
5997 |
RegName, getValue(RegValue))); |
--- |
| 5998 |
return; |
0 |
5998 |
return; |
0 |
| 5999 |
} |
--- |
5999 |
} |
--- |
| 6000 |
case Intrinsic::memcpy: { |
0 |
6000 |
case Intrinsic::memcpy: { |
0 |
| 6001 |
const auto &MCI = cast(I); |
0 |
6001 |
const auto &MCI = cast(I); |
0 |
| 6002 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6002 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6003 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6003 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6004 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
6004 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
| 6005 |
// @llvm.memcpy defines 0 and 1 to both mean no alignment. |
--- |
6005 |
// @llvm.memcpy defines 0 and 1 to both mean no alignment. |
--- |
| 6006 |
Align DstAlign = MCI.getDestAlign().valueOrOne(); |
0 |
6006 |
Align DstAlign = MCI.getDestAlign().valueOrOne(); |
0 |
| 6007 |
Align SrcAlign = MCI.getSourceAlign().valueOrOne(); |
0 |
6007 |
Align SrcAlign = MCI.getSourceAlign().valueOrOne(); |
0 |
| 6008 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
6008 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
| 6009 |
bool isVol = MCI.isVolatile(); |
0 |
6009 |
bool isVol = MCI.isVolatile(); |
0 |
| 6010 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6010 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6011 |
// FIXME: Support passing different dest/src alignments to the memcpy DAG |
--- |
6011 |
// FIXME: Support passing different dest/src alignments to the memcpy DAG |
--- |
| 6012 |
// node. |
--- |
6012 |
// node. |
--- |
| 6013 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
6013 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
| 6014 |
SDValue MC = DAG.getMemcpy( |
0 |
6014 |
SDValue MC = DAG.getMemcpy( |
0 |
| 6015 |
Root, sdl, Op1, Op2, Op3, Alignment, isVol, |
--- |
6015 |
Root, sdl, Op1, Op2, Op3, Alignment, isVol, |
--- |
| 6016 |
/* AlwaysInline */ false, isTC, MachinePointerInfo(I.getArgOperand(0)), |
0 |
6016 |
/* AlwaysInline */ false, isTC, MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 6017 |
MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), AA); |
0 |
6017 |
MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), AA); |
0 |
| 6018 |
updateDAGForMaybeTailCall(MC); |
0 |
6018 |
updateDAGForMaybeTailCall(MC); |
0 |
| 6019 |
return; |
0 |
6019 |
return; |
0 |
| 6020 |
} |
--- |
6020 |
} |
--- |
| 6021 |
case Intrinsic::memcpy_inline: { |
0 |
6021 |
case Intrinsic::memcpy_inline: { |
0 |
| 6022 |
const auto &MCI = cast(I); |
0 |
6022 |
const auto &MCI = cast(I); |
0 |
| 6023 |
SDValue Dst = getValue(I.getArgOperand(0)); |
0 |
6023 |
SDValue Dst = getValue(I.getArgOperand(0)); |
0 |
| 6024 |
SDValue Src = getValue(I.getArgOperand(1)); |
0 |
6024 |
SDValue Src = getValue(I.getArgOperand(1)); |
0 |
| 6025 |
SDValue Size = getValue(I.getArgOperand(2)); |
0 |
6025 |
SDValue Size = getValue(I.getArgOperand(2)); |
0 |
| 6026 |
assert(isa(Size) && "memcpy_inline needs constant size"); |
0 |
6026 |
assert(isa(Size) && "memcpy_inline needs constant size"); |
0 |
| 6027 |
// @llvm.memcpy.inline defines 0 and 1 to both mean no alignment. |
--- |
6027 |
// @llvm.memcpy.inline defines 0 and 1 to both mean no alignment. |
--- |
| 6028 |
Align DstAlign = MCI.getDestAlign().valueOrOne(); |
0 |
6028 |
Align DstAlign = MCI.getDestAlign().valueOrOne(); |
0 |
| 6029 |
Align SrcAlign = MCI.getSourceAlign().valueOrOne(); |
0 |
6029 |
Align SrcAlign = MCI.getSourceAlign().valueOrOne(); |
0 |
| 6030 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
6030 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
| 6031 |
bool isVol = MCI.isVolatile(); |
0 |
6031 |
bool isVol = MCI.isVolatile(); |
0 |
| 6032 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6032 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6033 |
// FIXME: Support passing different dest/src alignments to the memcpy DAG |
--- |
6033 |
// FIXME: Support passing different dest/src alignments to the memcpy DAG |
--- |
| 6034 |
// node. |
--- |
6034 |
// node. |
--- |
| 6035 |
SDValue MC = DAG.getMemcpy( |
0 |
6035 |
SDValue MC = DAG.getMemcpy( |
0 |
| 6036 |
getRoot(), sdl, Dst, Src, Size, Alignment, isVol, |
--- |
6036 |
getRoot(), sdl, Dst, Src, Size, Alignment, isVol, |
--- |
| 6037 |
/* AlwaysInline */ true, isTC, MachinePointerInfo(I.getArgOperand(0)), |
0 |
6037 |
/* AlwaysInline */ true, isTC, MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 6038 |
MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), AA); |
0 |
6038 |
MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), AA); |
0 |
| 6039 |
updateDAGForMaybeTailCall(MC); |
0 |
6039 |
updateDAGForMaybeTailCall(MC); |
0 |
| 6040 |
return; |
0 |
6040 |
return; |
0 |
| 6041 |
} |
--- |
6041 |
} |
--- |
| 6042 |
case Intrinsic::memset: { |
0 |
6042 |
case Intrinsic::memset: { |
0 |
| 6043 |
const auto &MSI = cast(I); |
0 |
6043 |
const auto &MSI = cast(I); |
0 |
| 6044 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6044 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6045 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6045 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6046 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
6046 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
| 6047 |
// @llvm.memset defines 0 and 1 to both mean no alignment. |
--- |
6047 |
// @llvm.memset defines 0 and 1 to both mean no alignment. |
--- |
| 6048 |
Align Alignment = MSI.getDestAlign().valueOrOne(); |
0 |
6048 |
Align Alignment = MSI.getDestAlign().valueOrOne(); |
0 |
| 6049 |
bool isVol = MSI.isVolatile(); |
0 |
6049 |
bool isVol = MSI.isVolatile(); |
0 |
| 6050 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6050 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6051 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
6051 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
| 6052 |
SDValue MS = DAG.getMemset( |
0 |
6052 |
SDValue MS = DAG.getMemset( |
0 |
| 6053 |
Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, |
--- |
6053 |
Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, |
--- |
| 6054 |
isTC, MachinePointerInfo(I.getArgOperand(0)), I.getAAMetadata()); |
0 |
6054 |
isTC, MachinePointerInfo(I.getArgOperand(0)), I.getAAMetadata()); |
0 |
| 6055 |
updateDAGForMaybeTailCall(MS); |
0 |
6055 |
updateDAGForMaybeTailCall(MS); |
0 |
| 6056 |
return; |
0 |
6056 |
return; |
0 |
| 6057 |
} |
--- |
6057 |
} |
--- |
| 6058 |
case Intrinsic::memset_inline: { |
0 |
6058 |
case Intrinsic::memset_inline: { |
0 |
| 6059 |
const auto &MSII = cast(I); |
0 |
6059 |
const auto &MSII = cast(I); |
0 |
| 6060 |
SDValue Dst = getValue(I.getArgOperand(0)); |
0 |
6060 |
SDValue Dst = getValue(I.getArgOperand(0)); |
0 |
| 6061 |
SDValue Value = getValue(I.getArgOperand(1)); |
0 |
6061 |
SDValue Value = getValue(I.getArgOperand(1)); |
0 |
| 6062 |
SDValue Size = getValue(I.getArgOperand(2)); |
0 |
6062 |
SDValue Size = getValue(I.getArgOperand(2)); |
0 |
| 6063 |
assert(isa(Size) && "memset_inline needs constant size"); |
0 |
6063 |
assert(isa(Size) && "memset_inline needs constant size"); |
0 |
| 6064 |
// @llvm.memset defines 0 and 1 to both mean no alignment. |
--- |
6064 |
// @llvm.memset defines 0 and 1 to both mean no alignment. |
--- |
| 6065 |
Align DstAlign = MSII.getDestAlign().valueOrOne(); |
0 |
6065 |
Align DstAlign = MSII.getDestAlign().valueOrOne(); |
0 |
| 6066 |
bool isVol = MSII.isVolatile(); |
0 |
6066 |
bool isVol = MSII.isVolatile(); |
0 |
| 6067 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6067 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6068 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
6068 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
| 6069 |
SDValue MC = DAG.getMemset(Root, sdl, Dst, Value, Size, DstAlign, isVol, |
0 |
6069 |
SDValue MC = DAG.getMemset(Root, sdl, Dst, Value, Size, DstAlign, isVol, |
0 |
| 6070 |
/* AlwaysInline */ true, isTC, |
--- |
6070 |
/* AlwaysInline */ true, isTC, |
--- |
| 6071 |
MachinePointerInfo(I.getArgOperand(0)), |
0 |
6071 |
MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 6072 |
I.getAAMetadata()); |
0 |
6072 |
I.getAAMetadata()); |
0 |
| 6073 |
updateDAGForMaybeTailCall(MC); |
0 |
6073 |
updateDAGForMaybeTailCall(MC); |
0 |
| 6074 |
return; |
0 |
6074 |
return; |
0 |
| 6075 |
} |
--- |
6075 |
} |
--- |
| 6076 |
case Intrinsic::memmove: { |
0 |
6076 |
case Intrinsic::memmove: { |
0 |
| 6077 |
const auto &MMI = cast(I); |
0 |
6077 |
const auto &MMI = cast(I); |
0 |
| 6078 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6078 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6079 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6079 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6080 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
6080 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
| 6081 |
// @llvm.memmove defines 0 and 1 to both mean no alignment. |
--- |
6081 |
// @llvm.memmove defines 0 and 1 to both mean no alignment. |
--- |
| 6082 |
Align DstAlign = MMI.getDestAlign().valueOrOne(); |
0 |
6082 |
Align DstAlign = MMI.getDestAlign().valueOrOne(); |
0 |
| 6083 |
Align SrcAlign = MMI.getSourceAlign().valueOrOne(); |
0 |
6083 |
Align SrcAlign = MMI.getSourceAlign().valueOrOne(); |
0 |
| 6084 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
6084 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
| 6085 |
bool isVol = MMI.isVolatile(); |
0 |
6085 |
bool isVol = MMI.isVolatile(); |
0 |
| 6086 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6086 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6087 |
// FIXME: Support passing different dest/src alignments to the memmove DAG |
--- |
6087 |
// FIXME: Support passing different dest/src alignments to the memmove DAG |
--- |
| 6088 |
// node. |
--- |
6088 |
// node. |
--- |
| 6089 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
6089 |
SDValue Root = isVol ? getRoot() : getMemoryRoot(); |
0 |
| 6090 |
SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, |
0 |
6090 |
SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, |
0 |
| 6091 |
isTC, MachinePointerInfo(I.getArgOperand(0)), |
0 |
6091 |
isTC, MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 6092 |
MachinePointerInfo(I.getArgOperand(1)), |
0 |
6092 |
MachinePointerInfo(I.getArgOperand(1)), |
0 |
| 6093 |
I.getAAMetadata(), AA); |
0 |
6093 |
I.getAAMetadata(), AA); |
0 |
| 6094 |
updateDAGForMaybeTailCall(MM); |
0 |
6094 |
updateDAGForMaybeTailCall(MM); |
0 |
| 6095 |
return; |
0 |
6095 |
return; |
0 |
| 6096 |
} |
--- |
6096 |
} |
--- |
| 6097 |
case Intrinsic::memcpy_element_unordered_atomic: { |
0 |
6097 |
case Intrinsic::memcpy_element_unordered_atomic: { |
0 |
| 6098 |
const AtomicMemCpyInst &MI = cast(I); |
0 |
6098 |
const AtomicMemCpyInst &MI = cast(I); |
0 |
| 6099 |
SDValue Dst = getValue(MI.getRawDest()); |
0 |
6099 |
SDValue Dst = getValue(MI.getRawDest()); |
0 |
| 6100 |
SDValue Src = getValue(MI.getRawSource()); |
0 |
6100 |
SDValue Src = getValue(MI.getRawSource()); |
0 |
| 6101 |
SDValue Length = getValue(MI.getLength()); |
0 |
6101 |
SDValue Length = getValue(MI.getLength()); |
0 |
| 6102 |
|
--- |
6102 |
|
--- |
| 6103 |
Type *LengthTy = MI.getLength()->getType(); |
0 |
6103 |
Type *LengthTy = MI.getLength()->getType(); |
0 |
| 6104 |
unsigned ElemSz = MI.getElementSizeInBytes(); |
0 |
6104 |
unsigned ElemSz = MI.getElementSizeInBytes(); |
0 |
| 6105 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6105 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6106 |
SDValue MC = |
--- |
6106 |
SDValue MC = |
--- |
| 6107 |
DAG.getAtomicMemcpy(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz, |
0 |
6107 |
DAG.getAtomicMemcpy(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz, |
0 |
| 6108 |
isTC, MachinePointerInfo(MI.getRawDest()), |
0 |
6108 |
isTC, MachinePointerInfo(MI.getRawDest()), |
0 |
| 6109 |
MachinePointerInfo(MI.getRawSource())); |
0 |
6109 |
MachinePointerInfo(MI.getRawSource())); |
0 |
| 6110 |
updateDAGForMaybeTailCall(MC); |
0 |
6110 |
updateDAGForMaybeTailCall(MC); |
0 |
| 6111 |
return; |
0 |
6111 |
return; |
0 |
| 6112 |
} |
--- |
6112 |
} |
--- |
| 6113 |
case Intrinsic::memmove_element_unordered_atomic: { |
0 |
6113 |
case Intrinsic::memmove_element_unordered_atomic: { |
0 |
| 6114 |
auto &MI = cast(I); |
0 |
6114 |
auto &MI = cast(I); |
0 |
| 6115 |
SDValue Dst = getValue(MI.getRawDest()); |
0 |
6115 |
SDValue Dst = getValue(MI.getRawDest()); |
0 |
| 6116 |
SDValue Src = getValue(MI.getRawSource()); |
0 |
6116 |
SDValue Src = getValue(MI.getRawSource()); |
0 |
| 6117 |
SDValue Length = getValue(MI.getLength()); |
0 |
6117 |
SDValue Length = getValue(MI.getLength()); |
0 |
| 6118 |
|
--- |
6118 |
|
--- |
| 6119 |
Type *LengthTy = MI.getLength()->getType(); |
0 |
6119 |
Type *LengthTy = MI.getLength()->getType(); |
0 |
| 6120 |
unsigned ElemSz = MI.getElementSizeInBytes(); |
0 |
6120 |
unsigned ElemSz = MI.getElementSizeInBytes(); |
0 |
| 6121 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6121 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6122 |
SDValue MC = |
--- |
6122 |
SDValue MC = |
--- |
| 6123 |
DAG.getAtomicMemmove(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz, |
0 |
6123 |
DAG.getAtomicMemmove(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz, |
0 |
| 6124 |
isTC, MachinePointerInfo(MI.getRawDest()), |
0 |
6124 |
isTC, MachinePointerInfo(MI.getRawDest()), |
0 |
| 6125 |
MachinePointerInfo(MI.getRawSource())); |
0 |
6125 |
MachinePointerInfo(MI.getRawSource())); |
0 |
| 6126 |
updateDAGForMaybeTailCall(MC); |
0 |
6126 |
updateDAGForMaybeTailCall(MC); |
0 |
| 6127 |
return; |
0 |
6127 |
return; |
0 |
| 6128 |
} |
--- |
6128 |
} |
--- |
| 6129 |
case Intrinsic::memset_element_unordered_atomic: { |
0 |
6129 |
case Intrinsic::memset_element_unordered_atomic: { |
0 |
| 6130 |
auto &MI = cast(I); |
0 |
6130 |
auto &MI = cast(I); |
0 |
| 6131 |
SDValue Dst = getValue(MI.getRawDest()); |
0 |
6131 |
SDValue Dst = getValue(MI.getRawDest()); |
0 |
| 6132 |
SDValue Val = getValue(MI.getValue()); |
0 |
6132 |
SDValue Val = getValue(MI.getValue()); |
0 |
| 6133 |
SDValue Length = getValue(MI.getLength()); |
0 |
6133 |
SDValue Length = getValue(MI.getLength()); |
0 |
| 6134 |
|
--- |
6134 |
|
--- |
| 6135 |
Type *LengthTy = MI.getLength()->getType(); |
0 |
6135 |
Type *LengthTy = MI.getLength()->getType(); |
0 |
| 6136 |
unsigned ElemSz = MI.getElementSizeInBytes(); |
0 |
6136 |
unsigned ElemSz = MI.getElementSizeInBytes(); |
0 |
| 6137 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
6137 |
bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); |
0 |
| 6138 |
SDValue MC = |
--- |
6138 |
SDValue MC = |
--- |
| 6139 |
DAG.getAtomicMemset(getRoot(), sdl, Dst, Val, Length, LengthTy, ElemSz, |
0 |
6139 |
DAG.getAtomicMemset(getRoot(), sdl, Dst, Val, Length, LengthTy, ElemSz, |
0 |
| 6140 |
isTC, MachinePointerInfo(MI.getRawDest())); |
0 |
6140 |
isTC, MachinePointerInfo(MI.getRawDest())); |
0 |
| 6141 |
updateDAGForMaybeTailCall(MC); |
0 |
6141 |
updateDAGForMaybeTailCall(MC); |
0 |
| 6142 |
return; |
0 |
6142 |
return; |
0 |
| 6143 |
} |
--- |
6143 |
} |
--- |
| 6144 |
case Intrinsic::call_preallocated_setup: { |
0 |
6144 |
case Intrinsic::call_preallocated_setup: { |
0 |
| 6145 |
const CallBase *PreallocatedCall = FindPreallocatedCall(&I); |
0 |
6145 |
const CallBase *PreallocatedCall = FindPreallocatedCall(&I); |
0 |
| 6146 |
SDValue SrcValue = DAG.getSrcValue(PreallocatedCall); |
0 |
6146 |
SDValue SrcValue = DAG.getSrcValue(PreallocatedCall); |
0 |
| 6147 |
SDValue Res = DAG.getNode(ISD::PREALLOCATED_SETUP, sdl, MVT::Other, |
0 |
6147 |
SDValue Res = DAG.getNode(ISD::PREALLOCATED_SETUP, sdl, MVT::Other, |
0 |
| 6148 |
getRoot(), SrcValue); |
--- |
6148 |
getRoot(), SrcValue); |
--- |
| 6149 |
setValue(&I, Res); |
0 |
6149 |
setValue(&I, Res); |
0 |
| 6150 |
DAG.setRoot(Res); |
0 |
6150 |
DAG.setRoot(Res); |
0 |
| 6151 |
return; |
0 |
6151 |
return; |
0 |
| 6152 |
} |
--- |
6152 |
} |
--- |
| 6153 |
case Intrinsic::call_preallocated_arg: { |
0 |
6153 |
case Intrinsic::call_preallocated_arg: { |
0 |
| 6154 |
const CallBase *PreallocatedCall = FindPreallocatedCall(I.getOperand(0)); |
0 |
6154 |
const CallBase *PreallocatedCall = FindPreallocatedCall(I.getOperand(0)); |
0 |
| 6155 |
SDValue SrcValue = DAG.getSrcValue(PreallocatedCall); |
0 |
6155 |
SDValue SrcValue = DAG.getSrcValue(PreallocatedCall); |
0 |
| 6156 |
SDValue Ops[3]; |
0 |
6156 |
SDValue Ops[3]; |
0 |
| 6157 |
Ops[0] = getRoot(); |
0 |
6157 |
Ops[0] = getRoot(); |
0 |
| 6158 |
Ops[1] = SrcValue; |
0 |
6158 |
Ops[1] = SrcValue; |
0 |
| 6159 |
Ops[2] = DAG.getTargetConstant(*cast(I.getArgOperand(1)), sdl, |
0 |
6159 |
Ops[2] = DAG.getTargetConstant(*cast(I.getArgOperand(1)), sdl, |
0 |
| 6160 |
MVT::i32); // arg index |
--- |
6160 |
MVT::i32); // arg index |
--- |
| 6161 |
SDValue Res = DAG.getNode( |
0 |
6161 |
SDValue Res = DAG.getNode( |
0 |
| 6162 |
ISD::PREALLOCATED_ARG, sdl, |
--- |
6162 |
ISD::PREALLOCATED_ARG, sdl, |
--- |
| 6163 |
DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Ops); |
0 |
6163 |
DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Ops); |
0 |
| 6164 |
setValue(&I, Res); |
0 |
6164 |
setValue(&I, Res); |
0 |
| 6165 |
DAG.setRoot(Res.getValue(1)); |
0 |
6165 |
DAG.setRoot(Res.getValue(1)); |
0 |
| 6166 |
return; |
0 |
6166 |
return; |
0 |
| 6167 |
} |
--- |
6167 |
} |
--- |
| 6168 |
case Intrinsic::dbg_declare: { |
3 |
6168 |
case Intrinsic::dbg_declare: { |
0 |
| 6169 |
const auto &DI = cast(I); |
3 |
6169 |
const auto &DI = cast(I); |
0 |
| 6170 |
// Debug intrinsics are handled separately in assignment tracking mode. |
--- |
6170 |
// Debug intrinsics are handled separately in assignment tracking mode. |
--- |
| 6171 |
// Some intrinsics are handled right after Argument lowering. |
--- |
6171 |
// Some intrinsics are handled right after Argument lowering. |
--- |
| 6172 |
if (AssignmentTrackingEnabled || |
6 |
6172 |
if (AssignmentTrackingEnabled || |
0 |
| 6173 |
FuncInfo.PreprocessedDbgDeclares.count(&DI)) |
3 |
6173 |
FuncInfo.PreprocessedDbgDeclares.count(&DI)) |
0 |
| 6174 |
return; |
3 |
6174 |
return; |
0 |
| 6175 |
// Assume dbg.declare can not currently use DIArgList, i.e. |
--- |
6175 |
// Assume dbg.declare can not currently use DIArgList, i.e. |
--- |
| 6176 |
// it is non-variadic. |
--- |
6176 |
// it is non-variadic. |
--- |
| 6177 |
assert(!DI.hasArgList() && "Only dbg.value should currently use DIArgList"); |
0 |
6177 |
assert(!DI.hasArgList() && "Only dbg.value should currently use DIArgList"); |
0 |
| 6178 |
DILocalVariable *Variable = DI.getVariable(); |
0 |
6178 |
DILocalVariable *Variable = DI.getVariable(); |
0 |
| 6179 |
DIExpression *Expression = DI.getExpression(); |
0 |
6179 |
DIExpression *Expression = DI.getExpression(); |
0 |
| 6180 |
dropDanglingDebugInfo(Variable, Expression); |
0 |
6180 |
dropDanglingDebugInfo(Variable, Expression); |
0 |
| 6181 |
assert(Variable && "Missing variable"); |
0 |
6181 |
assert(Variable && "Missing variable"); |
0 |
| 6182 |
LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DI |
0 |
6182 |
LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DI |
0 |
| 6183 |
<< "\n"); |
--- |
6183 |
<< "\n"); |
--- |
| 6184 |
// Check if address has undef value. |
--- |
6184 |
// Check if address has undef value. |
--- |
| 6185 |
const Value *Address = DI.getVariableLocationOp(0); |
0 |
6185 |
const Value *Address = DI.getVariableLocationOp(0); |
0 |
| 6186 |
if (!Address || isa(Address) || |
0 |
6186 |
if (!Address || isa(Address) || |
0 |
| 6187 |
(Address->use_empty() && !isa(Address))) { |
0 |
6187 |
(Address->use_empty() && !isa(Address))) { |
0 |
| 6188 |
LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI |
0 |
6188 |
LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI |
0 |
| 6189 |
<< " (bad/undef/unused-arg address)\n"); |
--- |
6189 |
<< " (bad/undef/unused-arg address)\n"); |
--- |
| 6190 |
return; |
0 |
6190 |
return; |
0 |
| 6191 |
} |
--- |
6191 |
} |
--- |
| 6192 |
|
--- |
6192 |
|
--- |
| 6193 |
bool isParameter = Variable->isParameter() || isa(Address); |
0 |
6193 |
bool isParameter = Variable->isParameter() || isa(Address); |
0 |
| 6194 |
|
--- |
6194 |
|
--- |
| 6195 |
SDValue &N = NodeMap[Address]; |
0 |
6195 |
SDValue &N = NodeMap[Address]; |
0 |
| 6196 |
if (!N.getNode() && isa(Address)) |
0 |
6196 |
if (!N.getNode() && isa(Address)) |
0 |
| 6197 |
// Check unused arguments map. |
--- |
6197 |
// Check unused arguments map. |
--- |
| 6198 |
N = UnusedArgNodeMap[Address]; |
0 |
6198 |
N = UnusedArgNodeMap[Address]; |
0 |
| 6199 |
SDDbgValue *SDV; |
--- |
6199 |
SDDbgValue *SDV; |
--- |
| 6200 |
if (N.getNode()) { |
0 |
6200 |
if (N.getNode()) { |
0 |
| 6201 |
if (const BitCastInst *BCI = dyn_cast(Address)) |
0 |
6201 |
if (const BitCastInst *BCI = dyn_cast(Address)) |
0 |
| 6202 |
Address = BCI->getOperand(0); |
0 |
6202 |
Address = BCI->getOperand(0); |
0 |
| 6203 |
// Parameters are handled specially. |
--- |
6203 |
// Parameters are handled specially. |
--- |
| 6204 |
auto FINode = dyn_cast(N.getNode()); |
0 |
6204 |
auto FINode = dyn_cast(N.getNode()); |
0 |
| 6205 |
if (isParameter && FINode) { |
0 |
6205 |
if (isParameter && FINode) { |
0 |
| 6206 |
// Byval parameter. We have a frame index at this point. |
--- |
6206 |
// Byval parameter. We have a frame index at this point. |
--- |
| 6207 |
SDV = |
0 |
6207 |
SDV = |
0 |
| 6208 |
DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(), |
0 |
6208 |
DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(), |
0 |
| 6209 |
/*IsIndirect*/ true, dl, SDNodeOrder); |
--- |
6209 |
/*IsIndirect*/ true, dl, SDNodeOrder); |
--- |
| 6210 |
} else if (isa(Address)) { |
0 |
6210 |
} else if (isa(Address)) { |
0 |
| 6211 |
// Address is an argument, so try to emit its dbg value using |
--- |
6211 |
// Address is an argument, so try to emit its dbg value using |
--- |
| 6212 |
// virtual register info from the FuncInfo.ValueMap. |
--- |
6212 |
// virtual register info from the FuncInfo.ValueMap. |
--- |
| 6213 |
EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, |
0 |
6213 |
EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, |
0 |
| 6214 |
FuncArgumentDbgValueKind::Declare, N); |
--- |
6214 |
FuncArgumentDbgValueKind::Declare, N); |
--- |
| 6215 |
return; |
0 |
6215 |
return; |
0 |
| 6216 |
} else { |
--- |
6216 |
} else { |
--- |
| 6217 |
SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), |
0 |
6217 |
SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), |
0 |
| 6218 |
true, dl, SDNodeOrder); |
--- |
6218 |
true, dl, SDNodeOrder); |
--- |
| 6219 |
} |
--- |
6219 |
} |
--- |
| 6220 |
DAG.AddDbgValue(SDV, isParameter); |
0 |
6220 |
DAG.AddDbgValue(SDV, isParameter); |
0 |
| 6221 |
} else { |
--- |
6221 |
} else { |
--- |
| 6222 |
// If Address is an argument then try to emit its dbg value using |
--- |
6222 |
// If Address is an argument then try to emit its dbg value using |
--- |
| 6223 |
// virtual register info from the FuncInfo.ValueMap. |
--- |
6223 |
// virtual register info from the FuncInfo.ValueMap. |
--- |
| 6224 |
if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, |
0 |
6224 |
if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, |
0 |
| 6225 |
FuncArgumentDbgValueKind::Declare, N)) { |
--- |
6225 |
FuncArgumentDbgValueKind::Declare, N)) { |
--- |
| 6226 |
LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI |
0 |
6226 |
LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI |
0 |
| 6227 |
<< " (could not emit func-arg dbg_value)\n"); |
--- |
6227 |
<< " (could not emit func-arg dbg_value)\n"); |
--- |
| 6228 |
} |
--- |
6228 |
} |
--- |
| 6229 |
} |
--- |
6229 |
} |
--- |
| 6230 |
return; |
0 |
6230 |
return; |
0 |
| 6231 |
} |
--- |
6231 |
} |
--- |
| 6232 |
case Intrinsic::dbg_label: { |
0 |
6232 |
case Intrinsic::dbg_label: { |
0 |
| 6233 |
const DbgLabelInst &DI = cast(I); |
0 |
6233 |
const DbgLabelInst &DI = cast(I); |
0 |
| 6234 |
DILabel *Label = DI.getLabel(); |
0 |
6234 |
DILabel *Label = DI.getLabel(); |
0 |
| 6235 |
assert(Label && "Missing label"); |
0 |
6235 |
assert(Label && "Missing label"); |
0 |
| 6236 |
|
--- |
6236 |
|
--- |
| 6237 |
SDDbgLabel *SDV; |
--- |
6237 |
SDDbgLabel *SDV; |
--- |
| 6238 |
SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder); |
0 |
6238 |
SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder); |
0 |
| 6239 |
DAG.AddDbgLabel(SDV); |
0 |
6239 |
DAG.AddDbgLabel(SDV); |
0 |
| 6240 |
return; |
0 |
6240 |
return; |
0 |
| 6241 |
} |
--- |
6241 |
} |
--- |
| 6242 |
case Intrinsic::dbg_assign: { |
0 |
6242 |
case Intrinsic::dbg_assign: { |
0 |
| 6243 |
// Debug intrinsics are handled seperately in assignment tracking mode. |
--- |
6243 |
// Debug intrinsics are handled seperately in assignment tracking mode. |
--- |
| 6244 |
if (AssignmentTrackingEnabled) |
0 |
6244 |
if (AssignmentTrackingEnabled) |
0 |
| 6245 |
return; |
0 |
6245 |
return; |
0 |
| 6246 |
// If assignment tracking hasn't been enabled then fall through and treat |
--- |
6246 |
// If assignment tracking hasn't been enabled then fall through and treat |
--- |
| 6247 |
// the dbg.assign as a dbg.value. |
--- |
6247 |
// the dbg.assign as a dbg.value. |
--- |
| 6248 |
[[fallthrough]]; |
--- |
6248 |
[[fallthrough]]; |
--- |
| 6249 |
} |
--- |
6249 |
} |
--- |
| 6250 |
case Intrinsic::dbg_value: { |
--- |
6250 |
case Intrinsic::dbg_value: { |
--- |
| 6251 |
// Debug intrinsics are handled seperately in assignment tracking mode. |
--- |
6251 |
// Debug intrinsics are handled seperately in assignment tracking mode. |
--- |
| 6252 |
if (AssignmentTrackingEnabled) |
0 |
6252 |
if (AssignmentTrackingEnabled) |
0 |
| 6253 |
return; |
0 |
6253 |
return; |
0 |
| 6254 |
const DbgValueInst &DI = cast(I); |
0 |
6254 |
const DbgValueInst &DI = cast(I); |
0 |
| 6255 |
assert(DI.getVariable() && "Missing variable"); |
0 |
6255 |
assert(DI.getVariable() && "Missing variable"); |
0 |
| 6256 |
|
--- |
6256 |
|
--- |
| 6257 |
DILocalVariable *Variable = DI.getVariable(); |
0 |
6257 |
DILocalVariable *Variable = DI.getVariable(); |
0 |
| 6258 |
DIExpression *Expression = DI.getExpression(); |
0 |
6258 |
DIExpression *Expression = DI.getExpression(); |
0 |
| 6259 |
dropDanglingDebugInfo(Variable, Expression); |
0 |
6259 |
dropDanglingDebugInfo(Variable, Expression); |
0 |
| 6260 |
|
--- |
6260 |
|
--- |
| 6261 |
if (DI.isKillLocation()) { |
0 |
6261 |
if (DI.isKillLocation()) { |
0 |
| 6262 |
handleKillDebugValue(Variable, Expression, DI.getDebugLoc(), SDNodeOrder); |
0 |
6262 |
handleKillDebugValue(Variable, Expression, DI.getDebugLoc(), SDNodeOrder); |
0 |
| 6263 |
return; |
0 |
6263 |
return; |
0 |
| 6264 |
} |
--- |
6264 |
} |
--- |
| 6265 |
|
--- |
6265 |
|
--- |
| 6266 |
SmallVector Values(DI.getValues()); |
0 |
6266 |
SmallVector Values(DI.getValues()); |
0 |
| 6267 |
if (Values.empty()) |
0 |
6267 |
if (Values.empty()) |
0 |
| 6268 |
return; |
0 |
6268 |
return; |
0 |
| 6269 |
|
--- |
6269 |
|
--- |
| 6270 |
bool IsVariadic = DI.hasArgList(); |
0 |
6270 |
bool IsVariadic = DI.hasArgList(); |
0 |
| 6271 |
if (!handleDebugValue(Values, Variable, Expression, DI.getDebugLoc(), |
0 |
6271 |
if (!handleDebugValue(Values, Variable, Expression, DI.getDebugLoc(), |
0 |
| 6272 |
SDNodeOrder, IsVariadic)) |
--- |
6272 |
SDNodeOrder, IsVariadic)) |
--- |
| 6273 |
addDanglingDebugInfo(&DI, SDNodeOrder); |
0 |
6273 |
addDanglingDebugInfo(&DI, SDNodeOrder); |
0 |
| 6274 |
return; |
0 |
6274 |
return; |
0 |
| 6275 |
} |
0 |
6275 |
} |
0 |
| 6276 |
|
--- |
6276 |
|
--- |
| 6277 |
case Intrinsic::eh_typeid_for: { |
0 |
6277 |
case Intrinsic::eh_typeid_for: { |
0 |
| 6278 |
// Find the type id for the given typeinfo. |
--- |
6278 |
// Find the type id for the given typeinfo. |
--- |
| 6279 |
GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0)); |
0 |
6279 |
GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0)); |
0 |
| 6280 |
unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV); |
0 |
6280 |
unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV); |
0 |
| 6281 |
Res = DAG.getConstant(TypeID, sdl, MVT::i32); |
0 |
6281 |
Res = DAG.getConstant(TypeID, sdl, MVT::i32); |
0 |
| 6282 |
setValue(&I, Res); |
0 |
6282 |
setValue(&I, Res); |
0 |
| 6283 |
return; |
0 |
6283 |
return; |
0 |
| 6284 |
} |
--- |
6284 |
} |
--- |
| 6285 |
|
--- |
6285 |
|
--- |
| 6286 |
case Intrinsic::eh_return_i32: |
0 |
6286 |
case Intrinsic::eh_return_i32: |
0 |
| 6287 |
case Intrinsic::eh_return_i64: |
--- |
6287 |
case Intrinsic::eh_return_i64: |
--- |
| 6288 |
DAG.getMachineFunction().setCallsEHReturn(true); |
0 |
6288 |
DAG.getMachineFunction().setCallsEHReturn(true); |
0 |
| 6289 |
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, |
0 |
6289 |
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, |
0 |
| 6290 |
MVT::Other, |
--- |
6290 |
MVT::Other, |
--- |
| 6291 |
getControlRoot(), |
--- |
6291 |
getControlRoot(), |
--- |
| 6292 |
getValue(I.getArgOperand(0)), |
0 |
6292 |
getValue(I.getArgOperand(0)), |
0 |
| 6293 |
getValue(I.getArgOperand(1)))); |
0 |
6293 |
getValue(I.getArgOperand(1)))); |
0 |
| 6294 |
return; |
0 |
6294 |
return; |
0 |
| 6295 |
case Intrinsic::eh_unwind_init: |
0 |
6295 |
case Intrinsic::eh_unwind_init: |
0 |
| 6296 |
DAG.getMachineFunction().setCallsUnwindInit(true); |
0 |
6296 |
DAG.getMachineFunction().setCallsUnwindInit(true); |
0 |
| 6297 |
return; |
0 |
6297 |
return; |
0 |
| 6298 |
case Intrinsic::eh_dwarf_cfa: |
0 |
6298 |
case Intrinsic::eh_dwarf_cfa: |
0 |
| 6299 |
setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl, |
0 |
6299 |
setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl, |
0 |
| 6300 |
TLI.getPointerTy(DAG.getDataLayout()), |
0 |
6300 |
TLI.getPointerTy(DAG.getDataLayout()), |
0 |
| 6301 |
getValue(I.getArgOperand(0)))); |
0 |
6301 |
getValue(I.getArgOperand(0)))); |
0 |
| 6302 |
return; |
0 |
6302 |
return; |
0 |
| 6303 |
case Intrinsic::eh_sjlj_callsite: { |
0 |
6303 |
case Intrinsic::eh_sjlj_callsite: { |
0 |
| 6304 |
MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); |
0 |
6304 |
MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); |
0 |
| 6305 |
ConstantInt *CI = cast(I.getArgOperand(0)); |
0 |
6305 |
ConstantInt *CI = cast(I.getArgOperand(0)); |
0 |
| 6306 |
assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); |
0 |
6306 |
assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); |
0 |
| 6307 |
|
--- |
6307 |
|
--- |
| 6308 |
MMI.setCurrentCallSite(CI->getZExtValue()); |
0 |
6308 |
MMI.setCurrentCallSite(CI->getZExtValue()); |
0 |
| 6309 |
return; |
0 |
6309 |
return; |
0 |
| 6310 |
} |
--- |
6310 |
} |
--- |
| 6311 |
case Intrinsic::eh_sjlj_functioncontext: { |
0 |
6311 |
case Intrinsic::eh_sjlj_functioncontext: { |
0 |
| 6312 |
// Get and store the index of the function context. |
--- |
6312 |
// Get and store the index of the function context. |
--- |
| 6313 |
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); |
0 |
6313 |
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); |
0 |
| 6314 |
AllocaInst *FnCtx = |
--- |
6314 |
AllocaInst *FnCtx = |
--- |
| 6315 |
cast(I.getArgOperand(0)->stripPointerCasts()); |
0 |
6315 |
cast(I.getArgOperand(0)->stripPointerCasts()); |
0 |
| 6316 |
int FI = FuncInfo.StaticAllocaMap[FnCtx]; |
0 |
6316 |
int FI = FuncInfo.StaticAllocaMap[FnCtx]; |
0 |
| 6317 |
MFI.setFunctionContextIndex(FI); |
0 |
6317 |
MFI.setFunctionContextIndex(FI); |
0 |
| 6318 |
return; |
0 |
6318 |
return; |
0 |
| 6319 |
} |
--- |
6319 |
} |
--- |
| 6320 |
case Intrinsic::eh_sjlj_setjmp: { |
0 |
6320 |
case Intrinsic::eh_sjlj_setjmp: { |
0 |
| 6321 |
SDValue Ops[2]; |
0 |
6321 |
SDValue Ops[2]; |
0 |
| 6322 |
Ops[0] = getRoot(); |
0 |
6322 |
Ops[0] = getRoot(); |
0 |
| 6323 |
Ops[1] = getValue(I.getArgOperand(0)); |
0 |
6323 |
Ops[1] = getValue(I.getArgOperand(0)); |
0 |
| 6324 |
SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, |
0 |
6324 |
SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, |
0 |
| 6325 |
DAG.getVTList(MVT::i32, MVT::Other), Ops); |
0 |
6325 |
DAG.getVTList(MVT::i32, MVT::Other), Ops); |
0 |
| 6326 |
setValue(&I, Op.getValue(0)); |
0 |
6326 |
setValue(&I, Op.getValue(0)); |
0 |
| 6327 |
DAG.setRoot(Op.getValue(1)); |
0 |
6327 |
DAG.setRoot(Op.getValue(1)); |
0 |
| 6328 |
return; |
0 |
6328 |
return; |
0 |
| 6329 |
} |
--- |
6329 |
} |
--- |
| 6330 |
case Intrinsic::eh_sjlj_longjmp: |
0 |
6330 |
case Intrinsic::eh_sjlj_longjmp: |
0 |
| 6331 |
DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, |
0 |
6331 |
DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, |
0 |
| 6332 |
getRoot(), getValue(I.getArgOperand(0)))); |
0 |
6332 |
getRoot(), getValue(I.getArgOperand(0)))); |
0 |
| 6333 |
return; |
0 |
6333 |
return; |
0 |
| 6334 |
case Intrinsic::eh_sjlj_setup_dispatch: |
0 |
6334 |
case Intrinsic::eh_sjlj_setup_dispatch: |
0 |
| 6335 |
DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other, |
0 |
6335 |
DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other, |
0 |
| 6336 |
getRoot())); |
--- |
6336 |
getRoot())); |
--- |
| 6337 |
return; |
0 |
6337 |
return; |
0 |
| 6338 |
case Intrinsic::masked_gather: |
0 |
6338 |
case Intrinsic::masked_gather: |
0 |
| 6339 |
visitMaskedGather(I); |
0 |
6339 |
visitMaskedGather(I); |
0 |
| 6340 |
return; |
0 |
6340 |
return; |
0 |
| 6341 |
case Intrinsic::masked_load: |
0 |
6341 |
case Intrinsic::masked_load: |
0 |
| 6342 |
visitMaskedLoad(I); |
0 |
6342 |
visitMaskedLoad(I); |
0 |
| 6343 |
return; |
0 |
6343 |
return; |
0 |
| 6344 |
case Intrinsic::masked_scatter: |
0 |
6344 |
case Intrinsic::masked_scatter: |
0 |
| 6345 |
visitMaskedScatter(I); |
0 |
6345 |
visitMaskedScatter(I); |
0 |
| 6346 |
return; |
0 |
6346 |
return; |
0 |
| 6347 |
case Intrinsic::masked_store: |
0 |
6347 |
case Intrinsic::masked_store: |
0 |
| 6348 |
visitMaskedStore(I); |
0 |
6348 |
visitMaskedStore(I); |
0 |
| 6349 |
return; |
0 |
6349 |
return; |
0 |
| 6350 |
case Intrinsic::masked_expandload: |
0 |
6350 |
case Intrinsic::masked_expandload: |
0 |
| 6351 |
visitMaskedLoad(I, true /* IsExpanding */); |
0 |
6351 |
visitMaskedLoad(I, true /* IsExpanding */); |
0 |
| 6352 |
return; |
0 |
6352 |
return; |
0 |
| 6353 |
case Intrinsic::masked_compressstore: |
0 |
6353 |
case Intrinsic::masked_compressstore: |
0 |
| 6354 |
visitMaskedStore(I, true /* IsCompressing */); |
0 |
6354 |
visitMaskedStore(I, true /* IsCompressing */); |
0 |
| 6355 |
return; |
0 |
6355 |
return; |
0 |
| 6356 |
case Intrinsic::powi: |
0 |
6356 |
case Intrinsic::powi: |
0 |
| 6357 |
setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), |
0 |
6357 |
setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), |
0 |
| 6358 |
getValue(I.getArgOperand(1)), DAG)); |
0 |
6358 |
getValue(I.getArgOperand(1)), DAG)); |
0 |
| 6359 |
return; |
0 |
6359 |
return; |
0 |
| 6360 |
case Intrinsic::log: |
0 |
6360 |
case Intrinsic::log: |
0 |
| 6361 |
setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
6361 |
setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
| 6362 |
return; |
0 |
6362 |
return; |
0 |
| 6363 |
case Intrinsic::log2: |
0 |
6363 |
case Intrinsic::log2: |
0 |
| 6364 |
setValue(&I, |
0 |
6364 |
setValue(&I, |
0 |
| 6365 |
expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
6365 |
expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
| 6366 |
return; |
0 |
6366 |
return; |
0 |
| 6367 |
case Intrinsic::log10: |
0 |
6367 |
case Intrinsic::log10: |
0 |
| 6368 |
setValue(&I, |
0 |
6368 |
setValue(&I, |
0 |
| 6369 |
expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
6369 |
expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
| 6370 |
return; |
0 |
6370 |
return; |
0 |
| 6371 |
case Intrinsic::exp: |
0 |
6371 |
case Intrinsic::exp: |
0 |
| 6372 |
setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
6372 |
setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
| 6373 |
return; |
0 |
6373 |
return; |
0 |
| 6374 |
case Intrinsic::exp2: |
0 |
6374 |
case Intrinsic::exp2: |
0 |
| 6375 |
setValue(&I, |
0 |
6375 |
setValue(&I, |
0 |
| 6376 |
expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
6376 |
expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); |
0 |
| 6377 |
return; |
0 |
6377 |
return; |
0 |
| 6378 |
case Intrinsic::pow: |
0 |
6378 |
case Intrinsic::pow: |
0 |
| 6379 |
setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), |
0 |
6379 |
setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), |
0 |
| 6380 |
getValue(I.getArgOperand(1)), DAG, TLI, Flags)); |
0 |
6380 |
getValue(I.getArgOperand(1)), DAG, TLI, Flags)); |
0 |
| 6381 |
return; |
0 |
6381 |
return; |
0 |
| 6382 |
case Intrinsic::sqrt: |
0 |
6382 |
case Intrinsic::sqrt: |
0 |
| 6383 |
case Intrinsic::fabs: |
--- |
6383 |
case Intrinsic::fabs: |
--- |
| 6384 |
case Intrinsic::sin: |
--- |
6384 |
case Intrinsic::sin: |
--- |
| 6385 |
case Intrinsic::cos: |
--- |
6385 |
case Intrinsic::cos: |
--- |
| 6386 |
case Intrinsic::floor: |
--- |
6386 |
case Intrinsic::floor: |
--- |
| 6387 |
case Intrinsic::ceil: |
--- |
6387 |
case Intrinsic::ceil: |
--- |
| 6388 |
case Intrinsic::trunc: |
--- |
6388 |
case Intrinsic::trunc: |
--- |
| 6389 |
case Intrinsic::rint: |
--- |
6389 |
case Intrinsic::rint: |
--- |
| 6390 |
case Intrinsic::nearbyint: |
--- |
6390 |
case Intrinsic::nearbyint: |
--- |
| 6391 |
case Intrinsic::round: |
--- |
6391 |
case Intrinsic::round: |
--- |
| 6392 |
case Intrinsic::roundeven: |
--- |
6392 |
case Intrinsic::roundeven: |
--- |
| 6393 |
case Intrinsic::canonicalize: { |
--- |
6393 |
case Intrinsic::canonicalize: { |
--- |
| 6394 |
unsigned Opcode; |
--- |
6394 |
unsigned Opcode; |
--- |
| 6395 |
switch (Intrinsic) { |
--- |
6395 |
switch (Intrinsic) { |
--- |
| 6396 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
6396 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
| 6397 |
case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; |
0 |
6397 |
case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; |
0 |
| 6398 |
case Intrinsic::fabs: Opcode = ISD::FABS; break; |
0 |
6398 |
case Intrinsic::fabs: Opcode = ISD::FABS; break; |
0 |
| 6399 |
case Intrinsic::sin: Opcode = ISD::FSIN; break; |
0 |
6399 |
case Intrinsic::sin: Opcode = ISD::FSIN; break; |
0 |
| 6400 |
case Intrinsic::cos: Opcode = ISD::FCOS; break; |
0 |
6400 |
case Intrinsic::cos: Opcode = ISD::FCOS; break; |
0 |
| 6401 |
case Intrinsic::floor: Opcode = ISD::FFLOOR; break; |
0 |
6401 |
case Intrinsic::floor: Opcode = ISD::FFLOOR; break; |
0 |
| 6402 |
case Intrinsic::ceil: Opcode = ISD::FCEIL; break; |
0 |
6402 |
case Intrinsic::ceil: Opcode = ISD::FCEIL; break; |
0 |
| 6403 |
case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; |
0 |
6403 |
case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; |
0 |
| 6404 |
case Intrinsic::rint: Opcode = ISD::FRINT; break; |
0 |
6404 |
case Intrinsic::rint: Opcode = ISD::FRINT; break; |
0 |
| 6405 |
case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; |
0 |
6405 |
case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; |
0 |
| 6406 |
case Intrinsic::round: Opcode = ISD::FROUND; break; |
0 |
6406 |
case Intrinsic::round: Opcode = ISD::FROUND; break; |
0 |
| 6407 |
case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break; |
0 |
6407 |
case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break; |
0 |
| 6408 |
case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break; |
0 |
6408 |
case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break; |
0 |
| 6409 |
} |
--- |
6409 |
} |
--- |
| 6410 |
|
--- |
6410 |
|
--- |
| 6411 |
setValue(&I, DAG.getNode(Opcode, sdl, |
0 |
6411 |
setValue(&I, DAG.getNode(Opcode, sdl, |
0 |
| 6412 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6412 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6413 |
getValue(I.getArgOperand(0)), Flags)); |
0 |
6413 |
getValue(I.getArgOperand(0)), Flags)); |
0 |
| 6414 |
return; |
0 |
6414 |
return; |
0 |
| 6415 |
} |
--- |
6415 |
} |
--- |
| 6416 |
case Intrinsic::lround: |
0 |
6416 |
case Intrinsic::lround: |
0 |
| 6417 |
case Intrinsic::llround: |
--- |
6417 |
case Intrinsic::llround: |
--- |
| 6418 |
case Intrinsic::lrint: |
--- |
6418 |
case Intrinsic::lrint: |
--- |
| 6419 |
case Intrinsic::llrint: { |
--- |
6419 |
case Intrinsic::llrint: { |
--- |
| 6420 |
unsigned Opcode; |
--- |
6420 |
unsigned Opcode; |
--- |
| 6421 |
switch (Intrinsic) { |
--- |
6421 |
switch (Intrinsic) { |
--- |
| 6422 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
6422 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
| 6423 |
case Intrinsic::lround: Opcode = ISD::LROUND; break; |
0 |
6423 |
case Intrinsic::lround: Opcode = ISD::LROUND; break; |
0 |
| 6424 |
case Intrinsic::llround: Opcode = ISD::LLROUND; break; |
0 |
6424 |
case Intrinsic::llround: Opcode = ISD::LLROUND; break; |
0 |
| 6425 |
case Intrinsic::lrint: Opcode = ISD::LRINT; break; |
0 |
6425 |
case Intrinsic::lrint: Opcode = ISD::LRINT; break; |
0 |
| 6426 |
case Intrinsic::llrint: Opcode = ISD::LLRINT; break; |
0 |
6426 |
case Intrinsic::llrint: Opcode = ISD::LLRINT; break; |
0 |
| 6427 |
} |
--- |
6427 |
} |
--- |
| 6428 |
|
--- |
6428 |
|
--- |
| 6429 |
EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6429 |
EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6430 |
setValue(&I, DAG.getNode(Opcode, sdl, RetVT, |
0 |
6430 |
setValue(&I, DAG.getNode(Opcode, sdl, RetVT, |
0 |
| 6431 |
getValue(I.getArgOperand(0)))); |
0 |
6431 |
getValue(I.getArgOperand(0)))); |
0 |
| 6432 |
return; |
0 |
6432 |
return; |
0 |
| 6433 |
} |
--- |
6433 |
} |
--- |
| 6434 |
case Intrinsic::minnum: |
0 |
6434 |
case Intrinsic::minnum: |
0 |
| 6435 |
setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, |
0 |
6435 |
setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, |
0 |
| 6436 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6436 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6437 |
getValue(I.getArgOperand(0)), |
0 |
6437 |
getValue(I.getArgOperand(0)), |
0 |
| 6438 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
6438 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
| 6439 |
return; |
0 |
6439 |
return; |
0 |
| 6440 |
case Intrinsic::maxnum: |
0 |
6440 |
case Intrinsic::maxnum: |
0 |
| 6441 |
setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, |
0 |
6441 |
setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, |
0 |
| 6442 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6442 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6443 |
getValue(I.getArgOperand(0)), |
0 |
6443 |
getValue(I.getArgOperand(0)), |
0 |
| 6444 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
6444 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
| 6445 |
return; |
0 |
6445 |
return; |
0 |
| 6446 |
case Intrinsic::minimum: |
0 |
6446 |
case Intrinsic::minimum: |
0 |
| 6447 |
setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl, |
0 |
6447 |
setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl, |
0 |
| 6448 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6448 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6449 |
getValue(I.getArgOperand(0)), |
0 |
6449 |
getValue(I.getArgOperand(0)), |
0 |
| 6450 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
6450 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
| 6451 |
return; |
0 |
6451 |
return; |
0 |
| 6452 |
case Intrinsic::maximum: |
0 |
6452 |
case Intrinsic::maximum: |
0 |
| 6453 |
setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl, |
0 |
6453 |
setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl, |
0 |
| 6454 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6454 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6455 |
getValue(I.getArgOperand(0)), |
0 |
6455 |
getValue(I.getArgOperand(0)), |
0 |
| 6456 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
6456 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
| 6457 |
return; |
0 |
6457 |
return; |
0 |
| 6458 |
case Intrinsic::copysign: |
0 |
6458 |
case Intrinsic::copysign: |
0 |
| 6459 |
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl, |
0 |
6459 |
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl, |
0 |
| 6460 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6460 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6461 |
getValue(I.getArgOperand(0)), |
0 |
6461 |
getValue(I.getArgOperand(0)), |
0 |
| 6462 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
6462 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
| 6463 |
return; |
0 |
6463 |
return; |
0 |
| 6464 |
case Intrinsic::ldexp: |
0 |
6464 |
case Intrinsic::ldexp: |
0 |
| 6465 |
setValue(&I, DAG.getNode(ISD::FLDEXP, sdl, |
0 |
6465 |
setValue(&I, DAG.getNode(ISD::FLDEXP, sdl, |
0 |
| 6466 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6466 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6467 |
getValue(I.getArgOperand(0)), |
0 |
6467 |
getValue(I.getArgOperand(0)), |
0 |
| 6468 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
6468 |
getValue(I.getArgOperand(1)), Flags)); |
0 |
| 6469 |
return; |
0 |
6469 |
return; |
0 |
| 6470 |
case Intrinsic::frexp: { |
0 |
6470 |
case Intrinsic::frexp: { |
0 |
| 6471 |
SmallVector ValueVTs; |
0 |
6471 |
SmallVector ValueVTs; |
0 |
| 6472 |
ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs); |
0 |
6472 |
ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs); |
0 |
| 6473 |
SDVTList VTs = DAG.getVTList(ValueVTs); |
0 |
6473 |
SDVTList VTs = DAG.getVTList(ValueVTs); |
0 |
| 6474 |
setValue(&I, |
0 |
6474 |
setValue(&I, |
0 |
| 6475 |
DAG.getNode(ISD::FFREXP, sdl, VTs, getValue(I.getArgOperand(0)))); |
0 |
6475 |
DAG.getNode(ISD::FFREXP, sdl, VTs, getValue(I.getArgOperand(0)))); |
0 |
| 6476 |
return; |
0 |
6476 |
return; |
0 |
| 6477 |
} |
0 |
6477 |
} |
0 |
| 6478 |
case Intrinsic::arithmetic_fence: { |
0 |
6478 |
case Intrinsic::arithmetic_fence: { |
0 |
| 6479 |
setValue(&I, DAG.getNode(ISD::ARITH_FENCE, sdl, |
0 |
6479 |
setValue(&I, DAG.getNode(ISD::ARITH_FENCE, sdl, |
0 |
| 6480 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6480 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6481 |
getValue(I.getArgOperand(0)), Flags)); |
0 |
6481 |
getValue(I.getArgOperand(0)), Flags)); |
0 |
| 6482 |
return; |
0 |
6482 |
return; |
0 |
| 6483 |
} |
--- |
6483 |
} |
--- |
| 6484 |
case Intrinsic::fma: |
0 |
6484 |
case Intrinsic::fma: |
0 |
| 6485 |
setValue(&I, DAG.getNode( |
0 |
6485 |
setValue(&I, DAG.getNode( |
0 |
| 6486 |
ISD::FMA, sdl, getValue(I.getArgOperand(0)).getValueType(), |
0 |
6486 |
ISD::FMA, sdl, getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6487 |
getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), |
0 |
6487 |
getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), |
0 |
| 6488 |
getValue(I.getArgOperand(2)), Flags)); |
0 |
6488 |
getValue(I.getArgOperand(2)), Flags)); |
0 |
| 6489 |
return; |
0 |
6489 |
return; |
0 |
| 6490 |
#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ |
--- |
6490 |
#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ |
--- |
| 6491 |
case Intrinsic::INTRINSIC: |
--- |
6491 |
case Intrinsic::INTRINSIC: |
--- |
| 6492 |
#include "llvm/IR/ConstrainedOps.def" |
--- |
6492 |
#include "llvm/IR/ConstrainedOps.def" |
--- |
| 6493 |
visitConstrainedFPIntrinsic(cast(I)); |
0 |
6493 |
visitConstrainedFPIntrinsic(cast(I)); |
0 |
| 6494 |
return; |
0 |
6494 |
return; |
0 |
| 6495 |
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: |
--- |
6495 |
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: |
--- |
| 6496 |
#include "llvm/IR/VPIntrinsics.def" |
--- |
6496 |
#include "llvm/IR/VPIntrinsics.def" |
--- |
| 6497 |
visitVectorPredicationIntrinsic(cast(I)); |
0 |
6497 |
visitVectorPredicationIntrinsic(cast(I)); |
0 |
| 6498 |
return; |
0 |
6498 |
return; |
0 |
| 6499 |
case Intrinsic::fptrunc_round: { |
0 |
6499 |
case Intrinsic::fptrunc_round: { |
0 |
| 6500 |
// Get the last argument, the metadata and convert it to an integer in the |
--- |
6500 |
// Get the last argument, the metadata and convert it to an integer in the |
--- |
| 6501 |
// call |
--- |
6501 |
// call |
--- |
| 6502 |
Metadata *MD = cast(I.getArgOperand(1))->getMetadata(); |
0 |
6502 |
Metadata *MD = cast(I.getArgOperand(1))->getMetadata(); |
0 |
| 6503 |
std::optional RoundMode = |
--- |
6503 |
std::optional RoundMode = |
--- |
| 6504 |
convertStrToRoundingMode(cast(MD)->getString()); |
0 |
6504 |
convertStrToRoundingMode(cast(MD)->getString()); |
0 |
| 6505 |
|
--- |
6505 |
|
--- |
| 6506 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6506 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6507 |
|
--- |
6507 |
|
--- |
| 6508 |
// Propagate fast-math-flags from IR to node(s). |
--- |
6508 |
// Propagate fast-math-flags from IR to node(s). |
--- |
| 6509 |
SDNodeFlags Flags; |
0 |
6509 |
SDNodeFlags Flags; |
0 |
| 6510 |
Flags.copyFMF(*cast(&I)); |
0 |
6510 |
Flags.copyFMF(*cast(&I)); |
0 |
| 6511 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
6511 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
| 6512 |
|
--- |
6512 |
|
--- |
| 6513 |
SDValue Result; |
0 |
6513 |
SDValue Result; |
0 |
| 6514 |
Result = DAG.getNode( |
0 |
6514 |
Result = DAG.getNode( |
0 |
| 6515 |
ISD::FPTRUNC_ROUND, sdl, VT, getValue(I.getArgOperand(0)), |
0 |
6515 |
ISD::FPTRUNC_ROUND, sdl, VT, getValue(I.getArgOperand(0)), |
0 |
| 6516 |
DAG.getTargetConstant((int)*RoundMode, sdl, |
0 |
6516 |
DAG.getTargetConstant((int)*RoundMode, sdl, |
0 |
| 6517 |
TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
6517 |
TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 6518 |
setValue(&I, Result); |
0 |
6518 |
setValue(&I, Result); |
0 |
| 6519 |
|
--- |
6519 |
|
--- |
| 6520 |
return; |
0 |
6520 |
return; |
0 |
| 6521 |
} |
0 |
6521 |
} |
0 |
| 6522 |
case Intrinsic::fmuladd: { |
0 |
6522 |
case Intrinsic::fmuladd: { |
0 |
| 6523 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6523 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6524 |
if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && |
0 |
6524 |
if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && |
0 |
| 6525 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) { |
0 |
6525 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) { |
0 |
| 6526 |
setValue(&I, DAG.getNode(ISD::FMA, sdl, |
0 |
6526 |
setValue(&I, DAG.getNode(ISD::FMA, sdl, |
0 |
| 6527 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6527 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6528 |
getValue(I.getArgOperand(0)), |
0 |
6528 |
getValue(I.getArgOperand(0)), |
0 |
| 6529 |
getValue(I.getArgOperand(1)), |
0 |
6529 |
getValue(I.getArgOperand(1)), |
0 |
| 6530 |
getValue(I.getArgOperand(2)), Flags)); |
0 |
6530 |
getValue(I.getArgOperand(2)), Flags)); |
0 |
| 6531 |
} else { |
--- |
6531 |
} else { |
--- |
| 6532 |
// TODO: Intrinsic calls should have fast-math-flags. |
--- |
6532 |
// TODO: Intrinsic calls should have fast-math-flags. |
--- |
| 6533 |
SDValue Mul = DAG.getNode( |
0 |
6533 |
SDValue Mul = DAG.getNode( |
0 |
| 6534 |
ISD::FMUL, sdl, getValue(I.getArgOperand(0)).getValueType(), |
0 |
6534 |
ISD::FMUL, sdl, getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6535 |
getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), Flags); |
0 |
6535 |
getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), Flags); |
0 |
| 6536 |
SDValue Add = DAG.getNode(ISD::FADD, sdl, |
0 |
6536 |
SDValue Add = DAG.getNode(ISD::FADD, sdl, |
0 |
| 6537 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6537 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6538 |
Mul, getValue(I.getArgOperand(2)), Flags); |
0 |
6538 |
Mul, getValue(I.getArgOperand(2)), Flags); |
0 |
| 6539 |
setValue(&I, Add); |
0 |
6539 |
setValue(&I, Add); |
0 |
| 6540 |
} |
--- |
6540 |
} |
--- |
| 6541 |
return; |
0 |
6541 |
return; |
0 |
| 6542 |
} |
--- |
6542 |
} |
--- |
| 6543 |
case Intrinsic::convert_to_fp16: |
0 |
6543 |
case Intrinsic::convert_to_fp16: |
0 |
| 6544 |
setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16, |
0 |
6544 |
setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16, |
0 |
| 6545 |
DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, |
0 |
6545 |
DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, |
0 |
| 6546 |
getValue(I.getArgOperand(0)), |
0 |
6546 |
getValue(I.getArgOperand(0)), |
0 |
| 6547 |
DAG.getTargetConstant(0, sdl, |
0 |
6547 |
DAG.getTargetConstant(0, sdl, |
0 |
| 6548 |
MVT::i32)))); |
--- |
6548 |
MVT::i32)))); |
--- |
| 6549 |
return; |
0 |
6549 |
return; |
0 |
| 6550 |
case Intrinsic::convert_from_fp16: |
0 |
6550 |
case Intrinsic::convert_from_fp16: |
0 |
| 6551 |
setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl, |
0 |
6551 |
setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl, |
0 |
| 6552 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
6552 |
TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
| 6553 |
DAG.getNode(ISD::BITCAST, sdl, MVT::f16, |
0 |
6553 |
DAG.getNode(ISD::BITCAST, sdl, MVT::f16, |
0 |
| 6554 |
getValue(I.getArgOperand(0))))); |
0 |
6554 |
getValue(I.getArgOperand(0))))); |
0 |
| 6555 |
return; |
0 |
6555 |
return; |
0 |
| 6556 |
case Intrinsic::fptosi_sat: { |
0 |
6556 |
case Intrinsic::fptosi_sat: { |
0 |
| 6557 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6557 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6558 |
setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, |
0 |
6558 |
setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, |
0 |
| 6559 |
getValue(I.getArgOperand(0)), |
0 |
6559 |
getValue(I.getArgOperand(0)), |
0 |
| 6560 |
DAG.getValueType(VT.getScalarType()))); |
0 |
6560 |
DAG.getValueType(VT.getScalarType()))); |
0 |
| 6561 |
return; |
0 |
6561 |
return; |
0 |
| 6562 |
} |
--- |
6562 |
} |
--- |
| 6563 |
case Intrinsic::fptoui_sat: { |
0 |
6563 |
case Intrinsic::fptoui_sat: { |
0 |
| 6564 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6564 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6565 |
setValue(&I, DAG.getNode(ISD::FP_TO_UINT_SAT, sdl, VT, |
0 |
6565 |
setValue(&I, DAG.getNode(ISD::FP_TO_UINT_SAT, sdl, VT, |
0 |
| 6566 |
getValue(I.getArgOperand(0)), |
0 |
6566 |
getValue(I.getArgOperand(0)), |
0 |
| 6567 |
DAG.getValueType(VT.getScalarType()))); |
0 |
6567 |
DAG.getValueType(VT.getScalarType()))); |
0 |
| 6568 |
return; |
0 |
6568 |
return; |
0 |
| 6569 |
} |
--- |
6569 |
} |
--- |
| 6570 |
case Intrinsic::set_rounding: |
0 |
6570 |
case Intrinsic::set_rounding: |
0 |
| 6571 |
Res = DAG.getNode(ISD::SET_ROUNDING, sdl, MVT::Other, |
0 |
6571 |
Res = DAG.getNode(ISD::SET_ROUNDING, sdl, MVT::Other, |
0 |
| 6572 |
{getRoot(), getValue(I.getArgOperand(0))}); |
0 |
6572 |
{getRoot(), getValue(I.getArgOperand(0))}); |
0 |
| 6573 |
setValue(&I, Res); |
0 |
6573 |
setValue(&I, Res); |
0 |
| 6574 |
DAG.setRoot(Res.getValue(0)); |
0 |
6574 |
DAG.setRoot(Res.getValue(0)); |
0 |
| 6575 |
return; |
0 |
6575 |
return; |
0 |
| 6576 |
case Intrinsic::is_fpclass: { |
0 |
6576 |
case Intrinsic::is_fpclass: { |
0 |
| 6577 |
const DataLayout DLayout = DAG.getDataLayout(); |
0 |
6577 |
const DataLayout DLayout = DAG.getDataLayout(); |
0 |
| 6578 |
EVT DestVT = TLI.getValueType(DLayout, I.getType()); |
0 |
6578 |
EVT DestVT = TLI.getValueType(DLayout, I.getType()); |
0 |
| 6579 |
EVT ArgVT = TLI.getValueType(DLayout, I.getArgOperand(0)->getType()); |
0 |
6579 |
EVT ArgVT = TLI.getValueType(DLayout, I.getArgOperand(0)->getType()); |
0 |
| 6580 |
FPClassTest Test = static_cast( |
--- |
6580 |
FPClassTest Test = static_cast( |
--- |
| 6581 |
cast(I.getArgOperand(1))->getZExtValue()); |
0 |
6581 |
cast(I.getArgOperand(1))->getZExtValue()); |
0 |
| 6582 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
6582 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 6583 |
const Function &F = MF.getFunction(); |
0 |
6583 |
const Function &F = MF.getFunction(); |
0 |
| 6584 |
SDValue Op = getValue(I.getArgOperand(0)); |
0 |
6584 |
SDValue Op = getValue(I.getArgOperand(0)); |
0 |
| 6585 |
SDNodeFlags Flags; |
0 |
6585 |
SDNodeFlags Flags; |
0 |
| 6586 |
Flags.setNoFPExcept( |
0 |
6586 |
Flags.setNoFPExcept( |
0 |
| 6587 |
!F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP)); |
0 |
6587 |
!F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP)); |
0 |
| 6588 |
// If ISD::IS_FPCLASS should be expanded, do it right now, because the |
--- |
6588 |
// If ISD::IS_FPCLASS should be expanded, do it right now, because the |
--- |
| 6589 |
// expansion can use illegal types. Making expansion early allows |
--- |
6589 |
// expansion can use illegal types. Making expansion early allows |
--- |
| 6590 |
// legalizing these types prior to selection. |
--- |
6590 |
// legalizing these types prior to selection. |
--- |
| 6591 |
if (!TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, ArgVT)) { |
0 |
6591 |
if (!TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, ArgVT)) { |
0 |
| 6592 |
SDValue Result = TLI.expandIS_FPCLASS(DestVT, Op, Test, Flags, sdl, DAG); |
0 |
6592 |
SDValue Result = TLI.expandIS_FPCLASS(DestVT, Op, Test, Flags, sdl, DAG); |
0 |
| 6593 |
setValue(&I, Result); |
0 |
6593 |
setValue(&I, Result); |
0 |
| 6594 |
return; |
0 |
6594 |
return; |
0 |
| 6595 |
} |
--- |
6595 |
} |
--- |
| 6596 |
|
--- |
6596 |
|
--- |
| 6597 |
SDValue Check = DAG.getTargetConstant(Test, sdl, MVT::i32); |
0 |
6597 |
SDValue Check = DAG.getTargetConstant(Test, sdl, MVT::i32); |
0 |
| 6598 |
SDValue V = DAG.getNode(ISD::IS_FPCLASS, sdl, DestVT, {Op, Check}, Flags); |
0 |
6598 |
SDValue V = DAG.getNode(ISD::IS_FPCLASS, sdl, DestVT, {Op, Check}, Flags); |
0 |
| 6599 |
setValue(&I, V); |
0 |
6599 |
setValue(&I, V); |
0 |
| 6600 |
return; |
0 |
6600 |
return; |
0 |
| 6601 |
} |
0 |
6601 |
} |
0 |
| 6602 |
case Intrinsic::get_fpenv: { |
0 |
6602 |
case Intrinsic::get_fpenv: { |
0 |
| 6603 |
const DataLayout DLayout = DAG.getDataLayout(); |
0 |
6603 |
const DataLayout DLayout = DAG.getDataLayout(); |
0 |
| 6604 |
EVT EnvVT = TLI.getValueType(DLayout, I.getType()); |
0 |
6604 |
EVT EnvVT = TLI.getValueType(DLayout, I.getType()); |
0 |
| 6605 |
Align TempAlign = DAG.getEVTAlign(EnvVT); |
0 |
6605 |
Align TempAlign = DAG.getEVTAlign(EnvVT); |
0 |
| 6606 |
SDValue Chain = getRoot(); |
0 |
6606 |
SDValue Chain = getRoot(); |
0 |
| 6607 |
// Use GET_FPENV if it is legal or custom. Otherwise use memory-based node |
--- |
6607 |
// Use GET_FPENV if it is legal or custom. Otherwise use memory-based node |
--- |
| 6608 |
// and temporary storage in stack. |
--- |
6608 |
// and temporary storage in stack. |
--- |
| 6609 |
if (TLI.isOperationLegalOrCustom(ISD::GET_FPENV, EnvVT)) { |
0 |
6609 |
if (TLI.isOperationLegalOrCustom(ISD::GET_FPENV, EnvVT)) { |
0 |
| 6610 |
Res = DAG.getNode( |
0 |
6610 |
Res = DAG.getNode( |
0 |
| 6611 |
ISD::GET_FPENV, sdl, |
--- |
6611 |
ISD::GET_FPENV, sdl, |
--- |
| 6612 |
DAG.getVTList(TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
6612 |
DAG.getVTList(TLI.getValueType(DAG.getDataLayout(), I.getType()), |
0 |
| 6613 |
MVT::Other), |
--- |
6613 |
MVT::Other), |
--- |
| 6614 |
Chain); |
--- |
6614 |
Chain); |
--- |
| 6615 |
} else { |
--- |
6615 |
} else { |
--- |
| 6616 |
SDValue Temp = DAG.CreateStackTemporary(EnvVT, TempAlign.value()); |
0 |
6616 |
SDValue Temp = DAG.CreateStackTemporary(EnvVT, TempAlign.value()); |
0 |
| 6617 |
int SPFI = cast(Temp.getNode())->getIndex(); |
0 |
6617 |
int SPFI = cast(Temp.getNode())->getIndex(); |
0 |
| 6618 |
auto MPI = |
--- |
6618 |
auto MPI = |
--- |
| 6619 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI); |
0 |
6619 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI); |
0 |
| 6620 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
6620 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 6621 |
MPI, MachineMemOperand::MOStore, MemoryLocation::UnknownSize, |
--- |
6621 |
MPI, MachineMemOperand::MOStore, MemoryLocation::UnknownSize, |
--- |
| 6622 |
TempAlign); |
--- |
6622 |
TempAlign); |
--- |
| 6623 |
Chain = DAG.getGetFPEnv(Chain, sdl, Temp, EnvVT, MMO); |
0 |
6623 |
Chain = DAG.getGetFPEnv(Chain, sdl, Temp, EnvVT, MMO); |
0 |
| 6624 |
Res = DAG.getLoad(EnvVT, sdl, Chain, Temp, MPI); |
0 |
6624 |
Res = DAG.getLoad(EnvVT, sdl, Chain, Temp, MPI); |
0 |
| 6625 |
} |
--- |
6625 |
} |
--- |
| 6626 |
setValue(&I, Res); |
0 |
6626 |
setValue(&I, Res); |
0 |
| 6627 |
DAG.setRoot(Res.getValue(1)); |
0 |
6627 |
DAG.setRoot(Res.getValue(1)); |
0 |
| 6628 |
return; |
0 |
6628 |
return; |
0 |
| 6629 |
} |
0 |
6629 |
} |
0 |
| 6630 |
case Intrinsic::set_fpenv: { |
0 |
6630 |
case Intrinsic::set_fpenv: { |
0 |
| 6631 |
const DataLayout DLayout = DAG.getDataLayout(); |
0 |
6631 |
const DataLayout DLayout = DAG.getDataLayout(); |
0 |
| 6632 |
SDValue Env = getValue(I.getArgOperand(0)); |
0 |
6632 |
SDValue Env = getValue(I.getArgOperand(0)); |
0 |
| 6633 |
EVT EnvVT = Env.getValueType(); |
0 |
6633 |
EVT EnvVT = Env.getValueType(); |
0 |
| 6634 |
Align TempAlign = DAG.getEVTAlign(EnvVT); |
0 |
6634 |
Align TempAlign = DAG.getEVTAlign(EnvVT); |
0 |
| 6635 |
SDValue Chain = getRoot(); |
0 |
6635 |
SDValue Chain = getRoot(); |
0 |
| 6636 |
// If SET_FPENV is custom or legal, use it. Otherwise use loading |
--- |
6636 |
// If SET_FPENV is custom or legal, use it. Otherwise use loading |
--- |
| 6637 |
// environment from memory. |
--- |
6637 |
// environment from memory. |
--- |
| 6638 |
if (TLI.isOperationLegalOrCustom(ISD::SET_FPENV, EnvVT)) { |
0 |
6638 |
if (TLI.isOperationLegalOrCustom(ISD::SET_FPENV, EnvVT)) { |
0 |
| 6639 |
Chain = DAG.getNode(ISD::SET_FPENV, sdl, MVT::Other, Chain, Env); |
0 |
6639 |
Chain = DAG.getNode(ISD::SET_FPENV, sdl, MVT::Other, Chain, Env); |
0 |
| 6640 |
} else { |
--- |
6640 |
} else { |
--- |
| 6641 |
// Allocate space in stack, copy environment bits into it and use this |
--- |
6641 |
// Allocate space in stack, copy environment bits into it and use this |
--- |
| 6642 |
// memory in SET_FPENV_MEM. |
--- |
6642 |
// memory in SET_FPENV_MEM. |
--- |
| 6643 |
SDValue Temp = DAG.CreateStackTemporary(EnvVT, TempAlign.value()); |
0 |
6643 |
SDValue Temp = DAG.CreateStackTemporary(EnvVT, TempAlign.value()); |
0 |
| 6644 |
int SPFI = cast(Temp.getNode())->getIndex(); |
0 |
6644 |
int SPFI = cast(Temp.getNode())->getIndex(); |
0 |
| 6645 |
auto MPI = |
--- |
6645 |
auto MPI = |
--- |
| 6646 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI); |
0 |
6646 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI); |
0 |
| 6647 |
Chain = DAG.getStore(Chain, sdl, Env, Temp, MPI, TempAlign, |
0 |
6647 |
Chain = DAG.getStore(Chain, sdl, Env, Temp, MPI, TempAlign, |
0 |
| 6648 |
MachineMemOperand::MOStore); |
--- |
6648 |
MachineMemOperand::MOStore); |
--- |
| 6649 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
6649 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 6650 |
MPI, MachineMemOperand::MOLoad, MemoryLocation::UnknownSize, |
--- |
6650 |
MPI, MachineMemOperand::MOLoad, MemoryLocation::UnknownSize, |
--- |
| 6651 |
TempAlign); |
--- |
6651 |
TempAlign); |
--- |
| 6652 |
Chain = DAG.getSetFPEnv(Chain, sdl, Temp, EnvVT, MMO); |
0 |
6652 |
Chain = DAG.getSetFPEnv(Chain, sdl, Temp, EnvVT, MMO); |
0 |
| 6653 |
} |
--- |
6653 |
} |
--- |
| 6654 |
DAG.setRoot(Chain); |
0 |
6654 |
DAG.setRoot(Chain); |
0 |
| 6655 |
return; |
0 |
6655 |
return; |
0 |
| 6656 |
} |
0 |
6656 |
} |
0 |
| 6657 |
case Intrinsic::reset_fpenv: |
0 |
6657 |
case Intrinsic::reset_fpenv: |
0 |
| 6658 |
DAG.setRoot(DAG.getNode(ISD::RESET_FPENV, sdl, MVT::Other, getRoot())); |
0 |
6658 |
DAG.setRoot(DAG.getNode(ISD::RESET_FPENV, sdl, MVT::Other, getRoot())); |
0 |
| 6659 |
return; |
0 |
6659 |
return; |
0 |
| 6660 |
case Intrinsic::pcmarker: { |
0 |
6660 |
case Intrinsic::pcmarker: { |
0 |
| 6661 |
SDValue Tmp = getValue(I.getArgOperand(0)); |
0 |
6661 |
SDValue Tmp = getValue(I.getArgOperand(0)); |
0 |
| 6662 |
DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); |
0 |
6662 |
DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); |
0 |
| 6663 |
return; |
0 |
6663 |
return; |
0 |
| 6664 |
} |
--- |
6664 |
} |
--- |
| 6665 |
case Intrinsic::readcyclecounter: { |
0 |
6665 |
case Intrinsic::readcyclecounter: { |
0 |
| 6666 |
SDValue Op = getRoot(); |
0 |
6666 |
SDValue Op = getRoot(); |
0 |
| 6667 |
Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, |
0 |
6667 |
Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, |
0 |
| 6668 |
DAG.getVTList(MVT::i64, MVT::Other), Op); |
0 |
6668 |
DAG.getVTList(MVT::i64, MVT::Other), Op); |
0 |
| 6669 |
setValue(&I, Res); |
0 |
6669 |
setValue(&I, Res); |
0 |
| 6670 |
DAG.setRoot(Res.getValue(1)); |
0 |
6670 |
DAG.setRoot(Res.getValue(1)); |
0 |
| 6671 |
return; |
0 |
6671 |
return; |
0 |
| 6672 |
} |
--- |
6672 |
} |
--- |
| 6673 |
case Intrinsic::bitreverse: |
0 |
6673 |
case Intrinsic::bitreverse: |
0 |
| 6674 |
setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl, |
0 |
6674 |
setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl, |
0 |
| 6675 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6675 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6676 |
getValue(I.getArgOperand(0)))); |
0 |
6676 |
getValue(I.getArgOperand(0)))); |
0 |
| 6677 |
return; |
0 |
6677 |
return; |
0 |
| 6678 |
case Intrinsic::bswap: |
0 |
6678 |
case Intrinsic::bswap: |
0 |
| 6679 |
setValue(&I, DAG.getNode(ISD::BSWAP, sdl, |
0 |
6679 |
setValue(&I, DAG.getNode(ISD::BSWAP, sdl, |
0 |
| 6680 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
6680 |
getValue(I.getArgOperand(0)).getValueType(), |
0 |
| 6681 |
getValue(I.getArgOperand(0)))); |
0 |
6681 |
getValue(I.getArgOperand(0)))); |
0 |
| 6682 |
return; |
0 |
6682 |
return; |
0 |
| 6683 |
case Intrinsic::cttz: { |
0 |
6683 |
case Intrinsic::cttz: { |
0 |
| 6684 |
SDValue Arg = getValue(I.getArgOperand(0)); |
0 |
6684 |
SDValue Arg = getValue(I.getArgOperand(0)); |
0 |
| 6685 |
ConstantInt *CI = cast(I.getArgOperand(1)); |
0 |
6685 |
ConstantInt *CI = cast(I.getArgOperand(1)); |
0 |
| 6686 |
EVT Ty = Arg.getValueType(); |
0 |
6686 |
EVT Ty = Arg.getValueType(); |
0 |
| 6687 |
setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, |
0 |
6687 |
setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, |
0 |
| 6688 |
sdl, Ty, Arg)); |
--- |
6688 |
sdl, Ty, Arg)); |
--- |
| 6689 |
return; |
0 |
6689 |
return; |
0 |
| 6690 |
} |
--- |
6690 |
} |
--- |
| 6691 |
case Intrinsic::ctlz: { |
0 |
6691 |
case Intrinsic::ctlz: { |
0 |
| 6692 |
SDValue Arg = getValue(I.getArgOperand(0)); |
0 |
6692 |
SDValue Arg = getValue(I.getArgOperand(0)); |
0 |
| 6693 |
ConstantInt *CI = cast(I.getArgOperand(1)); |
0 |
6693 |
ConstantInt *CI = cast(I.getArgOperand(1)); |
0 |
| 6694 |
EVT Ty = Arg.getValueType(); |
0 |
6694 |
EVT Ty = Arg.getValueType(); |
0 |
| 6695 |
setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, |
0 |
6695 |
setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, |
0 |
| 6696 |
sdl, Ty, Arg)); |
--- |
6696 |
sdl, Ty, Arg)); |
--- |
| 6697 |
return; |
0 |
6697 |
return; |
0 |
| 6698 |
} |
--- |
6698 |
} |
--- |
| 6699 |
case Intrinsic::ctpop: { |
0 |
6699 |
case Intrinsic::ctpop: { |
0 |
| 6700 |
SDValue Arg = getValue(I.getArgOperand(0)); |
0 |
6700 |
SDValue Arg = getValue(I.getArgOperand(0)); |
0 |
| 6701 |
EVT Ty = Arg.getValueType(); |
0 |
6701 |
EVT Ty = Arg.getValueType(); |
0 |
| 6702 |
setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); |
0 |
6702 |
setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); |
0 |
| 6703 |
return; |
0 |
6703 |
return; |
0 |
| 6704 |
} |
--- |
6704 |
} |
--- |
| 6705 |
case Intrinsic::fshl: |
0 |
6705 |
case Intrinsic::fshl: |
0 |
| 6706 |
case Intrinsic::fshr: { |
--- |
6706 |
case Intrinsic::fshr: { |
--- |
| 6707 |
bool IsFSHL = Intrinsic == Intrinsic::fshl; |
0 |
6707 |
bool IsFSHL = Intrinsic == Intrinsic::fshl; |
0 |
| 6708 |
SDValue X = getValue(I.getArgOperand(0)); |
0 |
6708 |
SDValue X = getValue(I.getArgOperand(0)); |
0 |
| 6709 |
SDValue Y = getValue(I.getArgOperand(1)); |
0 |
6709 |
SDValue Y = getValue(I.getArgOperand(1)); |
0 |
| 6710 |
SDValue Z = getValue(I.getArgOperand(2)); |
0 |
6710 |
SDValue Z = getValue(I.getArgOperand(2)); |
0 |
| 6711 |
EVT VT = X.getValueType(); |
0 |
6711 |
EVT VT = X.getValueType(); |
0 |
| 6712 |
|
--- |
6712 |
|
--- |
| 6713 |
if (X == Y) { |
0 |
6713 |
if (X == Y) { |
0 |
| 6714 |
auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR; |
0 |
6714 |
auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR; |
0 |
| 6715 |
setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z)); |
0 |
6715 |
setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z)); |
0 |
| 6716 |
} else { |
--- |
6716 |
} else { |
--- |
| 6717 |
auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; |
0 |
6717 |
auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; |
0 |
| 6718 |
setValue(&I, DAG.getNode(FunnelOpcode, sdl, VT, X, Y, Z)); |
0 |
6718 |
setValue(&I, DAG.getNode(FunnelOpcode, sdl, VT, X, Y, Z)); |
0 |
| 6719 |
} |
--- |
6719 |
} |
--- |
| 6720 |
return; |
0 |
6720 |
return; |
0 |
| 6721 |
} |
--- |
6721 |
} |
--- |
| 6722 |
case Intrinsic::sadd_sat: { |
0 |
6722 |
case Intrinsic::sadd_sat: { |
0 |
| 6723 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6723 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6724 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6724 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6725 |
setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6725 |
setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6726 |
return; |
0 |
6726 |
return; |
0 |
| 6727 |
} |
--- |
6727 |
} |
--- |
| 6728 |
case Intrinsic::uadd_sat: { |
0 |
6728 |
case Intrinsic::uadd_sat: { |
0 |
| 6729 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6729 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6730 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6730 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6731 |
setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6731 |
setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6732 |
return; |
0 |
6732 |
return; |
0 |
| 6733 |
} |
--- |
6733 |
} |
--- |
| 6734 |
case Intrinsic::ssub_sat: { |
0 |
6734 |
case Intrinsic::ssub_sat: { |
0 |
| 6735 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6735 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6736 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6736 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6737 |
setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6737 |
setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6738 |
return; |
0 |
6738 |
return; |
0 |
| 6739 |
} |
--- |
6739 |
} |
--- |
| 6740 |
case Intrinsic::usub_sat: { |
0 |
6740 |
case Intrinsic::usub_sat: { |
0 |
| 6741 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6741 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6742 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6742 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6743 |
setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6743 |
setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6744 |
return; |
0 |
6744 |
return; |
0 |
| 6745 |
} |
--- |
6745 |
} |
--- |
| 6746 |
case Intrinsic::sshl_sat: { |
0 |
6746 |
case Intrinsic::sshl_sat: { |
0 |
| 6747 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6747 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6748 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6748 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6749 |
setValue(&I, DAG.getNode(ISD::SSHLSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6749 |
setValue(&I, DAG.getNode(ISD::SSHLSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6750 |
return; |
0 |
6750 |
return; |
0 |
| 6751 |
} |
--- |
6751 |
} |
--- |
| 6752 |
case Intrinsic::ushl_sat: { |
0 |
6752 |
case Intrinsic::ushl_sat: { |
0 |
| 6753 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6753 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6754 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6754 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6755 |
setValue(&I, DAG.getNode(ISD::USHLSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6755 |
setValue(&I, DAG.getNode(ISD::USHLSAT, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6756 |
return; |
0 |
6756 |
return; |
0 |
| 6757 |
} |
--- |
6757 |
} |
--- |
| 6758 |
case Intrinsic::smul_fix: |
0 |
6758 |
case Intrinsic::smul_fix: |
0 |
| 6759 |
case Intrinsic::umul_fix: |
--- |
6759 |
case Intrinsic::umul_fix: |
--- |
| 6760 |
case Intrinsic::smul_fix_sat: |
--- |
6760 |
case Intrinsic::smul_fix_sat: |
--- |
| 6761 |
case Intrinsic::umul_fix_sat: { |
--- |
6761 |
case Intrinsic::umul_fix_sat: { |
--- |
| 6762 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6762 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6763 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6763 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6764 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
6764 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
| 6765 |
setValue(&I, DAG.getNode(FixedPointIntrinsicToOpcode(Intrinsic), sdl, |
0 |
6765 |
setValue(&I, DAG.getNode(FixedPointIntrinsicToOpcode(Intrinsic), sdl, |
0 |
| 6766 |
Op1.getValueType(), Op1, Op2, Op3)); |
--- |
6766 |
Op1.getValueType(), Op1, Op2, Op3)); |
--- |
| 6767 |
return; |
0 |
6767 |
return; |
0 |
| 6768 |
} |
--- |
6768 |
} |
--- |
| 6769 |
case Intrinsic::sdiv_fix: |
0 |
6769 |
case Intrinsic::sdiv_fix: |
0 |
| 6770 |
case Intrinsic::udiv_fix: |
--- |
6770 |
case Intrinsic::udiv_fix: |
--- |
| 6771 |
case Intrinsic::sdiv_fix_sat: |
--- |
6771 |
case Intrinsic::sdiv_fix_sat: |
--- |
| 6772 |
case Intrinsic::udiv_fix_sat: { |
--- |
6772 |
case Intrinsic::udiv_fix_sat: { |
--- |
| 6773 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6773 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6774 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6774 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6775 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
6775 |
SDValue Op3 = getValue(I.getArgOperand(2)); |
0 |
| 6776 |
setValue(&I, expandDivFix(FixedPointIntrinsicToOpcode(Intrinsic), sdl, |
0 |
6776 |
setValue(&I, expandDivFix(FixedPointIntrinsicToOpcode(Intrinsic), sdl, |
0 |
| 6777 |
Op1, Op2, Op3, DAG, TLI)); |
--- |
6777 |
Op1, Op2, Op3, DAG, TLI)); |
--- |
| 6778 |
return; |
0 |
6778 |
return; |
0 |
| 6779 |
} |
--- |
6779 |
} |
--- |
| 6780 |
case Intrinsic::smax: { |
0 |
6780 |
case Intrinsic::smax: { |
0 |
| 6781 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6781 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6782 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6782 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6783 |
setValue(&I, DAG.getNode(ISD::SMAX, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6783 |
setValue(&I, DAG.getNode(ISD::SMAX, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6784 |
return; |
0 |
6784 |
return; |
0 |
| 6785 |
} |
--- |
6785 |
} |
--- |
| 6786 |
case Intrinsic::smin: { |
0 |
6786 |
case Intrinsic::smin: { |
0 |
| 6787 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6787 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6788 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6788 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6789 |
setValue(&I, DAG.getNode(ISD::SMIN, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6789 |
setValue(&I, DAG.getNode(ISD::SMIN, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6790 |
return; |
0 |
6790 |
return; |
0 |
| 6791 |
} |
--- |
6791 |
} |
--- |
| 6792 |
case Intrinsic::umax: { |
0 |
6792 |
case Intrinsic::umax: { |
0 |
| 6793 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6793 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6794 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6794 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6795 |
setValue(&I, DAG.getNode(ISD::UMAX, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6795 |
setValue(&I, DAG.getNode(ISD::UMAX, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6796 |
return; |
0 |
6796 |
return; |
0 |
| 6797 |
} |
--- |
6797 |
} |
--- |
| 6798 |
case Intrinsic::umin: { |
0 |
6798 |
case Intrinsic::umin: { |
0 |
| 6799 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6799 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6800 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
6800 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 6801 |
setValue(&I, DAG.getNode(ISD::UMIN, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
6801 |
setValue(&I, DAG.getNode(ISD::UMIN, sdl, Op1.getValueType(), Op1, Op2)); |
0 |
| 6802 |
return; |
0 |
6802 |
return; |
0 |
| 6803 |
} |
--- |
6803 |
} |
--- |
| 6804 |
case Intrinsic::abs: { |
0 |
6804 |
case Intrinsic::abs: { |
0 |
| 6805 |
// TODO: Preserve "int min is poison" arg in SDAG? |
--- |
6805 |
// TODO: Preserve "int min is poison" arg in SDAG? |
--- |
| 6806 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
6806 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 6807 |
setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1)); |
0 |
6807 |
setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1)); |
0 |
| 6808 |
return; |
0 |
6808 |
return; |
0 |
| 6809 |
} |
--- |
6809 |
} |
--- |
| 6810 |
case Intrinsic::stacksave: { |
0 |
6810 |
case Intrinsic::stacksave: { |
0 |
| 6811 |
SDValue Op = getRoot(); |
0 |
6811 |
SDValue Op = getRoot(); |
0 |
| 6812 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6812 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6813 |
Res = DAG.getNode(ISD::STACKSAVE, sdl, DAG.getVTList(VT, MVT::Other), Op); |
0 |
6813 |
Res = DAG.getNode(ISD::STACKSAVE, sdl, DAG.getVTList(VT, MVT::Other), Op); |
0 |
| 6814 |
setValue(&I, Res); |
0 |
6814 |
setValue(&I, Res); |
0 |
| 6815 |
DAG.setRoot(Res.getValue(1)); |
0 |
6815 |
DAG.setRoot(Res.getValue(1)); |
0 |
| 6816 |
return; |
0 |
6816 |
return; |
0 |
| 6817 |
} |
--- |
6817 |
} |
--- |
| 6818 |
case Intrinsic::stackrestore: |
0 |
6818 |
case Intrinsic::stackrestore: |
0 |
| 6819 |
Res = getValue(I.getArgOperand(0)); |
0 |
6819 |
Res = getValue(I.getArgOperand(0)); |
0 |
| 6820 |
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); |
0 |
6820 |
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); |
0 |
| 6821 |
return; |
0 |
6821 |
return; |
0 |
| 6822 |
case Intrinsic::get_dynamic_area_offset: { |
0 |
6822 |
case Intrinsic::get_dynamic_area_offset: { |
0 |
| 6823 |
SDValue Op = getRoot(); |
0 |
6823 |
SDValue Op = getRoot(); |
0 |
| 6824 |
EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout()); |
0 |
6824 |
EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout()); |
0 |
| 6825 |
EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6825 |
EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6826 |
// Result type for @llvm.get.dynamic.area.offset should match PtrTy for |
--- |
6826 |
// Result type for @llvm.get.dynamic.area.offset should match PtrTy for |
--- |
| 6827 |
// target. |
--- |
6827 |
// target. |
--- |
| 6828 |
if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits()) |
0 |
6828 |
if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits()) |
0 |
| 6829 |
report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset" |
0 |
6829 |
report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset" |
0 |
| 6830 |
" intrinsic!"); |
--- |
6830 |
" intrinsic!"); |
--- |
| 6831 |
Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy), |
0 |
6831 |
Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy), |
0 |
| 6832 |
Op); |
--- |
6832 |
Op); |
--- |
| 6833 |
DAG.setRoot(Op); |
0 |
6833 |
DAG.setRoot(Op); |
0 |
| 6834 |
setValue(&I, Res); |
0 |
6834 |
setValue(&I, Res); |
0 |
| 6835 |
return; |
0 |
6835 |
return; |
0 |
| 6836 |
} |
--- |
6836 |
} |
--- |
| 6837 |
case Intrinsic::stackguard: { |
0 |
6837 |
case Intrinsic::stackguard: { |
0 |
| 6838 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
6838 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 6839 |
const Module &M = *MF.getFunction().getParent(); |
0 |
6839 |
const Module &M = *MF.getFunction().getParent(); |
0 |
| 6840 |
SDValue Chain = getRoot(); |
0 |
6840 |
SDValue Chain = getRoot(); |
0 |
| 6841 |
if (TLI.useLoadStackGuardNode()) { |
0 |
6841 |
if (TLI.useLoadStackGuardNode()) { |
0 |
| 6842 |
Res = getLoadStackGuard(DAG, sdl, Chain); |
0 |
6842 |
Res = getLoadStackGuard(DAG, sdl, Chain); |
0 |
| 6843 |
} else { |
--- |
6843 |
} else { |
--- |
| 6844 |
EVT PtrTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
6844 |
EVT PtrTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 6845 |
const Value *Global = TLI.getSDagStackGuard(M); |
0 |
6845 |
const Value *Global = TLI.getSDagStackGuard(M); |
0 |
| 6846 |
Align Align = DAG.getDataLayout().getPrefTypeAlign(Global->getType()); |
0 |
6846 |
Align Align = DAG.getDataLayout().getPrefTypeAlign(Global->getType()); |
0 |
| 6847 |
Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global), |
0 |
6847 |
Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global), |
0 |
| 6848 |
MachinePointerInfo(Global, 0), Align, |
--- |
6848 |
MachinePointerInfo(Global, 0), Align, |
--- |
| 6849 |
MachineMemOperand::MOVolatile); |
--- |
6849 |
MachineMemOperand::MOVolatile); |
--- |
| 6850 |
} |
--- |
6850 |
} |
--- |
| 6851 |
if (TLI.useStackGuardXorFP()) |
0 |
6851 |
if (TLI.useStackGuardXorFP()) |
0 |
| 6852 |
Res = TLI.emitStackGuardXorFP(DAG, Res, sdl); |
0 |
6852 |
Res = TLI.emitStackGuardXorFP(DAG, Res, sdl); |
0 |
| 6853 |
DAG.setRoot(Chain); |
0 |
6853 |
DAG.setRoot(Chain); |
0 |
| 6854 |
setValue(&I, Res); |
0 |
6854 |
setValue(&I, Res); |
0 |
| 6855 |
return; |
0 |
6855 |
return; |
0 |
| 6856 |
} |
--- |
6856 |
} |
--- |
| 6857 |
case Intrinsic::stackprotector: { |
0 |
6857 |
case Intrinsic::stackprotector: { |
0 |
| 6858 |
// Emit code into the DAG to store the stack guard onto the stack. |
--- |
6858 |
// Emit code into the DAG to store the stack guard onto the stack. |
--- |
| 6859 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
6859 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 6860 |
MachineFrameInfo &MFI = MF.getFrameInfo(); |
0 |
6860 |
MachineFrameInfo &MFI = MF.getFrameInfo(); |
0 |
| 6861 |
SDValue Src, Chain = getRoot(); |
0 |
6861 |
SDValue Src, Chain = getRoot(); |
0 |
| 6862 |
|
--- |
6862 |
|
--- |
| 6863 |
if (TLI.useLoadStackGuardNode()) |
0 |
6863 |
if (TLI.useLoadStackGuardNode()) |
0 |
| 6864 |
Src = getLoadStackGuard(DAG, sdl, Chain); |
0 |
6864 |
Src = getLoadStackGuard(DAG, sdl, Chain); |
0 |
| 6865 |
else |
--- |
6865 |
else |
--- |
| 6866 |
Src = getValue(I.getArgOperand(0)); // The guard's value. |
0 |
6866 |
Src = getValue(I.getArgOperand(0)); // The guard's value. |
0 |
| 6867 |
|
--- |
6867 |
|
--- |
| 6868 |
AllocaInst *Slot = cast(I.getArgOperand(1)); |
0 |
6868 |
AllocaInst *Slot = cast(I.getArgOperand(1)); |
0 |
| 6869 |
|
--- |
6869 |
|
--- |
| 6870 |
int FI = FuncInfo.StaticAllocaMap[Slot]; |
0 |
6870 |
int FI = FuncInfo.StaticAllocaMap[Slot]; |
0 |
| 6871 |
MFI.setStackProtectorIndex(FI); |
0 |
6871 |
MFI.setStackProtectorIndex(FI); |
0 |
| 6872 |
EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout()); |
0 |
6872 |
EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout()); |
0 |
| 6873 |
|
--- |
6873 |
|
--- |
| 6874 |
SDValue FIN = DAG.getFrameIndex(FI, PtrTy); |
0 |
6874 |
SDValue FIN = DAG.getFrameIndex(FI, PtrTy); |
0 |
| 6875 |
|
--- |
6875 |
|
--- |
| 6876 |
// Store the stack protector onto the stack. |
--- |
6876 |
// Store the stack protector onto the stack. |
--- |
| 6877 |
Res = DAG.getStore( |
0 |
6877 |
Res = DAG.getStore( |
0 |
| 6878 |
Chain, sdl, Src, FIN, |
--- |
6878 |
Chain, sdl, Src, FIN, |
--- |
| 6879 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), |
0 |
6879 |
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), |
0 |
| 6880 |
MaybeAlign(), MachineMemOperand::MOVolatile); |
--- |
6880 |
MaybeAlign(), MachineMemOperand::MOVolatile); |
--- |
| 6881 |
setValue(&I, Res); |
0 |
6881 |
setValue(&I, Res); |
0 |
| 6882 |
DAG.setRoot(Res); |
0 |
6882 |
DAG.setRoot(Res); |
0 |
| 6883 |
return; |
0 |
6883 |
return; |
0 |
| 6884 |
} |
--- |
6884 |
} |
--- |
| 6885 |
case Intrinsic::objectsize: |
0 |
6885 |
case Intrinsic::objectsize: |
0 |
| 6886 |
llvm_unreachable("llvm.objectsize.* should have been lowered already"); |
0 |
6886 |
llvm_unreachable("llvm.objectsize.* should have been lowered already"); |
0 |
| 6887 |
|
--- |
6887 |
|
--- |
| 6888 |
case Intrinsic::is_constant: |
0 |
6888 |
case Intrinsic::is_constant: |
0 |
| 6889 |
llvm_unreachable("llvm.is.constant.* should have been lowered already"); |
0 |
6889 |
llvm_unreachable("llvm.is.constant.* should have been lowered already"); |
0 |
| 6890 |
|
--- |
6890 |
|
--- |
| 6891 |
case Intrinsic::annotation: |
0 |
6891 |
case Intrinsic::annotation: |
0 |
| 6892 |
case Intrinsic::ptr_annotation: |
--- |
6892 |
case Intrinsic::ptr_annotation: |
--- |
| 6893 |
case Intrinsic::launder_invariant_group: |
--- |
6893 |
case Intrinsic::launder_invariant_group: |
--- |
| 6894 |
case Intrinsic::strip_invariant_group: |
--- |
6894 |
case Intrinsic::strip_invariant_group: |
--- |
| 6895 |
// Drop the intrinsic, but forward the value |
--- |
6895 |
// Drop the intrinsic, but forward the value |
--- |
| 6896 |
setValue(&I, getValue(I.getOperand(0))); |
0 |
6896 |
setValue(&I, getValue(I.getOperand(0))); |
0 |
| 6897 |
return; |
0 |
6897 |
return; |
0 |
| 6898 |
|
--- |
6898 |
|
--- |
| 6899 |
case Intrinsic::assume: |
0 |
6899 |
case Intrinsic::assume: |
0 |
| 6900 |
case Intrinsic::experimental_noalias_scope_decl: |
--- |
6900 |
case Intrinsic::experimental_noalias_scope_decl: |
--- |
| 6901 |
case Intrinsic::var_annotation: |
--- |
6901 |
case Intrinsic::var_annotation: |
--- |
| 6902 |
case Intrinsic::sideeffect: |
--- |
6902 |
case Intrinsic::sideeffect: |
--- |
| 6903 |
// Discard annotate attributes, noalias scope declarations, assumptions, and |
--- |
6903 |
// Discard annotate attributes, noalias scope declarations, assumptions, and |
--- |
| 6904 |
// artificial side-effects. |
--- |
6904 |
// artificial side-effects. |
--- |
| 6905 |
return; |
0 |
6905 |
return; |
0 |
| 6906 |
|
--- |
6906 |
|
--- |
| 6907 |
case Intrinsic::codeview_annotation: { |
0 |
6907 |
case Intrinsic::codeview_annotation: { |
0 |
| 6908 |
// Emit a label associated with this metadata. |
--- |
6908 |
// Emit a label associated with this metadata. |
--- |
| 6909 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
6909 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 6910 |
MCSymbol *Label = |
--- |
6910 |
MCSymbol *Label = |
--- |
| 6911 |
MF.getMMI().getContext().createTempSymbol("annotation", true); |
0 |
6911 |
MF.getMMI().getContext().createTempSymbol("annotation", true); |
0 |
| 6912 |
Metadata *MD = cast(I.getArgOperand(0))->getMetadata(); |
0 |
6912 |
Metadata *MD = cast(I.getArgOperand(0))->getMetadata(); |
0 |
| 6913 |
MF.addCodeViewAnnotation(Label, cast(MD)); |
0 |
6913 |
MF.addCodeViewAnnotation(Label, cast(MD)); |
0 |
| 6914 |
Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label); |
0 |
6914 |
Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label); |
0 |
| 6915 |
DAG.setRoot(Res); |
0 |
6915 |
DAG.setRoot(Res); |
0 |
| 6916 |
return; |
0 |
6916 |
return; |
0 |
| 6917 |
} |
--- |
6917 |
} |
--- |
| 6918 |
|
--- |
6918 |
|
--- |
| 6919 |
case Intrinsic::init_trampoline: { |
0 |
6919 |
case Intrinsic::init_trampoline: { |
0 |
| 6920 |
const Function *F = cast(I.getArgOperand(1)->stripPointerCasts()); |
0 |
6920 |
const Function *F = cast(I.getArgOperand(1)->stripPointerCasts()); |
0 |
| 6921 |
|
--- |
6921 |
|
--- |
| 6922 |
SDValue Ops[6]; |
0 |
6922 |
SDValue Ops[6]; |
0 |
| 6923 |
Ops[0] = getRoot(); |
0 |
6923 |
Ops[0] = getRoot(); |
0 |
| 6924 |
Ops[1] = getValue(I.getArgOperand(0)); |
0 |
6924 |
Ops[1] = getValue(I.getArgOperand(0)); |
0 |
| 6925 |
Ops[2] = getValue(I.getArgOperand(1)); |
0 |
6925 |
Ops[2] = getValue(I.getArgOperand(1)); |
0 |
| 6926 |
Ops[3] = getValue(I.getArgOperand(2)); |
0 |
6926 |
Ops[3] = getValue(I.getArgOperand(2)); |
0 |
| 6927 |
Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); |
0 |
6927 |
Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); |
0 |
| 6928 |
Ops[5] = DAG.getSrcValue(F); |
0 |
6928 |
Ops[5] = DAG.getSrcValue(F); |
0 |
| 6929 |
|
--- |
6929 |
|
--- |
| 6930 |
Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops); |
0 |
6930 |
Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops); |
0 |
| 6931 |
|
--- |
6931 |
|
--- |
| 6932 |
DAG.setRoot(Res); |
0 |
6932 |
DAG.setRoot(Res); |
0 |
| 6933 |
return; |
0 |
6933 |
return; |
0 |
| 6934 |
} |
--- |
6934 |
} |
--- |
| 6935 |
case Intrinsic::adjust_trampoline: |
0 |
6935 |
case Intrinsic::adjust_trampoline: |
0 |
| 6936 |
setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, |
0 |
6936 |
setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, |
0 |
| 6937 |
TLI.getPointerTy(DAG.getDataLayout()), |
0 |
6937 |
TLI.getPointerTy(DAG.getDataLayout()), |
0 |
| 6938 |
getValue(I.getArgOperand(0)))); |
0 |
6938 |
getValue(I.getArgOperand(0)))); |
0 |
| 6939 |
return; |
0 |
6939 |
return; |
0 |
| 6940 |
case Intrinsic::gcroot: { |
0 |
6940 |
case Intrinsic::gcroot: { |
0 |
| 6941 |
assert(DAG.getMachineFunction().getFunction().hasGC() && |
0 |
6941 |
assert(DAG.getMachineFunction().getFunction().hasGC() && |
0 |
| 6942 |
"only valid in functions with gc specified, enforced by Verifier"); |
--- |
6942 |
"only valid in functions with gc specified, enforced by Verifier"); |
--- |
| 6943 |
assert(GFI && "implied by previous"); |
0 |
6943 |
assert(GFI && "implied by previous"); |
0 |
| 6944 |
const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); |
0 |
6944 |
const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); |
0 |
| 6945 |
const Constant *TypeMap = cast(I.getArgOperand(1)); |
0 |
6945 |
const Constant *TypeMap = cast(I.getArgOperand(1)); |
0 |
| 6946 |
|
--- |
6946 |
|
--- |
| 6947 |
FrameIndexSDNode *FI = cast(getValue(Alloca).getNode()); |
0 |
6947 |
FrameIndexSDNode *FI = cast(getValue(Alloca).getNode()); |
0 |
| 6948 |
GFI->addStackRoot(FI->getIndex(), TypeMap); |
0 |
6948 |
GFI->addStackRoot(FI->getIndex(), TypeMap); |
0 |
| 6949 |
return; |
0 |
6949 |
return; |
0 |
| 6950 |
} |
--- |
6950 |
} |
--- |
| 6951 |
case Intrinsic::gcread: |
0 |
6951 |
case Intrinsic::gcread: |
0 |
| 6952 |
case Intrinsic::gcwrite: |
--- |
6952 |
case Intrinsic::gcwrite: |
--- |
| 6953 |
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); |
0 |
6953 |
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); |
0 |
| 6954 |
case Intrinsic::get_rounding: |
0 |
6954 |
case Intrinsic::get_rounding: |
0 |
| 6955 |
Res = DAG.getNode(ISD::GET_ROUNDING, sdl, {MVT::i32, MVT::Other}, getRoot()); |
0 |
6955 |
Res = DAG.getNode(ISD::GET_ROUNDING, sdl, {MVT::i32, MVT::Other}, getRoot()); |
0 |
| 6956 |
setValue(&I, Res); |
0 |
6956 |
setValue(&I, Res); |
0 |
| 6957 |
DAG.setRoot(Res.getValue(1)); |
0 |
6957 |
DAG.setRoot(Res.getValue(1)); |
0 |
| 6958 |
return; |
0 |
6958 |
return; |
0 |
| 6959 |
|
--- |
6959 |
|
--- |
| 6960 |
case Intrinsic::expect: |
0 |
6960 |
case Intrinsic::expect: |
0 |
| 6961 |
// Just replace __builtin_expect(exp, c) with EXP. |
--- |
6961 |
// Just replace __builtin_expect(exp, c) with EXP. |
--- |
| 6962 |
setValue(&I, getValue(I.getArgOperand(0))); |
0 |
6962 |
setValue(&I, getValue(I.getArgOperand(0))); |
0 |
| 6963 |
return; |
0 |
6963 |
return; |
0 |
| 6964 |
|
--- |
6964 |
|
--- |
| 6965 |
case Intrinsic::ubsantrap: |
0 |
6965 |
case Intrinsic::ubsantrap: |
0 |
| 6966 |
case Intrinsic::debugtrap: |
--- |
6966 |
case Intrinsic::debugtrap: |
--- |
| 6967 |
case Intrinsic::trap: { |
--- |
6967 |
case Intrinsic::trap: { |
--- |
| 6968 |
StringRef TrapFuncName = |
--- |
6968 |
StringRef TrapFuncName = |
--- |
| 6969 |
I.getAttributes().getFnAttr("trap-func-name").getValueAsString(); |
0 |
6969 |
I.getAttributes().getFnAttr("trap-func-name").getValueAsString(); |
0 |
| 6970 |
if (TrapFuncName.empty()) { |
0 |
6970 |
if (TrapFuncName.empty()) { |
0 |
| 6971 |
switch (Intrinsic) { |
--- |
6971 |
switch (Intrinsic) { |
--- |
| 6972 |
case Intrinsic::trap: |
0 |
6972 |
case Intrinsic::trap: |
0 |
| 6973 |
DAG.setRoot(DAG.getNode(ISD::TRAP, sdl, MVT::Other, getRoot())); |
0 |
6973 |
DAG.setRoot(DAG.getNode(ISD::TRAP, sdl, MVT::Other, getRoot())); |
0 |
| 6974 |
break; |
0 |
6974 |
break; |
0 |
| 6975 |
case Intrinsic::debugtrap: |
0 |
6975 |
case Intrinsic::debugtrap: |
0 |
| 6976 |
DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, sdl, MVT::Other, getRoot())); |
0 |
6976 |
DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, sdl, MVT::Other, getRoot())); |
0 |
| 6977 |
break; |
0 |
6977 |
break; |
0 |
| 6978 |
case Intrinsic::ubsantrap: |
0 |
6978 |
case Intrinsic::ubsantrap: |
0 |
| 6979 |
DAG.setRoot(DAG.getNode( |
0 |
6979 |
DAG.setRoot(DAG.getNode( |
0 |
| 6980 |
ISD::UBSANTRAP, sdl, MVT::Other, getRoot(), |
--- |
6980 |
ISD::UBSANTRAP, sdl, MVT::Other, getRoot(), |
--- |
| 6981 |
DAG.getTargetConstant( |
0 |
6981 |
DAG.getTargetConstant( |
0 |
| 6982 |
cast(I.getArgOperand(0))->getZExtValue(), sdl, |
--- |
6982 |
cast(I.getArgOperand(0))->getZExtValue(), sdl, |
--- |
| 6983 |
MVT::i32))); |
--- |
6983 |
MVT::i32))); |
--- |
| 6984 |
break; |
0 |
6984 |
break; |
0 |
| 6985 |
default: llvm_unreachable("unknown trap intrinsic"); |
0 |
6985 |
default: llvm_unreachable("unknown trap intrinsic"); |
0 |
| 6986 |
} |
--- |
6986 |
} |
--- |
| 6987 |
return; |
0 |
6987 |
return; |
0 |
| 6988 |
} |
--- |
6988 |
} |
--- |
| 6989 |
TargetLowering::ArgListTy Args; |
0 |
6989 |
TargetLowering::ArgListTy Args; |
0 |
| 6990 |
if (Intrinsic == Intrinsic::ubsantrap) { |
0 |
6990 |
if (Intrinsic == Intrinsic::ubsantrap) { |
0 |
| 6991 |
Args.push_back(TargetLoweringBase::ArgListEntry()); |
0 |
6991 |
Args.push_back(TargetLoweringBase::ArgListEntry()); |
0 |
| 6992 |
Args[0].Val = I.getArgOperand(0); |
0 |
6992 |
Args[0].Val = I.getArgOperand(0); |
0 |
| 6993 |
Args[0].Node = getValue(Args[0].Val); |
0 |
6993 |
Args[0].Node = getValue(Args[0].Val); |
0 |
| 6994 |
Args[0].Ty = Args[0].Val->getType(); |
0 |
6994 |
Args[0].Ty = Args[0].Val->getType(); |
0 |
| 6995 |
} |
--- |
6995 |
} |
--- |
| 6996 |
|
--- |
6996 |
|
--- |
| 6997 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
6997 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
| 6998 |
CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee( |
0 |
6998 |
CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee( |
0 |
| 6999 |
CallingConv::C, I.getType(), |
--- |
6999 |
CallingConv::C, I.getType(), |
--- |
| 7000 |
DAG.getExternalSymbol(TrapFuncName.data(), |
0 |
7000 |
DAG.getExternalSymbol(TrapFuncName.data(), |
0 |
| 7001 |
TLI.getPointerTy(DAG.getDataLayout())), |
0 |
7001 |
TLI.getPointerTy(DAG.getDataLayout())), |
0 |
| 7002 |
std::move(Args)); |
0 |
7002 |
std::move(Args)); |
0 |
| 7003 |
|
--- |
7003 |
|
--- |
| 7004 |
std::pair Result = TLI.LowerCallTo(CLI); |
0 |
7004 |
std::pair Result = TLI.LowerCallTo(CLI); |
0 |
| 7005 |
DAG.setRoot(Result.second); |
0 |
7005 |
DAG.setRoot(Result.second); |
0 |
| 7006 |
return; |
0 |
7006 |
return; |
0 |
| 7007 |
} |
--- |
7007 |
} |
--- |
| 7008 |
|
--- |
7008 |
|
--- |
| 7009 |
case Intrinsic::uadd_with_overflow: |
0 |
7009 |
case Intrinsic::uadd_with_overflow: |
0 |
| 7010 |
case Intrinsic::sadd_with_overflow: |
--- |
7010 |
case Intrinsic::sadd_with_overflow: |
--- |
| 7011 |
case Intrinsic::usub_with_overflow: |
--- |
7011 |
case Intrinsic::usub_with_overflow: |
--- |
| 7012 |
case Intrinsic::ssub_with_overflow: |
--- |
7012 |
case Intrinsic::ssub_with_overflow: |
--- |
| 7013 |
case Intrinsic::umul_with_overflow: |
--- |
7013 |
case Intrinsic::umul_with_overflow: |
--- |
| 7014 |
case Intrinsic::smul_with_overflow: { |
--- |
7014 |
case Intrinsic::smul_with_overflow: { |
--- |
| 7015 |
ISD::NodeType Op; |
--- |
7015 |
ISD::NodeType Op; |
--- |
| 7016 |
switch (Intrinsic) { |
--- |
7016 |
switch (Intrinsic) { |
--- |
| 7017 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
7017 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
| 7018 |
case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; |
0 |
7018 |
case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; |
0 |
| 7019 |
case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; |
0 |
7019 |
case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; |
0 |
| 7020 |
case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; |
0 |
7020 |
case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; |
0 |
| 7021 |
case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; |
0 |
7021 |
case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; |
0 |
| 7022 |
case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; |
0 |
7022 |
case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; |
0 |
| 7023 |
case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; |
0 |
7023 |
case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; |
0 |
| 7024 |
} |
--- |
7024 |
} |
--- |
| 7025 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
7025 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 7026 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
7026 |
SDValue Op2 = getValue(I.getArgOperand(1)); |
0 |
| 7027 |
|
--- |
7027 |
|
--- |
| 7028 |
EVT ResultVT = Op1.getValueType(); |
0 |
7028 |
EVT ResultVT = Op1.getValueType(); |
0 |
| 7029 |
EVT OverflowVT = MVT::i1; |
0 |
7029 |
EVT OverflowVT = MVT::i1; |
0 |
| 7030 |
if (ResultVT.isVector()) |
0 |
7030 |
if (ResultVT.isVector()) |
0 |
| 7031 |
OverflowVT = EVT::getVectorVT( |
0 |
7031 |
OverflowVT = EVT::getVectorVT( |
0 |
| 7032 |
*Context, OverflowVT, ResultVT.getVectorElementCount()); |
0 |
7032 |
*Context, OverflowVT, ResultVT.getVectorElementCount()); |
0 |
| 7033 |
|
--- |
7033 |
|
--- |
| 7034 |
SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT); |
0 |
7034 |
SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT); |
0 |
| 7035 |
setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); |
0 |
7035 |
setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); |
0 |
| 7036 |
return; |
0 |
7036 |
return; |
0 |
| 7037 |
} |
--- |
7037 |
} |
--- |
| 7038 |
case Intrinsic::prefetch: { |
0 |
7038 |
case Intrinsic::prefetch: { |
0 |
| 7039 |
SDValue Ops[5]; |
0 |
7039 |
SDValue Ops[5]; |
0 |
| 7040 |
unsigned rw = cast(I.getArgOperand(1))->getZExtValue(); |
0 |
7040 |
unsigned rw = cast(I.getArgOperand(1))->getZExtValue(); |
0 |
| 7041 |
auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore; |
0 |
7041 |
auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore; |
0 |
| 7042 |
Ops[0] = DAG.getRoot(); |
0 |
7042 |
Ops[0] = DAG.getRoot(); |
0 |
| 7043 |
Ops[1] = getValue(I.getArgOperand(0)); |
0 |
7043 |
Ops[1] = getValue(I.getArgOperand(0)); |
0 |
| 7044 |
Ops[2] = getValue(I.getArgOperand(1)); |
0 |
7044 |
Ops[2] = getValue(I.getArgOperand(1)); |
0 |
| 7045 |
Ops[3] = getValue(I.getArgOperand(2)); |
0 |
7045 |
Ops[3] = getValue(I.getArgOperand(2)); |
0 |
| 7046 |
Ops[4] = getValue(I.getArgOperand(3)); |
0 |
7046 |
Ops[4] = getValue(I.getArgOperand(3)); |
0 |
| 7047 |
SDValue Result = DAG.getMemIntrinsicNode( |
0 |
7047 |
SDValue Result = DAG.getMemIntrinsicNode( |
0 |
| 7048 |
ISD::PREFETCH, sdl, DAG.getVTList(MVT::Other), Ops, |
0 |
7048 |
ISD::PREFETCH, sdl, DAG.getVTList(MVT::Other), Ops, |
0 |
| 7049 |
EVT::getIntegerVT(*Context, 8), MachinePointerInfo(I.getArgOperand(0)), |
0 |
7049 |
EVT::getIntegerVT(*Context, 8), MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 7050 |
/* align */ std::nullopt, Flags); |
--- |
7050 |
/* align */ std::nullopt, Flags); |
--- |
| 7051 |
|
--- |
7051 |
|
--- |
| 7052 |
// Chain the prefetch in parallell with any pending loads, to stay out of |
--- |
7052 |
// Chain the prefetch in parallell with any pending loads, to stay out of |
--- |
| 7053 |
// the way of later optimizations. |
--- |
7053 |
// the way of later optimizations. |
--- |
| 7054 |
PendingLoads.push_back(Result); |
0 |
7054 |
PendingLoads.push_back(Result); |
0 |
| 7055 |
Result = getRoot(); |
0 |
7055 |
Result = getRoot(); |
0 |
| 7056 |
DAG.setRoot(Result); |
0 |
7056 |
DAG.setRoot(Result); |
0 |
| 7057 |
return; |
0 |
7057 |
return; |
0 |
| 7058 |
} |
--- |
7058 |
} |
--- |
| 7059 |
case Intrinsic::lifetime_start: |
0 |
7059 |
case Intrinsic::lifetime_start: |
0 |
| 7060 |
case Intrinsic::lifetime_end: { |
--- |
7060 |
case Intrinsic::lifetime_end: { |
--- |
| 7061 |
bool IsStart = (Intrinsic == Intrinsic::lifetime_start); |
0 |
7061 |
bool IsStart = (Intrinsic == Intrinsic::lifetime_start); |
0 |
| 7062 |
// Stack coloring is not enabled in O0, discard region information. |
--- |
7062 |
// Stack coloring is not enabled in O0, discard region information. |
--- |
| 7063 |
if (TM.getOptLevel() == CodeGenOpt::None) |
0 |
7063 |
if (TM.getOptLevel() == CodeGenOpt::None) |
0 |
| 7064 |
return; |
0 |
7064 |
return; |
0 |
| 7065 |
|
--- |
7065 |
|
--- |
| 7066 |
const int64_t ObjectSize = |
--- |
7066 |
const int64_t ObjectSize = |
--- |
| 7067 |
cast(I.getArgOperand(0))->getSExtValue(); |
0 |
7067 |
cast(I.getArgOperand(0))->getSExtValue(); |
0 |
| 7068 |
Value *const ObjectPtr = I.getArgOperand(1); |
0 |
7068 |
Value *const ObjectPtr = I.getArgOperand(1); |
0 |
| 7069 |
SmallVector Allocas; |
0 |
7069 |
SmallVector Allocas; |
0 |
| 7070 |
getUnderlyingObjects(ObjectPtr, Allocas); |
0 |
7070 |
getUnderlyingObjects(ObjectPtr, Allocas); |
0 |
| 7071 |
|
--- |
7071 |
|
--- |
| 7072 |
for (const Value *Alloca : Allocas) { |
0 |
7072 |
for (const Value *Alloca : Allocas) { |
0 |
| 7073 |
const AllocaInst *LifetimeObject = dyn_cast_or_null(Alloca); |
0 |
7073 |
const AllocaInst *LifetimeObject = dyn_cast_or_null(Alloca); |
0 |
| 7074 |
|
--- |
7074 |
|
--- |
| 7075 |
// Could not find an Alloca. |
--- |
7075 |
// Could not find an Alloca. |
--- |
| 7076 |
if (!LifetimeObject) |
0 |
7076 |
if (!LifetimeObject) |
0 |
| 7077 |
continue; |
0 |
7077 |
continue; |
0 |
| 7078 |
|
--- |
7078 |
|
--- |
| 7079 |
// First check that the Alloca is static, otherwise it won't have a |
--- |
7079 |
// First check that the Alloca is static, otherwise it won't have a |
--- |
| 7080 |
// valid frame index. |
--- |
7080 |
// valid frame index. |
--- |
| 7081 |
auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject); |
0 |
7081 |
auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject); |
0 |
| 7082 |
if (SI == FuncInfo.StaticAllocaMap.end()) |
0 |
7082 |
if (SI == FuncInfo.StaticAllocaMap.end()) |
0 |
| 7083 |
return; |
0 |
7083 |
return; |
0 |
| 7084 |
|
--- |
7084 |
|
--- |
| 7085 |
const int FrameIndex = SI->second; |
0 |
7085 |
const int FrameIndex = SI->second; |
0 |
| 7086 |
int64_t Offset; |
--- |
7086 |
int64_t Offset; |
--- |
| 7087 |
if (GetPointerBaseWithConstantOffset( |
0 |
7087 |
if (GetPointerBaseWithConstantOffset( |
0 |
| 7088 |
ObjectPtr, Offset, DAG.getDataLayout()) != LifetimeObject) |
0 |
7088 |
ObjectPtr, Offset, DAG.getDataLayout()) != LifetimeObject) |
0 |
| 7089 |
Offset = -1; // Cannot determine offset from alloca to lifetime object. |
0 |
7089 |
Offset = -1; // Cannot determine offset from alloca to lifetime object. |
0 |
| 7090 |
Res = DAG.getLifetimeNode(IsStart, sdl, getRoot(), FrameIndex, ObjectSize, |
0 |
7090 |
Res = DAG.getLifetimeNode(IsStart, sdl, getRoot(), FrameIndex, ObjectSize, |
0 |
| 7091 |
Offset); |
--- |
7091 |
Offset); |
--- |
| 7092 |
DAG.setRoot(Res); |
0 |
7092 |
DAG.setRoot(Res); |
0 |
| 7093 |
} |
--- |
7093 |
} |
--- |
| 7094 |
return; |
0 |
7094 |
return; |
0 |
| 7095 |
} |
0 |
7095 |
} |
0 |
| 7096 |
case Intrinsic::pseudoprobe: { |
0 |
7096 |
case Intrinsic::pseudoprobe: { |
0 |
| 7097 |
auto Guid = cast(I.getArgOperand(0))->getZExtValue(); |
0 |
7097 |
auto Guid = cast(I.getArgOperand(0))->getZExtValue(); |
0 |
| 7098 |
auto Index = cast(I.getArgOperand(1))->getZExtValue(); |
0 |
7098 |
auto Index = cast(I.getArgOperand(1))->getZExtValue(); |
0 |
| 7099 |
auto Attr = cast(I.getArgOperand(2))->getZExtValue(); |
0 |
7099 |
auto Attr = cast(I.getArgOperand(2))->getZExtValue(); |
0 |
| 7100 |
Res = DAG.getPseudoProbeNode(sdl, getRoot(), Guid, Index, Attr); |
0 |
7100 |
Res = DAG.getPseudoProbeNode(sdl, getRoot(), Guid, Index, Attr); |
0 |
| 7101 |
DAG.setRoot(Res); |
0 |
7101 |
DAG.setRoot(Res); |
0 |
| 7102 |
return; |
0 |
7102 |
return; |
0 |
| 7103 |
} |
--- |
7103 |
} |
--- |
| 7104 |
case Intrinsic::invariant_start: |
0 |
7104 |
case Intrinsic::invariant_start: |
0 |
| 7105 |
// Discard region information. |
--- |
7105 |
// Discard region information. |
--- |
| 7106 |
setValue(&I, |
0 |
7106 |
setValue(&I, |
0 |
| 7107 |
DAG.getUNDEF(TLI.getValueType(DAG.getDataLayout(), I.getType()))); |
0 |
7107 |
DAG.getUNDEF(TLI.getValueType(DAG.getDataLayout(), I.getType()))); |
0 |
| 7108 |
return; |
0 |
7108 |
return; |
0 |
| 7109 |
case Intrinsic::invariant_end: |
0 |
7109 |
case Intrinsic::invariant_end: |
0 |
| 7110 |
// Discard region information. |
--- |
7110 |
// Discard region information. |
--- |
| 7111 |
return; |
0 |
7111 |
return; |
0 |
| 7112 |
case Intrinsic::clear_cache: |
0 |
7112 |
case Intrinsic::clear_cache: |
0 |
| 7113 |
/// FunctionName may be null. |
--- |
7113 |
/// FunctionName may be null. |
--- |
| 7114 |
if (const char *FunctionName = TLI.getClearCacheBuiltinName()) |
0 |
7114 |
if (const char *FunctionName = TLI.getClearCacheBuiltinName()) |
0 |
| 7115 |
lowerCallToExternalSymbol(I, FunctionName); |
0 |
7115 |
lowerCallToExternalSymbol(I, FunctionName); |
0 |
| 7116 |
return; |
0 |
7116 |
return; |
0 |
| 7117 |
case Intrinsic::donothing: |
0 |
7117 |
case Intrinsic::donothing: |
0 |
| 7118 |
case Intrinsic::seh_try_begin: |
--- |
7118 |
case Intrinsic::seh_try_begin: |
--- |
| 7119 |
case Intrinsic::seh_scope_begin: |
--- |
7119 |
case Intrinsic::seh_scope_begin: |
--- |
| 7120 |
case Intrinsic::seh_try_end: |
--- |
7120 |
case Intrinsic::seh_try_end: |
--- |
| 7121 |
case Intrinsic::seh_scope_end: |
--- |
7121 |
case Intrinsic::seh_scope_end: |
--- |
| 7122 |
// ignore |
--- |
7122 |
// ignore |
--- |
| 7123 |
return; |
0 |
7123 |
return; |
0 |
| 7124 |
case Intrinsic::experimental_stackmap: |
0 |
7124 |
case Intrinsic::experimental_stackmap: |
0 |
| 7125 |
visitStackmap(I); |
0 |
7125 |
visitStackmap(I); |
0 |
| 7126 |
return; |
0 |
7126 |
return; |
0 |
| 7127 |
case Intrinsic::experimental_patchpoint_void: |
0 |
7127 |
case Intrinsic::experimental_patchpoint_void: |
0 |
| 7128 |
case Intrinsic::experimental_patchpoint_i64: |
--- |
7128 |
case Intrinsic::experimental_patchpoint_i64: |
--- |
| 7129 |
visitPatchpoint(I); |
0 |
7129 |
visitPatchpoint(I); |
0 |
| 7130 |
return; |
0 |
7130 |
return; |
0 |
| 7131 |
case Intrinsic::experimental_gc_statepoint: |
0 |
7131 |
case Intrinsic::experimental_gc_statepoint: |
0 |
| 7132 |
LowerStatepoint(cast(I)); |
0 |
7132 |
LowerStatepoint(cast(I)); |
0 |
| 7133 |
return; |
0 |
7133 |
return; |
0 |
| 7134 |
case Intrinsic::experimental_gc_result: |
0 |
7134 |
case Intrinsic::experimental_gc_result: |
0 |
| 7135 |
visitGCResult(cast(I)); |
0 |
7135 |
visitGCResult(cast(I)); |
0 |
| 7136 |
return; |
0 |
7136 |
return; |
0 |
| 7137 |
case Intrinsic::experimental_gc_relocate: |
0 |
7137 |
case Intrinsic::experimental_gc_relocate: |
0 |
| 7138 |
visitGCRelocate(cast(I)); |
0 |
7138 |
visitGCRelocate(cast(I)); |
0 |
| 7139 |
return; |
0 |
7139 |
return; |
0 |
| 7140 |
case Intrinsic::instrprof_cover: |
0 |
7140 |
case Intrinsic::instrprof_cover: |
0 |
| 7141 |
llvm_unreachable("instrprof failed to lower a cover"); |
0 |
7141 |
llvm_unreachable("instrprof failed to lower a cover"); |
0 |
| 7142 |
case Intrinsic::instrprof_increment: |
0 |
7142 |
case Intrinsic::instrprof_increment: |
0 |
| 7143 |
llvm_unreachable("instrprof failed to lower an increment"); |
0 |
7143 |
llvm_unreachable("instrprof failed to lower an increment"); |
0 |
| 7144 |
case Intrinsic::instrprof_timestamp: |
0 |
7144 |
case Intrinsic::instrprof_timestamp: |
0 |
| 7145 |
llvm_unreachable("instrprof failed to lower a timestamp"); |
0 |
7145 |
llvm_unreachable("instrprof failed to lower a timestamp"); |
0 |
| 7146 |
case Intrinsic::instrprof_value_profile: |
0 |
7146 |
case Intrinsic::instrprof_value_profile: |
0 |
| 7147 |
llvm_unreachable("instrprof failed to lower a value profiling call"); |
0 |
7147 |
llvm_unreachable("instrprof failed to lower a value profiling call"); |
0 |
| 7148 |
case Intrinsic::localescape: { |
0 |
7148 |
case Intrinsic::localescape: { |
0 |
| 7149 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
7149 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 7150 |
const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); |
0 |
7150 |
const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); |
0 |
| 7151 |
|
--- |
7151 |
|
--- |
| 7152 |
// Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission |
--- |
7152 |
// Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission |
--- |
| 7153 |
// is the same on all targets. |
--- |
7153 |
// is the same on all targets. |
--- |
| 7154 |
for (unsigned Idx = 0, E = I.arg_size(); Idx < E; ++Idx) { |
0 |
7154 |
for (unsigned Idx = 0, E = I.arg_size(); Idx < E; ++Idx) { |
0 |
| 7155 |
Value *Arg = I.getArgOperand(Idx)->stripPointerCasts(); |
0 |
7155 |
Value *Arg = I.getArgOperand(Idx)->stripPointerCasts(); |
0 |
| 7156 |
if (isa(Arg)) |
0 |
7156 |
if (isa(Arg)) |
0 |
| 7157 |
continue; // Skip null pointers. They represent a hole in index space. |
0 |
7157 |
continue; // Skip null pointers. They represent a hole in index space. |
0 |
| 7158 |
AllocaInst *Slot = cast(Arg); |
0 |
7158 |
AllocaInst *Slot = cast(Arg); |
0 |
| 7159 |
assert(FuncInfo.StaticAllocaMap.count(Slot) && |
0 |
7159 |
assert(FuncInfo.StaticAllocaMap.count(Slot) && |
0 |
| 7160 |
"can only escape static allocas"); |
--- |
7160 |
"can only escape static allocas"); |
--- |
| 7161 |
int FI = FuncInfo.StaticAllocaMap[Slot]; |
0 |
7161 |
int FI = FuncInfo.StaticAllocaMap[Slot]; |
0 |
| 7162 |
MCSymbol *FrameAllocSym = |
--- |
7162 |
MCSymbol *FrameAllocSym = |
--- |
| 7163 |
MF.getMMI().getContext().getOrCreateFrameAllocSymbol( |
0 |
7163 |
MF.getMMI().getContext().getOrCreateFrameAllocSymbol( |
0 |
| 7164 |
GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx); |
0 |
7164 |
GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx); |
0 |
| 7165 |
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl, |
0 |
7165 |
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl, |
0 |
| 7166 |
TII->get(TargetOpcode::LOCAL_ESCAPE)) |
--- |
7166 |
TII->get(TargetOpcode::LOCAL_ESCAPE)) |
--- |
| 7167 |
.addSym(FrameAllocSym) |
0 |
7167 |
.addSym(FrameAllocSym) |
0 |
| 7168 |
.addFrameIndex(FI); |
0 |
7168 |
.addFrameIndex(FI); |
0 |
| 7169 |
} |
--- |
7169 |
} |
--- |
| 7170 |
|
--- |
7170 |
|
--- |
| 7171 |
return; |
0 |
7171 |
return; |
0 |
| 7172 |
} |
--- |
7172 |
} |
--- |
| 7173 |
|
--- |
7173 |
|
--- |
| 7174 |
case Intrinsic::localrecover: { |
0 |
7174 |
case Intrinsic::localrecover: { |
0 |
| 7175 |
// i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx) |
--- |
7175 |
// i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx) |
--- |
| 7176 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
7176 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 7177 |
|
--- |
7177 |
|
--- |
| 7178 |
// Get the symbol that defines the frame offset. |
--- |
7178 |
// Get the symbol that defines the frame offset. |
--- |
| 7179 |
auto *Fn = cast(I.getArgOperand(0)->stripPointerCasts()); |
0 |
7179 |
auto *Fn = cast(I.getArgOperand(0)->stripPointerCasts()); |
0 |
| 7180 |
auto *Idx = cast(I.getArgOperand(2)); |
0 |
7180 |
auto *Idx = cast(I.getArgOperand(2)); |
0 |
| 7181 |
unsigned IdxVal = |
--- |
7181 |
unsigned IdxVal = |
--- |
| 7182 |
unsigned(Idx->getLimitedValue(std::numeric_limits::max())); |
0 |
7182 |
unsigned(Idx->getLimitedValue(std::numeric_limits::max())); |
0 |
| 7183 |
MCSymbol *FrameAllocSym = |
--- |
7183 |
MCSymbol *FrameAllocSym = |
--- |
| 7184 |
MF.getMMI().getContext().getOrCreateFrameAllocSymbol( |
0 |
7184 |
MF.getMMI().getContext().getOrCreateFrameAllocSymbol( |
0 |
| 7185 |
GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal); |
0 |
7185 |
GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal); |
0 |
| 7186 |
|
--- |
7186 |
|
--- |
| 7187 |
Value *FP = I.getArgOperand(1); |
0 |
7187 |
Value *FP = I.getArgOperand(1); |
0 |
| 7188 |
SDValue FPVal = getValue(FP); |
0 |
7188 |
SDValue FPVal = getValue(FP); |
0 |
| 7189 |
EVT PtrVT = FPVal.getValueType(); |
0 |
7189 |
EVT PtrVT = FPVal.getValueType(); |
0 |
| 7190 |
|
--- |
7190 |
|
--- |
| 7191 |
// Create a MCSymbol for the label to avoid any target lowering |
--- |
7191 |
// Create a MCSymbol for the label to avoid any target lowering |
--- |
| 7192 |
// that would make this PC relative. |
--- |
7192 |
// that would make this PC relative. |
--- |
| 7193 |
SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT); |
0 |
7193 |
SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT); |
0 |
| 7194 |
SDValue OffsetVal = |
--- |
7194 |
SDValue OffsetVal = |
--- |
| 7195 |
DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym); |
0 |
7195 |
DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym); |
0 |
| 7196 |
|
--- |
7196 |
|
--- |
| 7197 |
// Add the offset to the FP. |
--- |
7197 |
// Add the offset to the FP. |
--- |
| 7198 |
SDValue Add = DAG.getMemBasePlusOffset(FPVal, OffsetVal, sdl); |
0 |
7198 |
SDValue Add = DAG.getMemBasePlusOffset(FPVal, OffsetVal, sdl); |
0 |
| 7199 |
setValue(&I, Add); |
0 |
7199 |
setValue(&I, Add); |
0 |
| 7200 |
|
--- |
7200 |
|
--- |
| 7201 |
return; |
0 |
7201 |
return; |
0 |
| 7202 |
} |
--- |
7202 |
} |
--- |
| 7203 |
|
--- |
7203 |
|
--- |
| 7204 |
case Intrinsic::eh_exceptionpointer: |
0 |
7204 |
case Intrinsic::eh_exceptionpointer: |
0 |
| 7205 |
case Intrinsic::eh_exceptioncode: { |
--- |
7205 |
case Intrinsic::eh_exceptioncode: { |
--- |
| 7206 |
// Get the exception pointer vreg, copy from it, and resize it to fit. |
--- |
7206 |
// Get the exception pointer vreg, copy from it, and resize it to fit. |
--- |
| 7207 |
const auto *CPI = cast(I.getArgOperand(0)); |
0 |
7207 |
const auto *CPI = cast(I.getArgOperand(0)); |
0 |
| 7208 |
MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
7208 |
MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout()); |
0 |
| 7209 |
const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT); |
0 |
7209 |
const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT); |
0 |
| 7210 |
unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC); |
0 |
7210 |
unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC); |
0 |
| 7211 |
SDValue N = DAG.getCopyFromReg(DAG.getEntryNode(), sdl, VReg, PtrVT); |
0 |
7211 |
SDValue N = DAG.getCopyFromReg(DAG.getEntryNode(), sdl, VReg, PtrVT); |
0 |
| 7212 |
if (Intrinsic == Intrinsic::eh_exceptioncode) |
0 |
7212 |
if (Intrinsic == Intrinsic::eh_exceptioncode) |
0 |
| 7213 |
N = DAG.getZExtOrTrunc(N, sdl, MVT::i32); |
0 |
7213 |
N = DAG.getZExtOrTrunc(N, sdl, MVT::i32); |
0 |
| 7214 |
setValue(&I, N); |
0 |
7214 |
setValue(&I, N); |
0 |
| 7215 |
return; |
0 |
7215 |
return; |
0 |
| 7216 |
} |
--- |
7216 |
} |
--- |
| 7217 |
case Intrinsic::xray_customevent: { |
0 |
7217 |
case Intrinsic::xray_customevent: { |
0 |
| 7218 |
// Here we want to make sure that the intrinsic behaves as if it has a |
--- |
7218 |
// Here we want to make sure that the intrinsic behaves as if it has a |
--- |
| 7219 |
// specific calling convention. |
--- |
7219 |
// specific calling convention. |
--- |
| 7220 |
const auto &Triple = DAG.getTarget().getTargetTriple(); |
0 |
7220 |
const auto &Triple = DAG.getTarget().getTargetTriple(); |
0 |
| 7221 |
if (!Triple.isAArch64(64) && Triple.getArch() != Triple::x86_64) |
0 |
7221 |
if (!Triple.isAArch64(64) && Triple.getArch() != Triple::x86_64) |
0 |
| 7222 |
return; |
0 |
7222 |
return; |
0 |
| 7223 |
|
--- |
7223 |
|
--- |
| 7224 |
SmallVector Ops; |
0 |
7224 |
SmallVector Ops; |
0 |
| 7225 |
|
--- |
7225 |
|
--- |
| 7226 |
// We want to say that we always want the arguments in registers. |
--- |
7226 |
// We want to say that we always want the arguments in registers. |
--- |
| 7227 |
SDValue LogEntryVal = getValue(I.getArgOperand(0)); |
0 |
7227 |
SDValue LogEntryVal = getValue(I.getArgOperand(0)); |
0 |
| 7228 |
SDValue StrSizeVal = getValue(I.getArgOperand(1)); |
0 |
7228 |
SDValue StrSizeVal = getValue(I.getArgOperand(1)); |
0 |
| 7229 |
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
7229 |
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
| 7230 |
SDValue Chain = getRoot(); |
0 |
7230 |
SDValue Chain = getRoot(); |
0 |
| 7231 |
Ops.push_back(LogEntryVal); |
0 |
7231 |
Ops.push_back(LogEntryVal); |
0 |
| 7232 |
Ops.push_back(StrSizeVal); |
0 |
7232 |
Ops.push_back(StrSizeVal); |
0 |
| 7233 |
Ops.push_back(Chain); |
0 |
7233 |
Ops.push_back(Chain); |
0 |
| 7234 |
|
--- |
7234 |
|
--- |
| 7235 |
// We need to enforce the calling convention for the callsite, so that |
--- |
7235 |
// We need to enforce the calling convention for the callsite, so that |
--- |
| 7236 |
// argument ordering is enforced correctly, and that register allocation can |
--- |
7236 |
// argument ordering is enforced correctly, and that register allocation can |
--- |
| 7237 |
// see that some registers may be assumed clobbered and have to preserve |
--- |
7237 |
// see that some registers may be assumed clobbered and have to preserve |
--- |
| 7238 |
// them across calls to the intrinsic. |
--- |
7238 |
// them across calls to the intrinsic. |
--- |
| 7239 |
MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL, |
0 |
7239 |
MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL, |
0 |
| 7240 |
sdl, NodeTys, Ops); |
--- |
7240 |
sdl, NodeTys, Ops); |
--- |
| 7241 |
SDValue patchableNode = SDValue(MN, 0); |
0 |
7241 |
SDValue patchableNode = SDValue(MN, 0); |
0 |
| 7242 |
DAG.setRoot(patchableNode); |
0 |
7242 |
DAG.setRoot(patchableNode); |
0 |
| 7243 |
setValue(&I, patchableNode); |
0 |
7243 |
setValue(&I, patchableNode); |
0 |
| 7244 |
return; |
0 |
7244 |
return; |
0 |
| 7245 |
} |
0 |
7245 |
} |
0 |
| 7246 |
case Intrinsic::xray_typedevent: { |
0 |
7246 |
case Intrinsic::xray_typedevent: { |
0 |
| 7247 |
// Here we want to make sure that the intrinsic behaves as if it has a |
--- |
7247 |
// Here we want to make sure that the intrinsic behaves as if it has a |
--- |
| 7248 |
// specific calling convention. |
--- |
7248 |
// specific calling convention. |
--- |
| 7249 |
const auto &Triple = DAG.getTarget().getTargetTriple(); |
0 |
7249 |
const auto &Triple = DAG.getTarget().getTargetTriple(); |
0 |
| 7250 |
if (!Triple.isAArch64(64) && Triple.getArch() != Triple::x86_64) |
0 |
7250 |
if (!Triple.isAArch64(64) && Triple.getArch() != Triple::x86_64) |
0 |
| 7251 |
return; |
0 |
7251 |
return; |
0 |
| 7252 |
|
--- |
7252 |
|
--- |
| 7253 |
SmallVector Ops; |
0 |
7253 |
SmallVector Ops; |
0 |
| 7254 |
|
--- |
7254 |
|
--- |
| 7255 |
// We want to say that we always want the arguments in registers. |
--- |
7255 |
// We want to say that we always want the arguments in registers. |
--- |
| 7256 |
// It's unclear to me how manipulating the selection DAG here forces callers |
--- |
7256 |
// It's unclear to me how manipulating the selection DAG here forces callers |
--- |
| 7257 |
// to provide arguments in registers instead of on the stack. |
--- |
7257 |
// to provide arguments in registers instead of on the stack. |
--- |
| 7258 |
SDValue LogTypeId = getValue(I.getArgOperand(0)); |
0 |
7258 |
SDValue LogTypeId = getValue(I.getArgOperand(0)); |
0 |
| 7259 |
SDValue LogEntryVal = getValue(I.getArgOperand(1)); |
0 |
7259 |
SDValue LogEntryVal = getValue(I.getArgOperand(1)); |
0 |
| 7260 |
SDValue StrSizeVal = getValue(I.getArgOperand(2)); |
0 |
7260 |
SDValue StrSizeVal = getValue(I.getArgOperand(2)); |
0 |
| 7261 |
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
7261 |
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
| 7262 |
SDValue Chain = getRoot(); |
0 |
7262 |
SDValue Chain = getRoot(); |
0 |
| 7263 |
Ops.push_back(LogTypeId); |
0 |
7263 |
Ops.push_back(LogTypeId); |
0 |
| 7264 |
Ops.push_back(LogEntryVal); |
0 |
7264 |
Ops.push_back(LogEntryVal); |
0 |
| 7265 |
Ops.push_back(StrSizeVal); |
0 |
7265 |
Ops.push_back(StrSizeVal); |
0 |
| 7266 |
Ops.push_back(Chain); |
0 |
7266 |
Ops.push_back(Chain); |
0 |
| 7267 |
|
--- |
7267 |
|
--- |
| 7268 |
// We need to enforce the calling convention for the callsite, so that |
--- |
7268 |
// We need to enforce the calling convention for the callsite, so that |
--- |
| 7269 |
// argument ordering is enforced correctly, and that register allocation can |
--- |
7269 |
// argument ordering is enforced correctly, and that register allocation can |
--- |
| 7270 |
// see that some registers may be assumed clobbered and have to preserve |
--- |
7270 |
// see that some registers may be assumed clobbered and have to preserve |
--- |
| 7271 |
// them across calls to the intrinsic. |
--- |
7271 |
// them across calls to the intrinsic. |
--- |
| 7272 |
MachineSDNode *MN = DAG.getMachineNode( |
0 |
7272 |
MachineSDNode *MN = DAG.getMachineNode( |
0 |
| 7273 |
TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops); |
--- |
7273 |
TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops); |
--- |
| 7274 |
SDValue patchableNode = SDValue(MN, 0); |
0 |
7274 |
SDValue patchableNode = SDValue(MN, 0); |
0 |
| 7275 |
DAG.setRoot(patchableNode); |
0 |
7275 |
DAG.setRoot(patchableNode); |
0 |
| 7276 |
setValue(&I, patchableNode); |
0 |
7276 |
setValue(&I, patchableNode); |
0 |
| 7277 |
return; |
0 |
7277 |
return; |
0 |
| 7278 |
} |
0 |
7278 |
} |
0 |
| 7279 |
case Intrinsic::experimental_deoptimize: |
0 |
7279 |
case Intrinsic::experimental_deoptimize: |
0 |
| 7280 |
LowerDeoptimizeCall(&I); |
0 |
7280 |
LowerDeoptimizeCall(&I); |
0 |
| 7281 |
return; |
0 |
7281 |
return; |
0 |
| 7282 |
case Intrinsic::experimental_stepvector: |
0 |
7282 |
case Intrinsic::experimental_stepvector: |
0 |
| 7283 |
visitStepVector(I); |
0 |
7283 |
visitStepVector(I); |
0 |
| 7284 |
return; |
0 |
7284 |
return; |
0 |
| 7285 |
case Intrinsic::vector_reduce_fadd: |
0 |
7285 |
case Intrinsic::vector_reduce_fadd: |
0 |
| 7286 |
case Intrinsic::vector_reduce_fmul: |
--- |
7286 |
case Intrinsic::vector_reduce_fmul: |
--- |
| 7287 |
case Intrinsic::vector_reduce_add: |
--- |
7287 |
case Intrinsic::vector_reduce_add: |
--- |
| 7288 |
case Intrinsic::vector_reduce_mul: |
--- |
7288 |
case Intrinsic::vector_reduce_mul: |
--- |
| 7289 |
case Intrinsic::vector_reduce_and: |
--- |
7289 |
case Intrinsic::vector_reduce_and: |
--- |
| 7290 |
case Intrinsic::vector_reduce_or: |
--- |
7290 |
case Intrinsic::vector_reduce_or: |
--- |
| 7291 |
case Intrinsic::vector_reduce_xor: |
--- |
7291 |
case Intrinsic::vector_reduce_xor: |
--- |
| 7292 |
case Intrinsic::vector_reduce_smax: |
--- |
7292 |
case Intrinsic::vector_reduce_smax: |
--- |
| 7293 |
case Intrinsic::vector_reduce_smin: |
--- |
7293 |
case Intrinsic::vector_reduce_smin: |
--- |
| 7294 |
case Intrinsic::vector_reduce_umax: |
--- |
7294 |
case Intrinsic::vector_reduce_umax: |
--- |
| 7295 |
case Intrinsic::vector_reduce_umin: |
--- |
7295 |
case Intrinsic::vector_reduce_umin: |
--- |
| 7296 |
case Intrinsic::vector_reduce_fmax: |
--- |
7296 |
case Intrinsic::vector_reduce_fmax: |
--- |
| 7297 |
case Intrinsic::vector_reduce_fmin: |
--- |
7297 |
case Intrinsic::vector_reduce_fmin: |
--- |
| 7298 |
case Intrinsic::vector_reduce_fmaximum: |
--- |
7298 |
case Intrinsic::vector_reduce_fmaximum: |
--- |
| 7299 |
case Intrinsic::vector_reduce_fminimum: |
--- |
7299 |
case Intrinsic::vector_reduce_fminimum: |
--- |
| 7300 |
visitVectorReduce(I, Intrinsic); |
0 |
7300 |
visitVectorReduce(I, Intrinsic); |
0 |
| 7301 |
return; |
0 |
7301 |
return; |
0 |
| 7302 |
|
--- |
7302 |
|
--- |
| 7303 |
case Intrinsic::icall_branch_funnel: { |
0 |
7303 |
case Intrinsic::icall_branch_funnel: { |
0 |
| 7304 |
SmallVector Ops; |
0 |
7304 |
SmallVector Ops; |
0 |
| 7305 |
Ops.push_back(getValue(I.getArgOperand(0))); |
0 |
7305 |
Ops.push_back(getValue(I.getArgOperand(0))); |
0 |
| 7306 |
|
--- |
7306 |
|
--- |
| 7307 |
int64_t Offset; |
--- |
7307 |
int64_t Offset; |
--- |
| 7308 |
auto *Base = dyn_cast(GetPointerBaseWithConstantOffset( |
0 |
7308 |
auto *Base = dyn_cast(GetPointerBaseWithConstantOffset( |
0 |
| 7309 |
I.getArgOperand(1), Offset, DAG.getDataLayout())); |
0 |
7309 |
I.getArgOperand(1), Offset, DAG.getDataLayout())); |
0 |
| 7310 |
if (!Base) |
0 |
7310 |
if (!Base) |
0 |
| 7311 |
report_fatal_error( |
0 |
7311 |
report_fatal_error( |
0 |
| 7312 |
"llvm.icall.branch.funnel operand must be a GlobalValue"); |
--- |
7312 |
"llvm.icall.branch.funnel operand must be a GlobalValue"); |
--- |
| 7313 |
Ops.push_back(DAG.getTargetGlobalAddress(Base, sdl, MVT::i64, 0)); |
0 |
7313 |
Ops.push_back(DAG.getTargetGlobalAddress(Base, sdl, MVT::i64, 0)); |
0 |
| 7314 |
|
--- |
7314 |
|
--- |
| 7315 |
struct BranchFunnelTarget { |
--- |
7315 |
struct BranchFunnelTarget { |
--- |
| 7316 |
int64_t Offset; |
--- |
7316 |
int64_t Offset; |
--- |
| 7317 |
SDValue Target; |
--- |
7317 |
SDValue Target; |
--- |
| 7318 |
}; |
--- |
7318 |
}; |
--- |
| 7319 |
SmallVector Targets; |
0 |
7319 |
SmallVector Targets; |
0 |
| 7320 |
|
--- |
7320 |
|
--- |
| 7321 |
for (unsigned Op = 1, N = I.arg_size(); Op != N; Op += 2) { |
0 |
7321 |
for (unsigned Op = 1, N = I.arg_size(); Op != N; Op += 2) { |
0 |
| 7322 |
auto *ElemBase = dyn_cast(GetPointerBaseWithConstantOffset( |
0 |
7322 |
auto *ElemBase = dyn_cast(GetPointerBaseWithConstantOffset( |
0 |
| 7323 |
I.getArgOperand(Op), Offset, DAG.getDataLayout())); |
0 |
7323 |
I.getArgOperand(Op), Offset, DAG.getDataLayout())); |
0 |
| 7324 |
if (ElemBase != Base) |
0 |
7324 |
if (ElemBase != Base) |
0 |
| 7325 |
report_fatal_error("all llvm.icall.branch.funnel operands must refer " |
0 |
7325 |
report_fatal_error("all llvm.icall.branch.funnel operands must refer " |
0 |
| 7326 |
"to the same GlobalValue"); |
--- |
7326 |
"to the same GlobalValue"); |
--- |
| 7327 |
|
--- |
7327 |
|
--- |
| 7328 |
SDValue Val = getValue(I.getArgOperand(Op + 1)); |
0 |
7328 |
SDValue Val = getValue(I.getArgOperand(Op + 1)); |
0 |
| 7329 |
auto *GA = dyn_cast(Val); |
0 |
7329 |
auto *GA = dyn_cast(Val); |
0 |
| 7330 |
if (!GA) |
0 |
7330 |
if (!GA) |
0 |
| 7331 |
report_fatal_error( |
0 |
7331 |
report_fatal_error( |
0 |
| 7332 |
"llvm.icall.branch.funnel operand must be a GlobalValue"); |
--- |
7332 |
"llvm.icall.branch.funnel operand must be a GlobalValue"); |
--- |
| 7333 |
Targets.push_back({Offset, DAG.getTargetGlobalAddress( |
0 |
7333 |
Targets.push_back({Offset, DAG.getTargetGlobalAddress( |
0 |
| 7334 |
GA->getGlobal(), sdl, Val.getValueType(), |
--- |
7334 |
GA->getGlobal(), sdl, Val.getValueType(), |
--- |
| 7335 |
GA->getOffset())}); |
--- |
7335 |
GA->getOffset())}); |
--- |
| 7336 |
} |
--- |
7336 |
} |
--- |
| 7337 |
llvm::sort(Targets, |
0 |
7337 |
llvm::sort(Targets, |
0 |
| 7338 |
[](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) { |
0 |
7338 |
[](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) { |
0 |
| 7339 |
return T1.Offset < T2.Offset; |
0 |
7339 |
return T1.Offset < T2.Offset; |
0 |
| 7340 |
}); |
--- |
7340 |
}); |
--- |
| 7341 |
|
--- |
7341 |
|
--- |
| 7342 |
for (auto &T : Targets) { |
0 |
7342 |
for (auto &T : Targets) { |
0 |
| 7343 |
Ops.push_back(DAG.getTargetConstant(T.Offset, sdl, MVT::i32)); |
0 |
7343 |
Ops.push_back(DAG.getTargetConstant(T.Offset, sdl, MVT::i32)); |
0 |
| 7344 |
Ops.push_back(T.Target); |
0 |
7344 |
Ops.push_back(T.Target); |
0 |
| 7345 |
} |
--- |
7345 |
} |
--- |
| 7346 |
|
--- |
7346 |
|
--- |
| 7347 |
Ops.push_back(DAG.getRoot()); // Chain |
0 |
7347 |
Ops.push_back(DAG.getRoot()); // Chain |
0 |
| 7348 |
SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL, sdl, |
0 |
7348 |
SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL, sdl, |
0 |
| 7349 |
MVT::Other, Ops), |
--- |
7349 |
MVT::Other, Ops), |
--- |
| 7350 |
0); |
0 |
7350 |
0); |
0 |
| 7351 |
DAG.setRoot(N); |
0 |
7351 |
DAG.setRoot(N); |
0 |
| 7352 |
setValue(&I, N); |
0 |
7352 |
setValue(&I, N); |
0 |
| 7353 |
HasTailCall = true; |
0 |
7353 |
HasTailCall = true; |
0 |
| 7354 |
return; |
0 |
7354 |
return; |
0 |
| 7355 |
} |
0 |
7355 |
} |
0 |
| 7356 |
|
--- |
7356 |
|
--- |
| 7357 |
case Intrinsic::wasm_landingpad_index: |
0 |
7357 |
case Intrinsic::wasm_landingpad_index: |
0 |
| 7358 |
// Information this intrinsic contained has been transferred to |
--- |
7358 |
// Information this intrinsic contained has been transferred to |
--- |
| 7359 |
// MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely |
--- |
7359 |
// MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely |
--- |
| 7360 |
// delete it now. |
--- |
7360 |
// delete it now. |
--- |
| 7361 |
return; |
0 |
7361 |
return; |
0 |
| 7362 |
|
--- |
7362 |
|
--- |
| 7363 |
case Intrinsic::aarch64_settag: |
0 |
7363 |
case Intrinsic::aarch64_settag: |
0 |
| 7364 |
case Intrinsic::aarch64_settag_zero: { |
--- |
7364 |
case Intrinsic::aarch64_settag_zero: { |
--- |
| 7365 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
7365 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 7366 |
bool ZeroMemory = Intrinsic == Intrinsic::aarch64_settag_zero; |
0 |
7366 |
bool ZeroMemory = Intrinsic == Intrinsic::aarch64_settag_zero; |
0 |
| 7367 |
SDValue Val = TSI.EmitTargetCodeForSetTag( |
0 |
7367 |
SDValue Val = TSI.EmitTargetCodeForSetTag( |
0 |
| 7368 |
DAG, sdl, getRoot(), getValue(I.getArgOperand(0)), |
0 |
7368 |
DAG, sdl, getRoot(), getValue(I.getArgOperand(0)), |
0 |
| 7369 |
getValue(I.getArgOperand(1)), MachinePointerInfo(I.getArgOperand(0)), |
0 |
7369 |
getValue(I.getArgOperand(1)), MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 7370 |
ZeroMemory); |
--- |
7370 |
ZeroMemory); |
--- |
| 7371 |
DAG.setRoot(Val); |
0 |
7371 |
DAG.setRoot(Val); |
0 |
| 7372 |
setValue(&I, Val); |
0 |
7372 |
setValue(&I, Val); |
0 |
| 7373 |
return; |
0 |
7373 |
return; |
0 |
| 7374 |
} |
--- |
7374 |
} |
--- |
| 7375 |
case Intrinsic::ptrmask: { |
0 |
7375 |
case Intrinsic::ptrmask: { |
0 |
| 7376 |
SDValue Ptr = getValue(I.getOperand(0)); |
0 |
7376 |
SDValue Ptr = getValue(I.getOperand(0)); |
0 |
| 7377 |
SDValue Const = getValue(I.getOperand(1)); |
0 |
7377 |
SDValue Const = getValue(I.getOperand(1)); |
0 |
| 7378 |
|
--- |
7378 |
|
--- |
| 7379 |
EVT PtrVT = Ptr.getValueType(); |
0 |
7379 |
EVT PtrVT = Ptr.getValueType(); |
0 |
| 7380 |
setValue(&I, DAG.getNode(ISD::AND, sdl, PtrVT, Ptr, |
0 |
7380 |
setValue(&I, DAG.getNode(ISD::AND, sdl, PtrVT, Ptr, |
0 |
| 7381 |
DAG.getZExtOrTrunc(Const, sdl, PtrVT))); |
0 |
7381 |
DAG.getZExtOrTrunc(Const, sdl, PtrVT))); |
0 |
| 7382 |
return; |
0 |
7382 |
return; |
0 |
| 7383 |
} |
--- |
7383 |
} |
--- |
| 7384 |
case Intrinsic::threadlocal_address: { |
0 |
7384 |
case Intrinsic::threadlocal_address: { |
0 |
| 7385 |
setValue(&I, getValue(I.getOperand(0))); |
0 |
7385 |
setValue(&I, getValue(I.getOperand(0))); |
0 |
| 7386 |
return; |
0 |
7386 |
return; |
0 |
| 7387 |
} |
--- |
7387 |
} |
--- |
| 7388 |
case Intrinsic::get_active_lane_mask: { |
0 |
7388 |
case Intrinsic::get_active_lane_mask: { |
0 |
| 7389 |
EVT CCVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
7389 |
EVT CCVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 7390 |
SDValue Index = getValue(I.getOperand(0)); |
0 |
7390 |
SDValue Index = getValue(I.getOperand(0)); |
0 |
| 7391 |
EVT ElementVT = Index.getValueType(); |
0 |
7391 |
EVT ElementVT = Index.getValueType(); |
0 |
| 7392 |
|
--- |
7392 |
|
--- |
| 7393 |
if (!TLI.shouldExpandGetActiveLaneMask(CCVT, ElementVT)) { |
0 |
7393 |
if (!TLI.shouldExpandGetActiveLaneMask(CCVT, ElementVT)) { |
0 |
| 7394 |
visitTargetIntrinsic(I, Intrinsic); |
0 |
7394 |
visitTargetIntrinsic(I, Intrinsic); |
0 |
| 7395 |
return; |
0 |
7395 |
return; |
0 |
| 7396 |
} |
--- |
7396 |
} |
--- |
| 7397 |
|
--- |
7397 |
|
--- |
| 7398 |
SDValue TripCount = getValue(I.getOperand(1)); |
0 |
7398 |
SDValue TripCount = getValue(I.getOperand(1)); |
0 |
| 7399 |
auto VecTy = CCVT.changeVectorElementType(ElementVT); |
0 |
7399 |
auto VecTy = CCVT.changeVectorElementType(ElementVT); |
0 |
| 7400 |
|
--- |
7400 |
|
--- |
| 7401 |
SDValue VectorIndex = DAG.getSplat(VecTy, sdl, Index); |
0 |
7401 |
SDValue VectorIndex = DAG.getSplat(VecTy, sdl, Index); |
0 |
| 7402 |
SDValue VectorTripCount = DAG.getSplat(VecTy, sdl, TripCount); |
0 |
7402 |
SDValue VectorTripCount = DAG.getSplat(VecTy, sdl, TripCount); |
0 |
| 7403 |
SDValue VectorStep = DAG.getStepVector(sdl, VecTy); |
0 |
7403 |
SDValue VectorStep = DAG.getStepVector(sdl, VecTy); |
0 |
| 7404 |
SDValue VectorInduction = DAG.getNode( |
0 |
7404 |
SDValue VectorInduction = DAG.getNode( |
0 |
| 7405 |
ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); |
--- |
7405 |
ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); |
--- |
| 7406 |
SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, |
0 |
7406 |
SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, |
0 |
| 7407 |
VectorTripCount, ISD::CondCode::SETULT); |
--- |
7407 |
VectorTripCount, ISD::CondCode::SETULT); |
--- |
| 7408 |
setValue(&I, SetCC); |
0 |
7408 |
setValue(&I, SetCC); |
0 |
| 7409 |
return; |
0 |
7409 |
return; |
0 |
| 7410 |
} |
--- |
7410 |
} |
--- |
| 7411 |
case Intrinsic::experimental_get_vector_length: { |
0 |
7411 |
case Intrinsic::experimental_get_vector_length: { |
0 |
| 7412 |
assert(cast(I.getOperand(1))->getSExtValue() > 0 && |
0 |
7412 |
assert(cast(I.getOperand(1))->getSExtValue() > 0 && |
0 |
| 7413 |
"Expected positive VF"); |
--- |
7413 |
"Expected positive VF"); |
--- |
| 7414 |
unsigned VF = cast(I.getOperand(1))->getZExtValue(); |
0 |
7414 |
unsigned VF = cast(I.getOperand(1))->getZExtValue(); |
0 |
| 7415 |
bool IsScalable = cast(I.getOperand(2))->isOne(); |
0 |
7415 |
bool IsScalable = cast(I.getOperand(2))->isOne(); |
0 |
| 7416 |
|
--- |
7416 |
|
--- |
| 7417 |
SDValue Count = getValue(I.getOperand(0)); |
0 |
7417 |
SDValue Count = getValue(I.getOperand(0)); |
0 |
| 7418 |
EVT CountVT = Count.getValueType(); |
0 |
7418 |
EVT CountVT = Count.getValueType(); |
0 |
| 7419 |
|
--- |
7419 |
|
--- |
| 7420 |
if (!TLI.shouldExpandGetVectorLength(CountVT, VF, IsScalable)) { |
0 |
7420 |
if (!TLI.shouldExpandGetVectorLength(CountVT, VF, IsScalable)) { |
0 |
| 7421 |
visitTargetIntrinsic(I, Intrinsic); |
0 |
7421 |
visitTargetIntrinsic(I, Intrinsic); |
0 |
| 7422 |
return; |
0 |
7422 |
return; |
0 |
| 7423 |
} |
--- |
7423 |
} |
--- |
| 7424 |
|
--- |
7424 |
|
--- |
| 7425 |
// Expand to a umin between the trip count and the maximum elements the type |
--- |
7425 |
// Expand to a umin between the trip count and the maximum elements the type |
--- |
| 7426 |
// can hold. |
--- |
7426 |
// can hold. |
--- |
| 7427 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
7427 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 7428 |
|
--- |
7428 |
|
--- |
| 7429 |
// Extend the trip count to at least the result VT. |
--- |
7429 |
// Extend the trip count to at least the result VT. |
--- |
| 7430 |
if (CountVT.bitsLT(VT)) { |
0 |
7430 |
if (CountVT.bitsLT(VT)) { |
0 |
| 7431 |
Count = DAG.getNode(ISD::ZERO_EXTEND, sdl, VT, Count); |
0 |
7431 |
Count = DAG.getNode(ISD::ZERO_EXTEND, sdl, VT, Count); |
0 |
| 7432 |
CountVT = VT; |
0 |
7432 |
CountVT = VT; |
0 |
| 7433 |
} |
--- |
7433 |
} |
--- |
| 7434 |
|
--- |
7434 |
|
--- |
| 7435 |
SDValue MaxEVL = DAG.getElementCount(sdl, CountVT, |
0 |
7435 |
SDValue MaxEVL = DAG.getElementCount(sdl, CountVT, |
0 |
| 7436 |
ElementCount::get(VF, IsScalable)); |
--- |
7436 |
ElementCount::get(VF, IsScalable)); |
--- |
| 7437 |
|
--- |
7437 |
|
--- |
| 7438 |
SDValue UMin = DAG.getNode(ISD::UMIN, sdl, CountVT, Count, MaxEVL); |
0 |
7438 |
SDValue UMin = DAG.getNode(ISD::UMIN, sdl, CountVT, Count, MaxEVL); |
0 |
| 7439 |
// Clip to the result type if needed. |
--- |
7439 |
// Clip to the result type if needed. |
--- |
| 7440 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, sdl, VT, UMin); |
0 |
7440 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, sdl, VT, UMin); |
0 |
| 7441 |
|
--- |
7441 |
|
--- |
| 7442 |
setValue(&I, Trunc); |
0 |
7442 |
setValue(&I, Trunc); |
0 |
| 7443 |
return; |
0 |
7443 |
return; |
0 |
| 7444 |
} |
--- |
7444 |
} |
--- |
| 7445 |
case Intrinsic::vector_insert: { |
0 |
7445 |
case Intrinsic::vector_insert: { |
0 |
| 7446 |
SDValue Vec = getValue(I.getOperand(0)); |
0 |
7446 |
SDValue Vec = getValue(I.getOperand(0)); |
0 |
| 7447 |
SDValue SubVec = getValue(I.getOperand(1)); |
0 |
7447 |
SDValue SubVec = getValue(I.getOperand(1)); |
0 |
| 7448 |
SDValue Index = getValue(I.getOperand(2)); |
0 |
7448 |
SDValue Index = getValue(I.getOperand(2)); |
0 |
| 7449 |
|
--- |
7449 |
|
--- |
| 7450 |
// The intrinsic's index type is i64, but the SDNode requires an index type |
--- |
7450 |
// The intrinsic's index type is i64, but the SDNode requires an index type |
--- |
| 7451 |
// suitable for the target. Convert the index as required. |
--- |
7451 |
// suitable for the target. Convert the index as required. |
--- |
| 7452 |
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); |
0 |
7452 |
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); |
0 |
| 7453 |
if (Index.getValueType() != VectorIdxTy) |
0 |
7453 |
if (Index.getValueType() != VectorIdxTy) |
0 |
| 7454 |
Index = DAG.getVectorIdxConstant( |
0 |
7454 |
Index = DAG.getVectorIdxConstant( |
0 |
| 7455 |
cast(Index)->getZExtValue(), sdl); |
--- |
7455 |
cast(Index)->getZExtValue(), sdl); |
--- |
| 7456 |
|
--- |
7456 |
|
--- |
| 7457 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
7457 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 7458 |
setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, |
0 |
7458 |
setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, |
0 |
| 7459 |
Index)); |
--- |
7459 |
Index)); |
--- |
| 7460 |
return; |
0 |
7460 |
return; |
0 |
| 7461 |
} |
--- |
7461 |
} |
--- |
| 7462 |
case Intrinsic::vector_extract: { |
0 |
7462 |
case Intrinsic::vector_extract: { |
0 |
| 7463 |
SDValue Vec = getValue(I.getOperand(0)); |
0 |
7463 |
SDValue Vec = getValue(I.getOperand(0)); |
0 |
| 7464 |
SDValue Index = getValue(I.getOperand(1)); |
0 |
7464 |
SDValue Index = getValue(I.getOperand(1)); |
0 |
| 7465 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
7465 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 7466 |
|
--- |
7466 |
|
--- |
| 7467 |
// The intrinsic's index type is i64, but the SDNode requires an index type |
--- |
7467 |
// The intrinsic's index type is i64, but the SDNode requires an index type |
--- |
| 7468 |
// suitable for the target. Convert the index as required. |
--- |
7468 |
// suitable for the target. Convert the index as required. |
--- |
| 7469 |
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); |
0 |
7469 |
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); |
0 |
| 7470 |
if (Index.getValueType() != VectorIdxTy) |
0 |
7470 |
if (Index.getValueType() != VectorIdxTy) |
0 |
| 7471 |
Index = DAG.getVectorIdxConstant( |
0 |
7471 |
Index = DAG.getVectorIdxConstant( |
0 |
| 7472 |
cast(Index)->getZExtValue(), sdl); |
--- |
7472 |
cast(Index)->getZExtValue(), sdl); |
--- |
| 7473 |
|
--- |
7473 |
|
--- |
| 7474 |
setValue(&I, |
0 |
7474 |
setValue(&I, |
0 |
| 7475 |
DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); |
0 |
7475 |
DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); |
0 |
| 7476 |
return; |
0 |
7476 |
return; |
0 |
| 7477 |
} |
--- |
7477 |
} |
--- |
| 7478 |
case Intrinsic::experimental_vector_reverse: |
0 |
7478 |
case Intrinsic::experimental_vector_reverse: |
0 |
| 7479 |
visitVectorReverse(I); |
0 |
7479 |
visitVectorReverse(I); |
0 |
| 7480 |
return; |
0 |
7480 |
return; |
0 |
| 7481 |
case Intrinsic::experimental_vector_splice: |
0 |
7481 |
case Intrinsic::experimental_vector_splice: |
0 |
| 7482 |
visitVectorSplice(I); |
0 |
7482 |
visitVectorSplice(I); |
0 |
| 7483 |
return; |
0 |
7483 |
return; |
0 |
| 7484 |
case Intrinsic::callbr_landingpad: |
0 |
7484 |
case Intrinsic::callbr_landingpad: |
0 |
| 7485 |
visitCallBrLandingPad(I); |
0 |
7485 |
visitCallBrLandingPad(I); |
0 |
| 7486 |
return; |
0 |
7486 |
return; |
0 |
| 7487 |
case Intrinsic::experimental_vector_interleave2: |
0 |
7487 |
case Intrinsic::experimental_vector_interleave2: |
0 |
| 7488 |
visitVectorInterleave(I); |
0 |
7488 |
visitVectorInterleave(I); |
0 |
| 7489 |
return; |
0 |
7489 |
return; |
0 |
| 7490 |
case Intrinsic::experimental_vector_deinterleave2: |
0 |
7490 |
case Intrinsic::experimental_vector_deinterleave2: |
0 |
| 7491 |
visitVectorDeinterleave(I); |
0 |
7491 |
visitVectorDeinterleave(I); |
0 |
| 7492 |
return; |
0 |
7492 |
return; |
0 |
| 7493 |
} |
--- |
7493 |
} |
--- |
| 7494 |
} |
3 |
7494 |
} |
0 |
| 7495 |
|
--- |
7495 |
|
--- |
| 7496 |
void SelectionDAGBuilder::visitConstrainedFPIntrinsic( |
0 |
7496 |
void SelectionDAGBuilder::visitConstrainedFPIntrinsic( |
0 |
| 7497 |
const ConstrainedFPIntrinsic &FPI) { |
--- |
7497 |
const ConstrainedFPIntrinsic &FPI) { |
--- |
| 7498 |
SDLoc sdl = getCurSDLoc(); |
0 |
7498 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 7499 |
|
--- |
7499 |
|
--- |
| 7500 |
// We do not need to serialize constrained FP intrinsics against |
--- |
7500 |
// We do not need to serialize constrained FP intrinsics against |
--- |
| 7501 |
// each other or against (nonvolatile) loads, so they can be |
--- |
7501 |
// each other or against (nonvolatile) loads, so they can be |
--- |
| 7502 |
// chained like loads. |
--- |
7502 |
// chained like loads. |
--- |
| 7503 |
SDValue Chain = DAG.getRoot(); |
0 |
7503 |
SDValue Chain = DAG.getRoot(); |
0 |
| 7504 |
SmallVector Opers; |
0 |
7504 |
SmallVector Opers; |
0 |
| 7505 |
Opers.push_back(Chain); |
0 |
7505 |
Opers.push_back(Chain); |
0 |
| 7506 |
if (FPI.isUnaryOp()) { |
0 |
7506 |
if (FPI.isUnaryOp()) { |
0 |
| 7507 |
Opers.push_back(getValue(FPI.getArgOperand(0))); |
0 |
7507 |
Opers.push_back(getValue(FPI.getArgOperand(0))); |
0 |
| 7508 |
} else if (FPI.isTernaryOp()) { |
0 |
7508 |
} else if (FPI.isTernaryOp()) { |
0 |
| 7509 |
Opers.push_back(getValue(FPI.getArgOperand(0))); |
0 |
7509 |
Opers.push_back(getValue(FPI.getArgOperand(0))); |
0 |
| 7510 |
Opers.push_back(getValue(FPI.getArgOperand(1))); |
0 |
7510 |
Opers.push_back(getValue(FPI.getArgOperand(1))); |
0 |
| 7511 |
Opers.push_back(getValue(FPI.getArgOperand(2))); |
0 |
7511 |
Opers.push_back(getValue(FPI.getArgOperand(2))); |
0 |
| 7512 |
} else { |
--- |
7512 |
} else { |
--- |
| 7513 |
Opers.push_back(getValue(FPI.getArgOperand(0))); |
0 |
7513 |
Opers.push_back(getValue(FPI.getArgOperand(0))); |
0 |
| 7514 |
Opers.push_back(getValue(FPI.getArgOperand(1))); |
0 |
7514 |
Opers.push_back(getValue(FPI.getArgOperand(1))); |
0 |
| 7515 |
} |
--- |
7515 |
} |
--- |
| 7516 |
|
--- |
7516 |
|
--- |
| 7517 |
auto pushOutChain = [this](SDValue Result, fp::ExceptionBehavior EB) { |
0 |
7517 |
auto pushOutChain = [this](SDValue Result, fp::ExceptionBehavior EB) { |
0 |
| 7518 |
assert(Result.getNode()->getNumValues() == 2); |
0 |
7518 |
assert(Result.getNode()->getNumValues() == 2); |
0 |
| 7519 |
|
--- |
7519 |
|
--- |
| 7520 |
// Push node to the appropriate list so that future instructions can be |
--- |
7520 |
// Push node to the appropriate list so that future instructions can be |
--- |
| 7521 |
// chained up correctly. |
--- |
7521 |
// chained up correctly. |
--- |
| 7522 |
SDValue OutChain = Result.getValue(1); |
0 |
7522 |
SDValue OutChain = Result.getValue(1); |
0 |
| 7523 |
switch (EB) { |
0 |
7523 |
switch (EB) { |
0 |
| 7524 |
case fp::ExceptionBehavior::ebIgnore: |
0 |
7524 |
case fp::ExceptionBehavior::ebIgnore: |
0 |
| 7525 |
// The only reason why ebIgnore nodes still need to be chained is that |
--- |
7525 |
// The only reason why ebIgnore nodes still need to be chained is that |
--- |
| 7526 |
// they might depend on the current rounding mode, and therefore must |
--- |
7526 |
// they might depend on the current rounding mode, and therefore must |
--- |
| 7527 |
// not be moved across instruction that may change that mode. |
--- |
7527 |
// not be moved across instruction that may change that mode. |
--- |
| 7528 |
[[fallthrough]]; |
--- |
7528 |
[[fallthrough]]; |
--- |
| 7529 |
case fp::ExceptionBehavior::ebMayTrap: |
--- |
7529 |
case fp::ExceptionBehavior::ebMayTrap: |
--- |
| 7530 |
// These must not be moved across calls or instructions that may change |
--- |
7530 |
// These must not be moved across calls or instructions that may change |
--- |
| 7531 |
// floating-point exception masks. |
--- |
7531 |
// floating-point exception masks. |
--- |
| 7532 |
PendingConstrainedFP.push_back(OutChain); |
0 |
7532 |
PendingConstrainedFP.push_back(OutChain); |
0 |
| 7533 |
break; |
0 |
7533 |
break; |
0 |
| 7534 |
case fp::ExceptionBehavior::ebStrict: |
0 |
7534 |
case fp::ExceptionBehavior::ebStrict: |
0 |
| 7535 |
// These must not be moved across calls or instructions that may change |
--- |
7535 |
// These must not be moved across calls or instructions that may change |
--- |
| 7536 |
// floating-point exception masks or read floating-point exception flags. |
--- |
7536 |
// floating-point exception masks or read floating-point exception flags. |
--- |
| 7537 |
// In addition, they cannot be optimized out even if unused. |
--- |
7537 |
// In addition, they cannot be optimized out even if unused. |
--- |
| 7538 |
PendingConstrainedFPStrict.push_back(OutChain); |
0 |
7538 |
PendingConstrainedFPStrict.push_back(OutChain); |
0 |
| 7539 |
break; |
0 |
7539 |
break; |
0 |
| 7540 |
} |
--- |
7540 |
} |
--- |
| 7541 |
}; |
0 |
7541 |
}; |
0 |
| 7542 |
|
--- |
7542 |
|
--- |
| 7543 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
7543 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 7544 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), FPI.getType()); |
0 |
7544 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), FPI.getType()); |
0 |
| 7545 |
SDVTList VTs = DAG.getVTList(VT, MVT::Other); |
0 |
7545 |
SDVTList VTs = DAG.getVTList(VT, MVT::Other); |
0 |
| 7546 |
fp::ExceptionBehavior EB = *FPI.getExceptionBehavior(); |
0 |
7546 |
fp::ExceptionBehavior EB = *FPI.getExceptionBehavior(); |
0 |
| 7547 |
|
--- |
7547 |
|
--- |
| 7548 |
SDNodeFlags Flags; |
0 |
7548 |
SDNodeFlags Flags; |
0 |
| 7549 |
if (EB == fp::ExceptionBehavior::ebIgnore) |
0 |
7549 |
if (EB == fp::ExceptionBehavior::ebIgnore) |
0 |
| 7550 |
Flags.setNoFPExcept(true); |
0 |
7550 |
Flags.setNoFPExcept(true); |
0 |
| 7551 |
|
--- |
7551 |
|
--- |
| 7552 |
if (auto *FPOp = dyn_cast(&FPI)) |
0 |
7552 |
if (auto *FPOp = dyn_cast(&FPI)) |
0 |
| 7553 |
Flags.copyFMF(*FPOp); |
0 |
7553 |
Flags.copyFMF(*FPOp); |
0 |
| 7554 |
|
--- |
7554 |
|
--- |
| 7555 |
unsigned Opcode; |
--- |
7555 |
unsigned Opcode; |
--- |
| 7556 |
switch (FPI.getIntrinsicID()) { |
0 |
7556 |
switch (FPI.getIntrinsicID()) { |
0 |
| 7557 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
7557 |
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. |
0 |
| 7558 |
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ |
--- |
7558 |
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ |
--- |
| 7559 |
case Intrinsic::INTRINSIC: \ |
--- |
7559 |
case Intrinsic::INTRINSIC: \ |
--- |
| 7560 |
Opcode = ISD::STRICT_##DAGN; \ |
--- |
7560 |
Opcode = ISD::STRICT_##DAGN; \ |
--- |
| 7561 |
break; |
--- |
7561 |
break; |
--- |
| 7562 |
#include "llvm/IR/ConstrainedOps.def" |
--- |
7562 |
#include "llvm/IR/ConstrainedOps.def" |
--- |
| 7563 |
case Intrinsic::experimental_constrained_fmuladd: { |
0 |
7563 |
case Intrinsic::experimental_constrained_fmuladd: { |
0 |
| 7564 |
Opcode = ISD::STRICT_FMA; |
0 |
7564 |
Opcode = ISD::STRICT_FMA; |
0 |
| 7565 |
// Break fmuladd into fmul and fadd. |
--- |
7565 |
// Break fmuladd into fmul and fadd. |
--- |
| 7566 |
if (TM.Options.AllowFPOpFusion == FPOpFusion::Strict || |
0 |
7566 |
if (TM.Options.AllowFPOpFusion == FPOpFusion::Strict || |
0 |
| 7567 |
!TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) { |
0 |
7567 |
!TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) { |
0 |
| 7568 |
Opers.pop_back(); |
0 |
7568 |
Opers.pop_back(); |
0 |
| 7569 |
SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, sdl, VTs, Opers, Flags); |
0 |
7569 |
SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, sdl, VTs, Opers, Flags); |
0 |
| 7570 |
pushOutChain(Mul, EB); |
0 |
7570 |
pushOutChain(Mul, EB); |
0 |
| 7571 |
Opcode = ISD::STRICT_FADD; |
0 |
7571 |
Opcode = ISD::STRICT_FADD; |
0 |
| 7572 |
Opers.clear(); |
0 |
7572 |
Opers.clear(); |
0 |
| 7573 |
Opers.push_back(Mul.getValue(1)); |
0 |
7573 |
Opers.push_back(Mul.getValue(1)); |
0 |
| 7574 |
Opers.push_back(Mul.getValue(0)); |
0 |
7574 |
Opers.push_back(Mul.getValue(0)); |
0 |
| 7575 |
Opers.push_back(getValue(FPI.getArgOperand(2))); |
0 |
7575 |
Opers.push_back(getValue(FPI.getArgOperand(2))); |
0 |
| 7576 |
} |
--- |
7576 |
} |
--- |
| 7577 |
break; |
0 |
7577 |
break; |
0 |
| 7578 |
} |
--- |
7578 |
} |
--- |
| 7579 |
} |
--- |
7579 |
} |
--- |
| 7580 |
|
--- |
7580 |
|
--- |
| 7581 |
// A few strict DAG nodes carry additional operands that are not |
--- |
7581 |
// A few strict DAG nodes carry additional operands that are not |
--- |
| 7582 |
// set up by the default code above. |
--- |
7582 |
// set up by the default code above. |
--- |
| 7583 |
switch (Opcode) { |
0 |
7583 |
switch (Opcode) { |
0 |
| 7584 |
default: break; |
0 |
7584 |
default: break; |
0 |
| 7585 |
case ISD::STRICT_FP_ROUND: |
0 |
7585 |
case ISD::STRICT_FP_ROUND: |
0 |
| 7586 |
Opers.push_back( |
0 |
7586 |
Opers.push_back( |
0 |
| 7587 |
DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
7587 |
DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 7588 |
break; |
0 |
7588 |
break; |
0 |
| 7589 |
case ISD::STRICT_FSETCC: |
0 |
7589 |
case ISD::STRICT_FSETCC: |
0 |
| 7590 |
case ISD::STRICT_FSETCCS: { |
--- |
7590 |
case ISD::STRICT_FSETCCS: { |
--- |
| 7591 |
auto *FPCmp = dyn_cast(&FPI); |
0 |
7591 |
auto *FPCmp = dyn_cast(&FPI); |
0 |
| 7592 |
ISD::CondCode Condition = getFCmpCondCode(FPCmp->getPredicate()); |
0 |
7592 |
ISD::CondCode Condition = getFCmpCondCode(FPCmp->getPredicate()); |
0 |
| 7593 |
if (TM.Options.NoNaNsFPMath) |
0 |
7593 |
if (TM.Options.NoNaNsFPMath) |
0 |
| 7594 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
7594 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
| 7595 |
Opers.push_back(DAG.getCondCode(Condition)); |
0 |
7595 |
Opers.push_back(DAG.getCondCode(Condition)); |
0 |
| 7596 |
break; |
0 |
7596 |
break; |
0 |
| 7597 |
} |
--- |
7597 |
} |
--- |
| 7598 |
} |
--- |
7598 |
} |
--- |
| 7599 |
|
--- |
7599 |
|
--- |
| 7600 |
SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers, Flags); |
0 |
7600 |
SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers, Flags); |
0 |
| 7601 |
pushOutChain(Result, EB); |
0 |
7601 |
pushOutChain(Result, EB); |
0 |
| 7602 |
|
--- |
7602 |
|
--- |
| 7603 |
SDValue FPResult = Result.getValue(0); |
0 |
7603 |
SDValue FPResult = Result.getValue(0); |
0 |
| 7604 |
setValue(&FPI, FPResult); |
0 |
7604 |
setValue(&FPI, FPResult); |
0 |
| 7605 |
} |
0 |
7605 |
} |
0 |
| 7606 |
|
--- |
7606 |
|
--- |
| 7607 |
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) { |
0 |
7607 |
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) { |
0 |
| 7608 |
std::optional ResOPC; |
0 |
7608 |
std::optional ResOPC; |
0 |
| 7609 |
switch (VPIntrin.getIntrinsicID()) { |
0 |
7609 |
switch (VPIntrin.getIntrinsicID()) { |
0 |
| 7610 |
case Intrinsic::vp_ctlz: { |
0 |
7610 |
case Intrinsic::vp_ctlz: { |
0 |
| 7611 |
bool IsZeroUndef = cast(VPIntrin.getArgOperand(1))->isOne(); |
0 |
7611 |
bool IsZeroUndef = cast(VPIntrin.getArgOperand(1))->isOne(); |
0 |
| 7612 |
ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ; |
0 |
7612 |
ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ; |
0 |
| 7613 |
break; |
0 |
7613 |
break; |
0 |
| 7614 |
} |
--- |
7614 |
} |
--- |
| 7615 |
case Intrinsic::vp_cttz: { |
0 |
7615 |
case Intrinsic::vp_cttz: { |
0 |
| 7616 |
bool IsZeroUndef = cast(VPIntrin.getArgOperand(1))->isOne(); |
0 |
7616 |
bool IsZeroUndef = cast(VPIntrin.getArgOperand(1))->isOne(); |
0 |
| 7617 |
ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ; |
0 |
7617 |
ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ; |
0 |
| 7618 |
break; |
0 |
7618 |
break; |
0 |
| 7619 |
} |
--- |
7619 |
} |
--- |
| 7620 |
#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \ |
--- |
7620 |
#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \ |
--- |
| 7621 |
case Intrinsic::VPID: \ |
--- |
7621 |
case Intrinsic::VPID: \ |
--- |
| 7622 |
ResOPC = ISD::VPSD; \ |
--- |
7622 |
ResOPC = ISD::VPSD; \ |
--- |
| 7623 |
break; |
--- |
7623 |
break; |
--- |
| 7624 |
#include "llvm/IR/VPIntrinsics.def" |
--- |
7624 |
#include "llvm/IR/VPIntrinsics.def" |
--- |
| 7625 |
} |
--- |
7625 |
} |
--- |
| 7626 |
|
--- |
7626 |
|
--- |
| 7627 |
if (!ResOPC) |
0 |
7627 |
if (!ResOPC) |
0 |
| 7628 |
llvm_unreachable( |
0 |
7628 |
llvm_unreachable( |
0 |
| 7629 |
"Inconsistency: no SDNode available for this VPIntrinsic!"); |
--- |
7629 |
"Inconsistency: no SDNode available for this VPIntrinsic!"); |
--- |
| 7630 |
|
--- |
7630 |
|
--- |
| 7631 |
if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD || |
0 |
7631 |
if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD || |
0 |
| 7632 |
*ResOPC == ISD::VP_REDUCE_SEQ_FMUL) { |
0 |
7632 |
*ResOPC == ISD::VP_REDUCE_SEQ_FMUL) { |
0 |
| 7633 |
if (VPIntrin.getFastMathFlags().allowReassoc()) |
0 |
7633 |
if (VPIntrin.getFastMathFlags().allowReassoc()) |
0 |
| 7634 |
return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD |
0 |
7634 |
return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD |
0 |
| 7635 |
: ISD::VP_REDUCE_FMUL; |
0 |
7635 |
: ISD::VP_REDUCE_FMUL; |
0 |
| 7636 |
} |
--- |
7636 |
} |
--- |
| 7637 |
|
--- |
7637 |
|
--- |
| 7638 |
return *ResOPC; |
0 |
7638 |
return *ResOPC; |
0 |
| 7639 |
} |
--- |
7639 |
} |
--- |
| 7640 |
|
--- |
7640 |
|
--- |
| 7641 |
void SelectionDAGBuilder::visitVPLoad( |
0 |
7641 |
void SelectionDAGBuilder::visitVPLoad( |
0 |
| 7642 |
const VPIntrinsic &VPIntrin, EVT VT, |
--- |
7642 |
const VPIntrinsic &VPIntrin, EVT VT, |
--- |
| 7643 |
const SmallVectorImpl &OpValues) { |
--- |
7643 |
const SmallVectorImpl &OpValues) { |
--- |
| 7644 |
SDLoc DL = getCurSDLoc(); |
0 |
7644 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7645 |
Value *PtrOperand = VPIntrin.getArgOperand(0); |
0 |
7645 |
Value *PtrOperand = VPIntrin.getArgOperand(0); |
0 |
| 7646 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
7646 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
| 7647 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
7647 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
| 7648 |
const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); |
0 |
7648 |
const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); |
0 |
| 7649 |
SDValue LD; |
0 |
7649 |
SDValue LD; |
0 |
| 7650 |
// Do not serialize variable-length loads of constant memory with |
--- |
7650 |
// Do not serialize variable-length loads of constant memory with |
--- |
| 7651 |
// anything. |
--- |
7651 |
// anything. |
--- |
| 7652 |
if (!Alignment) |
0 |
7652 |
if (!Alignment) |
0 |
| 7653 |
Alignment = DAG.getEVTAlign(VT); |
0 |
7653 |
Alignment = DAG.getEVTAlign(VT); |
0 |
| 7654 |
MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); |
0 |
7654 |
MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); |
0 |
| 7655 |
bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); |
0 |
7655 |
bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); |
0 |
| 7656 |
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); |
0 |
7656 |
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); |
0 |
| 7657 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
7657 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 7658 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, |
--- |
7658 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, |
--- |
| 7659 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
7659 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
| 7660 |
LD = DAG.getLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], OpValues[2], |
0 |
7660 |
LD = DAG.getLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], OpValues[2], |
0 |
| 7661 |
MMO, false /*IsExpanding */); |
--- |
7661 |
MMO, false /*IsExpanding */); |
--- |
| 7662 |
if (AddToChain) |
0 |
7662 |
if (AddToChain) |
0 |
| 7663 |
PendingLoads.push_back(LD.getValue(1)); |
0 |
7663 |
PendingLoads.push_back(LD.getValue(1)); |
0 |
| 7664 |
setValue(&VPIntrin, LD); |
0 |
7664 |
setValue(&VPIntrin, LD); |
0 |
| 7665 |
} |
0 |
7665 |
} |
0 |
| 7666 |
|
--- |
7666 |
|
--- |
| 7667 |
void SelectionDAGBuilder::visitVPGather( |
0 |
7667 |
void SelectionDAGBuilder::visitVPGather( |
0 |
| 7668 |
const VPIntrinsic &VPIntrin, EVT VT, |
--- |
7668 |
const VPIntrinsic &VPIntrin, EVT VT, |
--- |
| 7669 |
const SmallVectorImpl &OpValues) { |
--- |
7669 |
const SmallVectorImpl &OpValues) { |
--- |
| 7670 |
SDLoc DL = getCurSDLoc(); |
0 |
7670 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7671 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
7671 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 7672 |
Value *PtrOperand = VPIntrin.getArgOperand(0); |
0 |
7672 |
Value *PtrOperand = VPIntrin.getArgOperand(0); |
0 |
| 7673 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
7673 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
| 7674 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
7674 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
| 7675 |
const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); |
0 |
7675 |
const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); |
0 |
| 7676 |
SDValue LD; |
0 |
7676 |
SDValue LD; |
0 |
| 7677 |
if (!Alignment) |
0 |
7677 |
if (!Alignment) |
0 |
| 7678 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
7678 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
| 7679 |
unsigned AS = |
--- |
7679 |
unsigned AS = |
--- |
| 7680 |
PtrOperand->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
7680 |
PtrOperand->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
| 7681 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
7681 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 7682 |
MachinePointerInfo(AS), MachineMemOperand::MOLoad, |
--- |
7682 |
MachinePointerInfo(AS), MachineMemOperand::MOLoad, |
--- |
| 7683 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
7683 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
| 7684 |
SDValue Base, Index, Scale; |
0 |
7684 |
SDValue Base, Index, Scale; |
0 |
| 7685 |
ISD::MemIndexType IndexType; |
--- |
7685 |
ISD::MemIndexType IndexType; |
--- |
| 7686 |
bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale, |
0 |
7686 |
bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale, |
0 |
| 7687 |
this, VPIntrin.getParent(), |
--- |
7687 |
this, VPIntrin.getParent(), |
--- |
| 7688 |
VT.getScalarStoreSize()); |
--- |
7688 |
VT.getScalarStoreSize()); |
--- |
| 7689 |
if (!UniformBase) { |
0 |
7689 |
if (!UniformBase) { |
0 |
| 7690 |
Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
7690 |
Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 7691 |
Index = getValue(PtrOperand); |
0 |
7691 |
Index = getValue(PtrOperand); |
0 |
| 7692 |
IndexType = ISD::SIGNED_SCALED; |
0 |
7692 |
IndexType = ISD::SIGNED_SCALED; |
0 |
| 7693 |
Scale = DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
7693 |
Scale = DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 7694 |
} |
--- |
7694 |
} |
--- |
| 7695 |
EVT IdxVT = Index.getValueType(); |
0 |
7695 |
EVT IdxVT = Index.getValueType(); |
0 |
| 7696 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
7696 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
| 7697 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
7697 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
| 7698 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
7698 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
| 7699 |
Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); |
0 |
7699 |
Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); |
0 |
| 7700 |
} |
--- |
7700 |
} |
--- |
| 7701 |
LD = DAG.getGatherVP( |
0 |
7701 |
LD = DAG.getGatherVP( |
0 |
| 7702 |
DAG.getVTList(VT, MVT::Other), VT, DL, |
0 |
7702 |
DAG.getVTList(VT, MVT::Other), VT, DL, |
0 |
| 7703 |
{DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO, |
0 |
7703 |
{DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO, |
0 |
| 7704 |
IndexType); |
--- |
7704 |
IndexType); |
--- |
| 7705 |
PendingLoads.push_back(LD.getValue(1)); |
0 |
7705 |
PendingLoads.push_back(LD.getValue(1)); |
0 |
| 7706 |
setValue(&VPIntrin, LD); |
0 |
7706 |
setValue(&VPIntrin, LD); |
0 |
| 7707 |
} |
0 |
7707 |
} |
0 |
| 7708 |
|
--- |
7708 |
|
--- |
| 7709 |
void SelectionDAGBuilder::visitVPStore( |
0 |
7709 |
void SelectionDAGBuilder::visitVPStore( |
0 |
| 7710 |
const VPIntrinsic &VPIntrin, const SmallVectorImpl &OpValues) { |
--- |
7710 |
const VPIntrinsic &VPIntrin, const SmallVectorImpl &OpValues) { |
--- |
| 7711 |
SDLoc DL = getCurSDLoc(); |
0 |
7711 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7712 |
Value *PtrOperand = VPIntrin.getArgOperand(1); |
0 |
7712 |
Value *PtrOperand = VPIntrin.getArgOperand(1); |
0 |
| 7713 |
EVT VT = OpValues[0].getValueType(); |
0 |
7713 |
EVT VT = OpValues[0].getValueType(); |
0 |
| 7714 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
7714 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
| 7715 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
7715 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
| 7716 |
SDValue ST; |
0 |
7716 |
SDValue ST; |
0 |
| 7717 |
if (!Alignment) |
0 |
7717 |
if (!Alignment) |
0 |
| 7718 |
Alignment = DAG.getEVTAlign(VT); |
0 |
7718 |
Alignment = DAG.getEVTAlign(VT); |
0 |
| 7719 |
SDValue Ptr = OpValues[1]; |
0 |
7719 |
SDValue Ptr = OpValues[1]; |
0 |
| 7720 |
SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); |
0 |
7720 |
SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); |
0 |
| 7721 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
7721 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 7722 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, |
--- |
7722 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, |
--- |
| 7723 |
MemoryLocation::UnknownSize, *Alignment, AAInfo); |
0 |
7723 |
MemoryLocation::UnknownSize, *Alignment, AAInfo); |
0 |
| 7724 |
ST = DAG.getStoreVP(getMemoryRoot(), DL, OpValues[0], Ptr, Offset, |
0 |
7724 |
ST = DAG.getStoreVP(getMemoryRoot(), DL, OpValues[0], Ptr, Offset, |
0 |
| 7725 |
OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED, |
0 |
7725 |
OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED, |
0 |
| 7726 |
/* IsTruncating */ false, /*IsCompressing*/ false); |
--- |
7726 |
/* IsTruncating */ false, /*IsCompressing*/ false); |
--- |
| 7727 |
DAG.setRoot(ST); |
0 |
7727 |
DAG.setRoot(ST); |
0 |
| 7728 |
setValue(&VPIntrin, ST); |
0 |
7728 |
setValue(&VPIntrin, ST); |
0 |
| 7729 |
} |
0 |
7729 |
} |
0 |
| 7730 |
|
--- |
7730 |
|
--- |
| 7731 |
void SelectionDAGBuilder::visitVPScatter( |
0 |
7731 |
void SelectionDAGBuilder::visitVPScatter( |
0 |
| 7732 |
const VPIntrinsic &VPIntrin, const SmallVectorImpl &OpValues) { |
--- |
7732 |
const VPIntrinsic &VPIntrin, const SmallVectorImpl &OpValues) { |
--- |
| 7733 |
SDLoc DL = getCurSDLoc(); |
0 |
7733 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7734 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
7734 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 7735 |
Value *PtrOperand = VPIntrin.getArgOperand(1); |
0 |
7735 |
Value *PtrOperand = VPIntrin.getArgOperand(1); |
0 |
| 7736 |
EVT VT = OpValues[0].getValueType(); |
0 |
7736 |
EVT VT = OpValues[0].getValueType(); |
0 |
| 7737 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
7737 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
| 7738 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
7738 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
| 7739 |
SDValue ST; |
0 |
7739 |
SDValue ST; |
0 |
| 7740 |
if (!Alignment) |
0 |
7740 |
if (!Alignment) |
0 |
| 7741 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
7741 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
| 7742 |
unsigned AS = |
--- |
7742 |
unsigned AS = |
--- |
| 7743 |
PtrOperand->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
7743 |
PtrOperand->getType()->getScalarType()->getPointerAddressSpace(); |
0 |
| 7744 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
7744 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 7745 |
MachinePointerInfo(AS), MachineMemOperand::MOStore, |
--- |
7745 |
MachinePointerInfo(AS), MachineMemOperand::MOStore, |
--- |
| 7746 |
MemoryLocation::UnknownSize, *Alignment, AAInfo); |
0 |
7746 |
MemoryLocation::UnknownSize, *Alignment, AAInfo); |
0 |
| 7747 |
SDValue Base, Index, Scale; |
0 |
7747 |
SDValue Base, Index, Scale; |
0 |
| 7748 |
ISD::MemIndexType IndexType; |
--- |
7748 |
ISD::MemIndexType IndexType; |
--- |
| 7749 |
bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale, |
0 |
7749 |
bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale, |
0 |
| 7750 |
this, VPIntrin.getParent(), |
--- |
7750 |
this, VPIntrin.getParent(), |
--- |
| 7751 |
VT.getScalarStoreSize()); |
--- |
7751 |
VT.getScalarStoreSize()); |
--- |
| 7752 |
if (!UniformBase) { |
0 |
7752 |
if (!UniformBase) { |
0 |
| 7753 |
Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
7753 |
Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 7754 |
Index = getValue(PtrOperand); |
0 |
7754 |
Index = getValue(PtrOperand); |
0 |
| 7755 |
IndexType = ISD::SIGNED_SCALED; |
0 |
7755 |
IndexType = ISD::SIGNED_SCALED; |
0 |
| 7756 |
Scale = |
0 |
7756 |
Scale = |
0 |
| 7757 |
DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
7757 |
DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 7758 |
} |
--- |
7758 |
} |
--- |
| 7759 |
EVT IdxVT = Index.getValueType(); |
0 |
7759 |
EVT IdxVT = Index.getValueType(); |
0 |
| 7760 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
7760 |
EVT EltTy = IdxVT.getVectorElementType(); |
0 |
| 7761 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
7761 |
if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { |
0 |
| 7762 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
7762 |
EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); |
0 |
| 7763 |
Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); |
0 |
7763 |
Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); |
0 |
| 7764 |
} |
--- |
7764 |
} |
--- |
| 7765 |
ST = DAG.getScatterVP(DAG.getVTList(MVT::Other), VT, DL, |
0 |
7765 |
ST = DAG.getScatterVP(DAG.getVTList(MVT::Other), VT, DL, |
0 |
| 7766 |
{getMemoryRoot(), OpValues[0], Base, Index, Scale, |
0 |
7766 |
{getMemoryRoot(), OpValues[0], Base, Index, Scale, |
0 |
| 7767 |
OpValues[2], OpValues[3]}, |
0 |
7767 |
OpValues[2], OpValues[3]}, |
0 |
| 7768 |
MMO, IndexType); |
--- |
7768 |
MMO, IndexType); |
--- |
| 7769 |
DAG.setRoot(ST); |
0 |
7769 |
DAG.setRoot(ST); |
0 |
| 7770 |
setValue(&VPIntrin, ST); |
0 |
7770 |
setValue(&VPIntrin, ST); |
0 |
| 7771 |
} |
0 |
7771 |
} |
0 |
| 7772 |
|
--- |
7772 |
|
--- |
| 7773 |
void SelectionDAGBuilder::visitVPStridedLoad( |
0 |
7773 |
void SelectionDAGBuilder::visitVPStridedLoad( |
0 |
| 7774 |
const VPIntrinsic &VPIntrin, EVT VT, |
--- |
7774 |
const VPIntrinsic &VPIntrin, EVT VT, |
--- |
| 7775 |
const SmallVectorImpl &OpValues) { |
--- |
7775 |
const SmallVectorImpl &OpValues) { |
--- |
| 7776 |
SDLoc DL = getCurSDLoc(); |
0 |
7776 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7777 |
Value *PtrOperand = VPIntrin.getArgOperand(0); |
0 |
7777 |
Value *PtrOperand = VPIntrin.getArgOperand(0); |
0 |
| 7778 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
7778 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
| 7779 |
if (!Alignment) |
0 |
7779 |
if (!Alignment) |
0 |
| 7780 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
7780 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
| 7781 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
7781 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
| 7782 |
const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); |
0 |
7782 |
const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); |
0 |
| 7783 |
MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); |
0 |
7783 |
MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); |
0 |
| 7784 |
bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); |
0 |
7784 |
bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); |
0 |
| 7785 |
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); |
0 |
7785 |
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); |
0 |
| 7786 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
7786 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 7787 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, |
--- |
7787 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, |
--- |
| 7788 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
7788 |
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); |
0 |
| 7789 |
|
--- |
7789 |
|
--- |
| 7790 |
SDValue LD = DAG.getStridedLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], |
0 |
7790 |
SDValue LD = DAG.getStridedLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], |
0 |
| 7791 |
OpValues[2], OpValues[3], MMO, |
0 |
7791 |
OpValues[2], OpValues[3], MMO, |
0 |
| 7792 |
false /*IsExpanding*/); |
--- |
7792 |
false /*IsExpanding*/); |
--- |
| 7793 |
|
--- |
7793 |
|
--- |
| 7794 |
if (AddToChain) |
0 |
7794 |
if (AddToChain) |
0 |
| 7795 |
PendingLoads.push_back(LD.getValue(1)); |
0 |
7795 |
PendingLoads.push_back(LD.getValue(1)); |
0 |
| 7796 |
setValue(&VPIntrin, LD); |
0 |
7796 |
setValue(&VPIntrin, LD); |
0 |
| 7797 |
} |
0 |
7797 |
} |
0 |
| 7798 |
|
--- |
7798 |
|
--- |
| 7799 |
void SelectionDAGBuilder::visitVPStridedStore( |
0 |
7799 |
void SelectionDAGBuilder::visitVPStridedStore( |
0 |
| 7800 |
const VPIntrinsic &VPIntrin, const SmallVectorImpl &OpValues) { |
--- |
7800 |
const VPIntrinsic &VPIntrin, const SmallVectorImpl &OpValues) { |
--- |
| 7801 |
SDLoc DL = getCurSDLoc(); |
0 |
7801 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7802 |
Value *PtrOperand = VPIntrin.getArgOperand(1); |
0 |
7802 |
Value *PtrOperand = VPIntrin.getArgOperand(1); |
0 |
| 7803 |
EVT VT = OpValues[0].getValueType(); |
0 |
7803 |
EVT VT = OpValues[0].getValueType(); |
0 |
| 7804 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
7804 |
MaybeAlign Alignment = VPIntrin.getPointerAlignment(); |
0 |
| 7805 |
if (!Alignment) |
0 |
7805 |
if (!Alignment) |
0 |
| 7806 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
7806 |
Alignment = DAG.getEVTAlign(VT.getScalarType()); |
0 |
| 7807 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
7807 |
AAMDNodes AAInfo = VPIntrin.getAAMetadata(); |
0 |
| 7808 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
7808 |
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( |
0 |
| 7809 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, |
--- |
7809 |
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, |
--- |
| 7810 |
MemoryLocation::UnknownSize, *Alignment, AAInfo); |
0 |
7810 |
MemoryLocation::UnknownSize, *Alignment, AAInfo); |
0 |
| 7811 |
|
--- |
7811 |
|
--- |
| 7812 |
SDValue ST = DAG.getStridedStoreVP( |
0 |
7812 |
SDValue ST = DAG.getStridedStoreVP( |
0 |
| 7813 |
getMemoryRoot(), DL, OpValues[0], OpValues[1], |
0 |
7813 |
getMemoryRoot(), DL, OpValues[0], OpValues[1], |
0 |
| 7814 |
DAG.getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3], |
0 |
7814 |
DAG.getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3], |
0 |
| 7815 |
OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false, |
0 |
7815 |
OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false, |
0 |
| 7816 |
/*IsCompressing*/ false); |
--- |
7816 |
/*IsCompressing*/ false); |
--- |
| 7817 |
|
--- |
7817 |
|
--- |
| 7818 |
DAG.setRoot(ST); |
0 |
7818 |
DAG.setRoot(ST); |
0 |
| 7819 |
setValue(&VPIntrin, ST); |
0 |
7819 |
setValue(&VPIntrin, ST); |
0 |
| 7820 |
} |
0 |
7820 |
} |
0 |
| 7821 |
|
--- |
7821 |
|
--- |
| 7822 |
void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) { |
0 |
7822 |
void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) { |
0 |
| 7823 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
7823 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 7824 |
SDLoc DL = getCurSDLoc(); |
0 |
7824 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7825 |
|
--- |
7825 |
|
--- |
| 7826 |
ISD::CondCode Condition; |
--- |
7826 |
ISD::CondCode Condition; |
--- |
| 7827 |
CmpInst::Predicate CondCode = VPIntrin.getPredicate(); |
0 |
7827 |
CmpInst::Predicate CondCode = VPIntrin.getPredicate(); |
0 |
| 7828 |
bool IsFP = VPIntrin.getOperand(0)->getType()->isFPOrFPVectorTy(); |
0 |
7828 |
bool IsFP = VPIntrin.getOperand(0)->getType()->isFPOrFPVectorTy(); |
0 |
| 7829 |
if (IsFP) { |
0 |
7829 |
if (IsFP) { |
0 |
| 7830 |
// FIXME: Regular fcmps are FPMathOperators which may have fast-math (nnan) |
--- |
7830 |
// FIXME: Regular fcmps are FPMathOperators which may have fast-math (nnan) |
--- |
| 7831 |
// flags, but calls that don't return floating-point types can't be |
--- |
7831 |
// flags, but calls that don't return floating-point types can't be |
--- |
| 7832 |
// FPMathOperators, like vp.fcmp. This affects constrained fcmp too. |
--- |
7832 |
// FPMathOperators, like vp.fcmp. This affects constrained fcmp too. |
--- |
| 7833 |
Condition = getFCmpCondCode(CondCode); |
0 |
7833 |
Condition = getFCmpCondCode(CondCode); |
0 |
| 7834 |
if (TM.Options.NoNaNsFPMath) |
0 |
7834 |
if (TM.Options.NoNaNsFPMath) |
0 |
| 7835 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
7835 |
Condition = getFCmpCodeWithoutNaN(Condition); |
0 |
| 7836 |
} else { |
--- |
7836 |
} else { |
--- |
| 7837 |
Condition = getICmpCondCode(CondCode); |
0 |
7837 |
Condition = getICmpCondCode(CondCode); |
0 |
| 7838 |
} |
--- |
7838 |
} |
--- |
| 7839 |
|
--- |
7839 |
|
--- |
| 7840 |
SDValue Op1 = getValue(VPIntrin.getOperand(0)); |
0 |
7840 |
SDValue Op1 = getValue(VPIntrin.getOperand(0)); |
0 |
| 7841 |
SDValue Op2 = getValue(VPIntrin.getOperand(1)); |
0 |
7841 |
SDValue Op2 = getValue(VPIntrin.getOperand(1)); |
0 |
| 7842 |
// #2 is the condition code |
--- |
7842 |
// #2 is the condition code |
--- |
| 7843 |
SDValue MaskOp = getValue(VPIntrin.getOperand(3)); |
0 |
7843 |
SDValue MaskOp = getValue(VPIntrin.getOperand(3)); |
0 |
| 7844 |
SDValue EVL = getValue(VPIntrin.getOperand(4)); |
0 |
7844 |
SDValue EVL = getValue(VPIntrin.getOperand(4)); |
0 |
| 7845 |
MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy(); |
0 |
7845 |
MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy(); |
0 |
| 7846 |
assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && |
0 |
7846 |
assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && |
0 |
| 7847 |
"Unexpected target EVL type"); |
--- |
7847 |
"Unexpected target EVL type"); |
--- |
| 7848 |
EVL = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, EVL); |
0 |
7848 |
EVL = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, EVL); |
0 |
| 7849 |
|
--- |
7849 |
|
--- |
| 7850 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
7850 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 7851 |
VPIntrin.getType()); |
--- |
7851 |
VPIntrin.getType()); |
--- |
| 7852 |
setValue(&VPIntrin, |
0 |
7852 |
setValue(&VPIntrin, |
0 |
| 7853 |
DAG.getSetCCVP(DL, DestVT, Op1, Op2, Condition, MaskOp, EVL)); |
0 |
7853 |
DAG.getSetCCVP(DL, DestVT, Op1, Op2, Condition, MaskOp, EVL)); |
0 |
| 7854 |
} |
0 |
7854 |
} |
0 |
| 7855 |
|
--- |
7855 |
|
--- |
| 7856 |
void SelectionDAGBuilder::visitVectorPredicationIntrinsic( |
0 |
7856 |
void SelectionDAGBuilder::visitVectorPredicationIntrinsic( |
0 |
| 7857 |
const VPIntrinsic &VPIntrin) { |
--- |
7857 |
const VPIntrinsic &VPIntrin) { |
--- |
| 7858 |
SDLoc DL = getCurSDLoc(); |
0 |
7858 |
SDLoc DL = getCurSDLoc(); |
0 |
| 7859 |
unsigned Opcode = getISDForVPIntrinsic(VPIntrin); |
0 |
7859 |
unsigned Opcode = getISDForVPIntrinsic(VPIntrin); |
0 |
| 7860 |
|
--- |
7860 |
|
--- |
| 7861 |
auto IID = VPIntrin.getIntrinsicID(); |
0 |
7861 |
auto IID = VPIntrin.getIntrinsicID(); |
0 |
| 7862 |
|
--- |
7862 |
|
--- |
| 7863 |
if (const auto *CmpI = dyn_cast(&VPIntrin)) |
0 |
7863 |
if (const auto *CmpI = dyn_cast(&VPIntrin)) |
0 |
| 7864 |
return visitVPCmp(*CmpI); |
0 |
7864 |
return visitVPCmp(*CmpI); |
0 |
| 7865 |
|
--- |
7865 |
|
--- |
| 7866 |
SmallVector ValueVTs; |
0 |
7866 |
SmallVector ValueVTs; |
0 |
| 7867 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
7867 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 7868 |
ComputeValueVTs(TLI, DAG.getDataLayout(), VPIntrin.getType(), ValueVTs); |
0 |
7868 |
ComputeValueVTs(TLI, DAG.getDataLayout(), VPIntrin.getType(), ValueVTs); |
0 |
| 7869 |
SDVTList VTs = DAG.getVTList(ValueVTs); |
0 |
7869 |
SDVTList VTs = DAG.getVTList(ValueVTs); |
0 |
| 7870 |
|
--- |
7870 |
|
--- |
| 7871 |
auto EVLParamPos = VPIntrinsic::getVectorLengthParamPos(IID); |
0 |
7871 |
auto EVLParamPos = VPIntrinsic::getVectorLengthParamPos(IID); |
0 |
| 7872 |
|
--- |
7872 |
|
--- |
| 7873 |
MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy(); |
0 |
7873 |
MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy(); |
0 |
| 7874 |
assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && |
0 |
7874 |
assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && |
0 |
| 7875 |
"Unexpected target EVL type"); |
--- |
7875 |
"Unexpected target EVL type"); |
--- |
| 7876 |
|
--- |
7876 |
|
--- |
| 7877 |
// Request operands. |
--- |
7877 |
// Request operands. |
--- |
| 7878 |
SmallVector OpValues; |
0 |
7878 |
SmallVector OpValues; |
0 |
| 7879 |
for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) { |
0 |
7879 |
for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) { |
0 |
| 7880 |
auto Op = getValue(VPIntrin.getArgOperand(I)); |
0 |
7880 |
auto Op = getValue(VPIntrin.getArgOperand(I)); |
0 |
| 7881 |
if (I == EVLParamPos) |
0 |
7881 |
if (I == EVLParamPos) |
0 |
| 7882 |
Op = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, Op); |
0 |
7882 |
Op = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, Op); |
0 |
| 7883 |
OpValues.push_back(Op); |
0 |
7883 |
OpValues.push_back(Op); |
0 |
| 7884 |
} |
--- |
7884 |
} |
--- |
| 7885 |
|
--- |
7885 |
|
--- |
| 7886 |
switch (Opcode) { |
0 |
7886 |
switch (Opcode) { |
0 |
| 7887 |
default: { |
0 |
7887 |
default: { |
0 |
| 7888 |
SDNodeFlags SDFlags; |
0 |
7888 |
SDNodeFlags SDFlags; |
0 |
| 7889 |
if (auto *FPMO = dyn_cast(&VPIntrin)) |
0 |
7889 |
if (auto *FPMO = dyn_cast(&VPIntrin)) |
0 |
| 7890 |
SDFlags.copyFMF(*FPMO); |
0 |
7890 |
SDFlags.copyFMF(*FPMO); |
0 |
| 7891 |
SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues, SDFlags); |
0 |
7891 |
SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues, SDFlags); |
0 |
| 7892 |
setValue(&VPIntrin, Result); |
0 |
7892 |
setValue(&VPIntrin, Result); |
0 |
| 7893 |
break; |
0 |
7893 |
break; |
0 |
| 7894 |
} |
--- |
7894 |
} |
--- |
| 7895 |
case ISD::VP_LOAD: |
0 |
7895 |
case ISD::VP_LOAD: |
0 |
| 7896 |
visitVPLoad(VPIntrin, ValueVTs[0], OpValues); |
0 |
7896 |
visitVPLoad(VPIntrin, ValueVTs[0], OpValues); |
0 |
| 7897 |
break; |
0 |
7897 |
break; |
0 |
| 7898 |
case ISD::VP_GATHER: |
0 |
7898 |
case ISD::VP_GATHER: |
0 |
| 7899 |
visitVPGather(VPIntrin, ValueVTs[0], OpValues); |
0 |
7899 |
visitVPGather(VPIntrin, ValueVTs[0], OpValues); |
0 |
| 7900 |
break; |
0 |
7900 |
break; |
0 |
| 7901 |
case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: |
0 |
7901 |
case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: |
0 |
| 7902 |
visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues); |
0 |
7902 |
visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues); |
0 |
| 7903 |
break; |
0 |
7903 |
break; |
0 |
| 7904 |
case ISD::VP_STORE: |
0 |
7904 |
case ISD::VP_STORE: |
0 |
| 7905 |
visitVPStore(VPIntrin, OpValues); |
0 |
7905 |
visitVPStore(VPIntrin, OpValues); |
0 |
| 7906 |
break; |
0 |
7906 |
break; |
0 |
| 7907 |
case ISD::VP_SCATTER: |
0 |
7907 |
case ISD::VP_SCATTER: |
0 |
| 7908 |
visitVPScatter(VPIntrin, OpValues); |
0 |
7908 |
visitVPScatter(VPIntrin, OpValues); |
0 |
| 7909 |
break; |
0 |
7909 |
break; |
0 |
| 7910 |
case ISD::EXPERIMENTAL_VP_STRIDED_STORE: |
0 |
7910 |
case ISD::EXPERIMENTAL_VP_STRIDED_STORE: |
0 |
| 7911 |
visitVPStridedStore(VPIntrin, OpValues); |
0 |
7911 |
visitVPStridedStore(VPIntrin, OpValues); |
0 |
| 7912 |
break; |
0 |
7912 |
break; |
0 |
| 7913 |
case ISD::VP_FMULADD: { |
0 |
7913 |
case ISD::VP_FMULADD: { |
0 |
| 7914 |
assert(OpValues.size() == 5 && "Unexpected number of operands"); |
0 |
7914 |
assert(OpValues.size() == 5 && "Unexpected number of operands"); |
0 |
| 7915 |
SDNodeFlags SDFlags; |
0 |
7915 |
SDNodeFlags SDFlags; |
0 |
| 7916 |
if (auto *FPMO = dyn_cast(&VPIntrin)) |
0 |
7916 |
if (auto *FPMO = dyn_cast(&VPIntrin)) |
0 |
| 7917 |
SDFlags.copyFMF(*FPMO); |
0 |
7917 |
SDFlags.copyFMF(*FPMO); |
0 |
| 7918 |
if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && |
0 |
7918 |
if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && |
0 |
| 7919 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), ValueVTs[0])) { |
0 |
7919 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), ValueVTs[0])) { |
0 |
| 7920 |
setValue(&VPIntrin, DAG.getNode(ISD::VP_FMA, DL, VTs, OpValues, SDFlags)); |
0 |
7920 |
setValue(&VPIntrin, DAG.getNode(ISD::VP_FMA, DL, VTs, OpValues, SDFlags)); |
0 |
| 7921 |
} else { |
--- |
7921 |
} else { |
--- |
| 7922 |
SDValue Mul = DAG.getNode( |
0 |
7922 |
SDValue Mul = DAG.getNode( |
0 |
| 7923 |
ISD::VP_FMUL, DL, VTs, |
--- |
7923 |
ISD::VP_FMUL, DL, VTs, |
--- |
| 7924 |
{OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags); |
0 |
7924 |
{OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags); |
0 |
| 7925 |
SDValue Add = |
--- |
7925 |
SDValue Add = |
--- |
| 7926 |
DAG.getNode(ISD::VP_FADD, DL, VTs, |
0 |
7926 |
DAG.getNode(ISD::VP_FADD, DL, VTs, |
0 |
| 7927 |
{Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags); |
0 |
7927 |
{Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags); |
0 |
| 7928 |
setValue(&VPIntrin, Add); |
0 |
7928 |
setValue(&VPIntrin, Add); |
0 |
| 7929 |
} |
--- |
7929 |
} |
--- |
| 7930 |
break; |
0 |
7930 |
break; |
0 |
| 7931 |
} |
--- |
7931 |
} |
--- |
| 7932 |
case ISD::VP_INTTOPTR: { |
0 |
7932 |
case ISD::VP_INTTOPTR: { |
0 |
| 7933 |
SDValue N = OpValues[0]; |
0 |
7933 |
SDValue N = OpValues[0]; |
0 |
| 7934 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), VPIntrin.getType()); |
0 |
7934 |
EVT DestVT = TLI.getValueType(DAG.getDataLayout(), VPIntrin.getType()); |
0 |
| 7935 |
EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), VPIntrin.getType()); |
0 |
7935 |
EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), VPIntrin.getType()); |
0 |
| 7936 |
N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1], |
0 |
7936 |
N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1], |
0 |
| 7937 |
OpValues[2]); |
0 |
7937 |
OpValues[2]); |
0 |
| 7938 |
N = DAG.getVPZExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1], |
0 |
7938 |
N = DAG.getVPZExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1], |
0 |
| 7939 |
OpValues[2]); |
0 |
7939 |
OpValues[2]); |
0 |
| 7940 |
setValue(&VPIntrin, N); |
0 |
7940 |
setValue(&VPIntrin, N); |
0 |
| 7941 |
break; |
0 |
7941 |
break; |
0 |
| 7942 |
} |
--- |
7942 |
} |
--- |
| 7943 |
case ISD::VP_PTRTOINT: { |
0 |
7943 |
case ISD::VP_PTRTOINT: { |
0 |
| 7944 |
SDValue N = OpValues[0]; |
0 |
7944 |
SDValue N = OpValues[0]; |
0 |
| 7945 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
7945 |
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 7946 |
VPIntrin.getType()); |
--- |
7946 |
VPIntrin.getType()); |
--- |
| 7947 |
EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), |
0 |
7947 |
EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), |
0 |
| 7948 |
VPIntrin.getOperand(0)->getType()); |
--- |
7948 |
VPIntrin.getOperand(0)->getType()); |
--- |
| 7949 |
N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1], |
0 |
7949 |
N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1], |
0 |
| 7950 |
OpValues[2]); |
0 |
7950 |
OpValues[2]); |
0 |
| 7951 |
N = DAG.getVPZExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1], |
0 |
7951 |
N = DAG.getVPZExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1], |
0 |
| 7952 |
OpValues[2]); |
0 |
7952 |
OpValues[2]); |
0 |
| 7953 |
setValue(&VPIntrin, N); |
0 |
7953 |
setValue(&VPIntrin, N); |
0 |
| 7954 |
break; |
0 |
7954 |
break; |
0 |
| 7955 |
} |
--- |
7955 |
} |
--- |
| 7956 |
case ISD::VP_ABS: |
0 |
7956 |
case ISD::VP_ABS: |
0 |
| 7957 |
case ISD::VP_CTLZ: |
--- |
7957 |
case ISD::VP_CTLZ: |
--- |
| 7958 |
case ISD::VP_CTLZ_ZERO_UNDEF: |
--- |
7958 |
case ISD::VP_CTLZ_ZERO_UNDEF: |
--- |
| 7959 |
case ISD::VP_CTTZ: |
--- |
7959 |
case ISD::VP_CTTZ: |
--- |
| 7960 |
case ISD::VP_CTTZ_ZERO_UNDEF: { |
--- |
7960 |
case ISD::VP_CTTZ_ZERO_UNDEF: { |
--- |
| 7961 |
SDValue Result = |
--- |
7961 |
SDValue Result = |
--- |
| 7962 |
DAG.getNode(Opcode, DL, VTs, {OpValues[0], OpValues[2], OpValues[3]}); |
0 |
7962 |
DAG.getNode(Opcode, DL, VTs, {OpValues[0], OpValues[2], OpValues[3]}); |
0 |
| 7963 |
setValue(&VPIntrin, Result); |
0 |
7963 |
setValue(&VPIntrin, Result); |
0 |
| 7964 |
break; |
0 |
7964 |
break; |
0 |
| 7965 |
} |
--- |
7965 |
} |
--- |
| 7966 |
} |
--- |
7966 |
} |
--- |
| 7967 |
} |
0 |
7967 |
} |
0 |
| 7968 |
|
--- |
7968 |
|
--- |
| 7969 |
SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain, |
0 |
7969 |
SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain, |
0 |
| 7970 |
const BasicBlock *EHPadBB, |
--- |
7970 |
const BasicBlock *EHPadBB, |
--- |
| 7971 |
MCSymbol *&BeginLabel) { |
--- |
7971 |
MCSymbol *&BeginLabel) { |
--- |
| 7972 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
7972 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 7973 |
MachineModuleInfo &MMI = MF.getMMI(); |
0 |
7973 |
MachineModuleInfo &MMI = MF.getMMI(); |
0 |
| 7974 |
|
--- |
7974 |
|
--- |
| 7975 |
// Insert a label before the invoke call to mark the try range. This can be |
--- |
7975 |
// Insert a label before the invoke call to mark the try range. This can be |
--- |
| 7976 |
// used to detect deletion of the invoke via the MachineModuleInfo. |
--- |
7976 |
// used to detect deletion of the invoke via the MachineModuleInfo. |
--- |
| 7977 |
BeginLabel = MMI.getContext().createTempSymbol(); |
0 |
7977 |
BeginLabel = MMI.getContext().createTempSymbol(); |
0 |
| 7978 |
|
--- |
7978 |
|
--- |
| 7979 |
// For SjLj, keep track of which landing pads go with which invokes |
--- |
7979 |
// For SjLj, keep track of which landing pads go with which invokes |
--- |
| 7980 |
// so as to maintain the ordering of pads in the LSDA. |
--- |
7980 |
// so as to maintain the ordering of pads in the LSDA. |
--- |
| 7981 |
unsigned CallSiteIndex = MMI.getCurrentCallSite(); |
0 |
7981 |
unsigned CallSiteIndex = MMI.getCurrentCallSite(); |
0 |
| 7982 |
if (CallSiteIndex) { |
0 |
7982 |
if (CallSiteIndex) { |
0 |
| 7983 |
MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); |
0 |
7983 |
MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); |
0 |
| 7984 |
LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex); |
0 |
7984 |
LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex); |
0 |
| 7985 |
|
--- |
7985 |
|
--- |
| 7986 |
// Now that the call site is handled, stop tracking it. |
--- |
7986 |
// Now that the call site is handled, stop tracking it. |
--- |
| 7987 |
MMI.setCurrentCallSite(0); |
0 |
7987 |
MMI.setCurrentCallSite(0); |
0 |
| 7988 |
} |
--- |
7988 |
} |
--- |
| 7989 |
|
--- |
7989 |
|
--- |
| 7990 |
return DAG.getEHLabel(getCurSDLoc(), Chain, BeginLabel); |
0 |
7990 |
return DAG.getEHLabel(getCurSDLoc(), Chain, BeginLabel); |
0 |
| 7991 |
} |
--- |
7991 |
} |
--- |
| 7992 |
|
--- |
7992 |
|
--- |
| 7993 |
SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II, |
0 |
7993 |
SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II, |
0 |
| 7994 |
const BasicBlock *EHPadBB, |
--- |
7994 |
const BasicBlock *EHPadBB, |
--- |
| 7995 |
MCSymbol *BeginLabel) { |
--- |
7995 |
MCSymbol *BeginLabel) { |
--- |
| 7996 |
assert(BeginLabel && "BeginLabel should've been set"); |
0 |
7996 |
assert(BeginLabel && "BeginLabel should've been set"); |
0 |
| 7997 |
|
--- |
7997 |
|
--- |
| 7998 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
7998 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 7999 |
MachineModuleInfo &MMI = MF.getMMI(); |
0 |
7999 |
MachineModuleInfo &MMI = MF.getMMI(); |
0 |
| 8000 |
|
--- |
8000 |
|
--- |
| 8001 |
// Insert a label at the end of the invoke call to mark the try range. This |
--- |
8001 |
// Insert a label at the end of the invoke call to mark the try range. This |
--- |
| 8002 |
// can be used to detect deletion of the invoke via the MachineModuleInfo. |
--- |
8002 |
// can be used to detect deletion of the invoke via the MachineModuleInfo. |
--- |
| 8003 |
MCSymbol *EndLabel = MMI.getContext().createTempSymbol(); |
0 |
8003 |
MCSymbol *EndLabel = MMI.getContext().createTempSymbol(); |
0 |
| 8004 |
Chain = DAG.getEHLabel(getCurSDLoc(), Chain, EndLabel); |
0 |
8004 |
Chain = DAG.getEHLabel(getCurSDLoc(), Chain, EndLabel); |
0 |
| 8005 |
|
--- |
8005 |
|
--- |
| 8006 |
// Inform MachineModuleInfo of range. |
--- |
8006 |
// Inform MachineModuleInfo of range. |
--- |
| 8007 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
8007 |
auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); |
0 |
| 8008 |
// There is a platform (e.g. wasm) that uses funclet style IR but does not |
--- |
8008 |
// There is a platform (e.g. wasm) that uses funclet style IR but does not |
--- |
| 8009 |
// actually use outlined funclets and their LSDA info style. |
--- |
8009 |
// actually use outlined funclets and their LSDA info style. |
--- |
| 8010 |
if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) { |
0 |
8010 |
if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) { |
0 |
| 8011 |
assert(II && "II should've been set"); |
0 |
8011 |
assert(II && "II should've been set"); |
0 |
| 8012 |
WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo(); |
0 |
8012 |
WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo(); |
0 |
| 8013 |
EHInfo->addIPToStateRange(II, BeginLabel, EndLabel); |
0 |
8013 |
EHInfo->addIPToStateRange(II, BeginLabel, EndLabel); |
0 |
| 8014 |
} else if (!isScopedEHPersonality(Pers)) { |
0 |
8014 |
} else if (!isScopedEHPersonality(Pers)) { |
0 |
| 8015 |
assert(EHPadBB); |
0 |
8015 |
assert(EHPadBB); |
0 |
| 8016 |
MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel); |
0 |
8016 |
MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel); |
0 |
| 8017 |
} |
--- |
8017 |
} |
--- |
| 8018 |
|
--- |
8018 |
|
--- |
| 8019 |
return Chain; |
0 |
8019 |
return Chain; |
0 |
| 8020 |
} |
--- |
8020 |
} |
--- |
| 8021 |
|
--- |
8021 |
|
--- |
| 8022 |
std::pair |
--- |
8022 |
std::pair |
--- |
| 8023 |
SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, |
0 |
8023 |
SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, |
0 |
| 8024 |
const BasicBlock *EHPadBB) { |
--- |
8024 |
const BasicBlock *EHPadBB) { |
--- |
| 8025 |
MCSymbol *BeginLabel = nullptr; |
0 |
8025 |
MCSymbol *BeginLabel = nullptr; |
0 |
| 8026 |
|
--- |
8026 |
|
--- |
| 8027 |
if (EHPadBB) { |
0 |
8027 |
if (EHPadBB) { |
0 |
| 8028 |
// Both PendingLoads and PendingExports must be flushed here; |
--- |
8028 |
// Both PendingLoads and PendingExports must be flushed here; |
--- |
| 8029 |
// this call might not return. |
--- |
8029 |
// this call might not return. |
--- |
| 8030 |
(void)getRoot(); |
0 |
8030 |
(void)getRoot(); |
0 |
| 8031 |
DAG.setRoot(lowerStartEH(getControlRoot(), EHPadBB, BeginLabel)); |
0 |
8031 |
DAG.setRoot(lowerStartEH(getControlRoot(), EHPadBB, BeginLabel)); |
0 |
| 8032 |
CLI.setChain(getRoot()); |
0 |
8032 |
CLI.setChain(getRoot()); |
0 |
| 8033 |
} |
--- |
8033 |
} |
--- |
| 8034 |
|
--- |
8034 |
|
--- |
| 8035 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
8035 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 8036 |
std::pair Result = TLI.LowerCallTo(CLI); |
0 |
8036 |
std::pair Result = TLI.LowerCallTo(CLI); |
0 |
| 8037 |
|
--- |
8037 |
|
--- |
| 8038 |
assert((CLI.IsTailCall || Result.second.getNode()) && |
0 |
8038 |
assert((CLI.IsTailCall || Result.second.getNode()) && |
0 |
| 8039 |
"Non-null chain expected with non-tail call!"); |
--- |
8039 |
"Non-null chain expected with non-tail call!"); |
--- |
| 8040 |
assert((Result.second.getNode() || !Result.first.getNode()) && |
0 |
8040 |
assert((Result.second.getNode() || !Result.first.getNode()) && |
0 |
| 8041 |
"Null value expected with tail call!"); |
--- |
8041 |
"Null value expected with tail call!"); |
--- |
| 8042 |
|
--- |
8042 |
|
--- |
| 8043 |
if (!Result.second.getNode()) { |
0 |
8043 |
if (!Result.second.getNode()) { |
0 |
| 8044 |
// As a special case, a null chain means that a tail call has been emitted |
--- |
8044 |
// As a special case, a null chain means that a tail call has been emitted |
--- |
| 8045 |
// and the DAG root is already updated. |
--- |
8045 |
// and the DAG root is already updated. |
--- |
| 8046 |
HasTailCall = true; |
0 |
8046 |
HasTailCall = true; |
0 |
| 8047 |
|
--- |
8047 |
|
--- |
| 8048 |
// Since there's no actual continuation from this block, nothing can be |
--- |
8048 |
// Since there's no actual continuation from this block, nothing can be |
--- |
| 8049 |
// relying on us setting vregs for them. |
--- |
8049 |
// relying on us setting vregs for them. |
--- |
| 8050 |
PendingExports.clear(); |
0 |
8050 |
PendingExports.clear(); |
0 |
| 8051 |
} else { |
--- |
8051 |
} else { |
--- |
| 8052 |
DAG.setRoot(Result.second); |
0 |
8052 |
DAG.setRoot(Result.second); |
0 |
| 8053 |
} |
--- |
8053 |
} |
--- |
| 8054 |
|
--- |
8054 |
|
--- |
| 8055 |
if (EHPadBB) { |
0 |
8055 |
if (EHPadBB) { |
0 |
| 8056 |
DAG.setRoot(lowerEndEH(getRoot(), cast_or_null(CLI.CB), EHPadBB, |
0 |
8056 |
DAG.setRoot(lowerEndEH(getRoot(), cast_or_null(CLI.CB), EHPadBB, |
0 |
| 8057 |
BeginLabel)); |
--- |
8057 |
BeginLabel)); |
--- |
| 8058 |
} |
--- |
8058 |
} |
--- |
| 8059 |
|
--- |
8059 |
|
--- |
| 8060 |
return Result; |
0 |
8060 |
return Result; |
0 |
| 8061 |
} |
--- |
8061 |
} |
--- |
| 8062 |
|
--- |
8062 |
|
--- |
| 8063 |
void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee, |
0 |
8063 |
void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee, |
0 |
| 8064 |
bool isTailCall, |
--- |
8064 |
bool isTailCall, |
--- |
| 8065 |
bool isMustTailCall, |
--- |
8065 |
bool isMustTailCall, |
--- |
| 8066 |
const BasicBlock *EHPadBB) { |
--- |
8066 |
const BasicBlock *EHPadBB) { |
--- |
| 8067 |
auto &DL = DAG.getDataLayout(); |
0 |
8067 |
auto &DL = DAG.getDataLayout(); |
0 |
| 8068 |
FunctionType *FTy = CB.getFunctionType(); |
0 |
8068 |
FunctionType *FTy = CB.getFunctionType(); |
0 |
| 8069 |
Type *RetTy = CB.getType(); |
0 |
8069 |
Type *RetTy = CB.getType(); |
0 |
| 8070 |
|
--- |
8070 |
|
--- |
| 8071 |
TargetLowering::ArgListTy Args; |
0 |
8071 |
TargetLowering::ArgListTy Args; |
0 |
| 8072 |
Args.reserve(CB.arg_size()); |
0 |
8072 |
Args.reserve(CB.arg_size()); |
0 |
| 8073 |
|
--- |
8073 |
|
--- |
| 8074 |
const Value *SwiftErrorVal = nullptr; |
0 |
8074 |
const Value *SwiftErrorVal = nullptr; |
0 |
| 8075 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
8075 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 8076 |
|
--- |
8076 |
|
--- |
| 8077 |
if (isTailCall) { |
0 |
8077 |
if (isTailCall) { |
0 |
| 8078 |
// Avoid emitting tail calls in functions with the disable-tail-calls |
--- |
8078 |
// Avoid emitting tail calls in functions with the disable-tail-calls |
--- |
| 8079 |
// attribute. |
--- |
8079 |
// attribute. |
--- |
| 8080 |
auto *Caller = CB.getParent()->getParent(); |
0 |
8080 |
auto *Caller = CB.getParent()->getParent(); |
0 |
| 8081 |
if (Caller->getFnAttribute("disable-tail-calls").getValueAsString() == |
0 |
8081 |
if (Caller->getFnAttribute("disable-tail-calls").getValueAsString() == |
0 |
| 8082 |
"true" && !isMustTailCall) |
0 |
8082 |
"true" && !isMustTailCall) |
0 |
| 8083 |
isTailCall = false; |
0 |
8083 |
isTailCall = false; |
0 |
| 8084 |
|
--- |
8084 |
|
--- |
| 8085 |
// We can't tail call inside a function with a swifterror argument. Lowering |
--- |
8085 |
// We can't tail call inside a function with a swifterror argument. Lowering |
--- |
| 8086 |
// does not support this yet. It would have to move into the swifterror |
--- |
8086 |
// does not support this yet. It would have to move into the swifterror |
--- |
| 8087 |
// register before the call. |
--- |
8087 |
// register before the call. |
--- |
| 8088 |
if (TLI.supportSwiftError() && |
0 |
8088 |
if (TLI.supportSwiftError() && |
0 |
| 8089 |
Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) |
0 |
8089 |
Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) |
0 |
| 8090 |
isTailCall = false; |
0 |
8090 |
isTailCall = false; |
0 |
| 8091 |
} |
--- |
8091 |
} |
--- |
| 8092 |
|
--- |
8092 |
|
--- |
| 8093 |
for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) { |
0 |
8093 |
for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) { |
0 |
| 8094 |
TargetLowering::ArgListEntry Entry; |
0 |
8094 |
TargetLowering::ArgListEntry Entry; |
0 |
| 8095 |
const Value *V = *I; |
0 |
8095 |
const Value *V = *I; |
0 |
| 8096 |
|
--- |
8096 |
|
--- |
| 8097 |
// Skip empty types |
--- |
8097 |
// Skip empty types |
--- |
| 8098 |
if (V->getType()->isEmptyTy()) |
0 |
8098 |
if (V->getType()->isEmptyTy()) |
0 |
| 8099 |
continue; |
0 |
8099 |
continue; |
0 |
| 8100 |
|
--- |
8100 |
|
--- |
| 8101 |
SDValue ArgNode = getValue(V); |
0 |
8101 |
SDValue ArgNode = getValue(V); |
0 |
| 8102 |
Entry.Node = ArgNode; Entry.Ty = V->getType(); |
0 |
8102 |
Entry.Node = ArgNode; Entry.Ty = V->getType(); |
0 |
| 8103 |
|
--- |
8103 |
|
--- |
| 8104 |
Entry.setAttributes(&CB, I - CB.arg_begin()); |
0 |
8104 |
Entry.setAttributes(&CB, I - CB.arg_begin()); |
0 |
| 8105 |
|
--- |
8105 |
|
--- |
| 8106 |
// Use swifterror virtual register as input to the call. |
--- |
8106 |
// Use swifterror virtual register as input to the call. |
--- |
| 8107 |
if (Entry.IsSwiftError && TLI.supportSwiftError()) { |
0 |
8107 |
if (Entry.IsSwiftError && TLI.supportSwiftError()) { |
0 |
| 8108 |
SwiftErrorVal = V; |
0 |
8108 |
SwiftErrorVal = V; |
0 |
| 8109 |
// We find the virtual register for the actual swifterror argument. |
--- |
8109 |
// We find the virtual register for the actual swifterror argument. |
--- |
| 8110 |
// Instead of using the Value, we use the virtual register instead. |
--- |
8110 |
// Instead of using the Value, we use the virtual register instead. |
--- |
| 8111 |
Entry.Node = |
0 |
8111 |
Entry.Node = |
0 |
| 8112 |
DAG.getRegister(SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V), |
0 |
8112 |
DAG.getRegister(SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V), |
0 |
| 8113 |
EVT(TLI.getPointerTy(DL))); |
0 |
8113 |
EVT(TLI.getPointerTy(DL))); |
0 |
| 8114 |
} |
--- |
8114 |
} |
--- |
| 8115 |
|
--- |
8115 |
|
--- |
| 8116 |
Args.push_back(Entry); |
0 |
8116 |
Args.push_back(Entry); |
0 |
| 8117 |
|
--- |
8117 |
|
--- |
| 8118 |
// If we have an explicit sret argument that is an Instruction, (i.e., it |
--- |
8118 |
// If we have an explicit sret argument that is an Instruction, (i.e., it |
--- |
| 8119 |
// might point to function-local memory), we can't meaningfully tail-call. |
--- |
8119 |
// might point to function-local memory), we can't meaningfully tail-call. |
--- |
| 8120 |
if (Entry.IsSRet && isa(V)) |
0 |
8120 |
if (Entry.IsSRet && isa(V)) |
0 |
| 8121 |
isTailCall = false; |
0 |
8121 |
isTailCall = false; |
0 |
| 8122 |
} |
--- |
8122 |
} |
--- |
| 8123 |
|
--- |
8123 |
|
--- |
| 8124 |
// If call site has a cfguardtarget operand bundle, create and add an |
--- |
8124 |
// If call site has a cfguardtarget operand bundle, create and add an |
--- |
| 8125 |
// additional ArgListEntry. |
--- |
8125 |
// additional ArgListEntry. |
--- |
| 8126 |
if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_cfguardtarget)) { |
0 |
8126 |
if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_cfguardtarget)) { |
0 |
| 8127 |
TargetLowering::ArgListEntry Entry; |
0 |
8127 |
TargetLowering::ArgListEntry Entry; |
0 |
| 8128 |
Value *V = Bundle->Inputs[0]; |
0 |
8128 |
Value *V = Bundle->Inputs[0]; |
0 |
| 8129 |
SDValue ArgNode = getValue(V); |
0 |
8129 |
SDValue ArgNode = getValue(V); |
0 |
| 8130 |
Entry.Node = ArgNode; |
0 |
8130 |
Entry.Node = ArgNode; |
0 |
| 8131 |
Entry.Ty = V->getType(); |
0 |
8131 |
Entry.Ty = V->getType(); |
0 |
| 8132 |
Entry.IsCFGuardTarget = true; |
0 |
8132 |
Entry.IsCFGuardTarget = true; |
0 |
| 8133 |
Args.push_back(Entry); |
0 |
8133 |
Args.push_back(Entry); |
0 |
| 8134 |
} |
--- |
8134 |
} |
--- |
| 8135 |
|
--- |
8135 |
|
--- |
| 8136 |
// Check if target-independent constraints permit a tail call here. |
--- |
8136 |
// Check if target-independent constraints permit a tail call here. |
--- |
| 8137 |
// Target-dependent constraints are checked within TLI->LowerCallTo. |
--- |
8137 |
// Target-dependent constraints are checked within TLI->LowerCallTo. |
--- |
| 8138 |
if (isTailCall && !isInTailCallPosition(CB, DAG.getTarget())) |
0 |
8138 |
if (isTailCall && !isInTailCallPosition(CB, DAG.getTarget())) |
0 |
| 8139 |
isTailCall = false; |
0 |
8139 |
isTailCall = false; |
0 |
| 8140 |
|
--- |
8140 |
|
--- |
| 8141 |
// Disable tail calls if there is an swifterror argument. Targets have not |
--- |
8141 |
// Disable tail calls if there is an swifterror argument. Targets have not |
--- |
| 8142 |
// been updated to support tail calls. |
--- |
8142 |
// been updated to support tail calls. |
--- |
| 8143 |
if (TLI.supportSwiftError() && SwiftErrorVal) |
0 |
8143 |
if (TLI.supportSwiftError() && SwiftErrorVal) |
0 |
| 8144 |
isTailCall = false; |
0 |
8144 |
isTailCall = false; |
0 |
| 8145 |
|
--- |
8145 |
|
--- |
| 8146 |
ConstantInt *CFIType = nullptr; |
0 |
8146 |
ConstantInt *CFIType = nullptr; |
0 |
| 8147 |
if (CB.isIndirectCall()) { |
0 |
8147 |
if (CB.isIndirectCall()) { |
0 |
| 8148 |
if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_kcfi)) { |
0 |
8148 |
if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_kcfi)) { |
0 |
| 8149 |
if (!TLI.supportKCFIBundles()) |
0 |
8149 |
if (!TLI.supportKCFIBundles()) |
0 |
| 8150 |
report_fatal_error( |
0 |
8150 |
report_fatal_error( |
0 |
| 8151 |
"Target doesn't support calls with kcfi operand bundles."); |
--- |
8151 |
"Target doesn't support calls with kcfi operand bundles."); |
--- |
| 8152 |
CFIType = cast(Bundle->Inputs[0]); |
0 |
8152 |
CFIType = cast(Bundle->Inputs[0]); |
0 |
| 8153 |
assert(CFIType->getType()->isIntegerTy(32) && "Invalid CFI type"); |
0 |
8153 |
assert(CFIType->getType()->isIntegerTy(32) && "Invalid CFI type"); |
0 |
| 8154 |
} |
--- |
8154 |
} |
--- |
| 8155 |
} |
--- |
8155 |
} |
--- |
| 8156 |
|
--- |
8156 |
|
--- |
| 8157 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
8157 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
| 8158 |
CLI.setDebugLoc(getCurSDLoc()) |
0 |
8158 |
CLI.setDebugLoc(getCurSDLoc()) |
0 |
| 8159 |
.setChain(getRoot()) |
0 |
8159 |
.setChain(getRoot()) |
0 |
| 8160 |
.setCallee(RetTy, FTy, Callee, std::move(Args), CB) |
0 |
8160 |
.setCallee(RetTy, FTy, Callee, std::move(Args), CB) |
0 |
| 8161 |
.setTailCall(isTailCall) |
0 |
8161 |
.setTailCall(isTailCall) |
0 |
| 8162 |
.setConvergent(CB.isConvergent()) |
0 |
8162 |
.setConvergent(CB.isConvergent()) |
0 |
| 8163 |
.setIsPreallocated( |
0 |
8163 |
.setIsPreallocated( |
0 |
| 8164 |
CB.countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0) |
0 |
8164 |
CB.countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0) |
0 |
| 8165 |
.setCFIType(CFIType); |
0 |
8165 |
.setCFIType(CFIType); |
0 |
| 8166 |
std::pair Result = lowerInvokable(CLI, EHPadBB); |
0 |
8166 |
std::pair Result = lowerInvokable(CLI, EHPadBB); |
0 |
| 8167 |
|
--- |
8167 |
|
--- |
| 8168 |
if (Result.first.getNode()) { |
0 |
8168 |
if (Result.first.getNode()) { |
0 |
| 8169 |
Result.first = lowerRangeToAssertZExt(DAG, CB, Result.first); |
0 |
8169 |
Result.first = lowerRangeToAssertZExt(DAG, CB, Result.first); |
0 |
| 8170 |
setValue(&CB, Result.first); |
0 |
8170 |
setValue(&CB, Result.first); |
0 |
| 8171 |
} |
--- |
8171 |
} |
--- |
| 8172 |
|
--- |
8172 |
|
--- |
| 8173 |
// The last element of CLI.InVals has the SDValue for swifterror return. |
--- |
8173 |
// The last element of CLI.InVals has the SDValue for swifterror return. |
--- |
| 8174 |
// Here we copy it to a virtual register and update SwiftErrorMap for |
--- |
8174 |
// Here we copy it to a virtual register and update SwiftErrorMap for |
--- |
| 8175 |
// book-keeping. |
--- |
8175 |
// book-keeping. |
--- |
| 8176 |
if (SwiftErrorVal && TLI.supportSwiftError()) { |
0 |
8176 |
if (SwiftErrorVal && TLI.supportSwiftError()) { |
0 |
| 8177 |
// Get the last element of InVals. |
--- |
8177 |
// Get the last element of InVals. |
--- |
| 8178 |
SDValue Src = CLI.InVals.back(); |
0 |
8178 |
SDValue Src = CLI.InVals.back(); |
0 |
| 8179 |
Register VReg = |
--- |
8179 |
Register VReg = |
--- |
| 8180 |
SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal); |
0 |
8180 |
SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal); |
0 |
| 8181 |
SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src); |
0 |
8181 |
SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src); |
0 |
| 8182 |
DAG.setRoot(CopyNode); |
0 |
8182 |
DAG.setRoot(CopyNode); |
0 |
| 8183 |
} |
--- |
8183 |
} |
--- |
| 8184 |
} |
0 |
8184 |
} |
0 |
| 8185 |
|
--- |
8185 |
|
--- |
| 8186 |
static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, |
0 |
8186 |
static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, |
0 |
| 8187 |
SelectionDAGBuilder &Builder) { |
--- |
8187 |
SelectionDAGBuilder &Builder) { |
--- |
| 8188 |
// Check to see if this load can be trivially constant folded, e.g. if the |
--- |
8188 |
// Check to see if this load can be trivially constant folded, e.g. if the |
--- |
| 8189 |
// input is from a string literal. |
--- |
8189 |
// input is from a string literal. |
--- |
| 8190 |
if (const Constant *LoadInput = dyn_cast(PtrVal)) { |
0 |
8190 |
if (const Constant *LoadInput = dyn_cast(PtrVal)) { |
0 |
| 8191 |
// Cast pointer to the type we really want to load. |
--- |
8191 |
// Cast pointer to the type we really want to load. |
--- |
| 8192 |
Type *LoadTy = |
--- |
8192 |
Type *LoadTy = |
--- |
| 8193 |
Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); |
0 |
8193 |
Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); |
0 |
| 8194 |
if (LoadVT.isVector()) |
0 |
8194 |
if (LoadVT.isVector()) |
0 |
| 8195 |
LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements()); |
0 |
8195 |
LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements()); |
0 |
| 8196 |
|
--- |
8196 |
|
--- |
| 8197 |
LoadInput = ConstantExpr::getBitCast(const_cast(LoadInput), |
0 |
8197 |
LoadInput = ConstantExpr::getBitCast(const_cast(LoadInput), |
0 |
| 8198 |
PointerType::getUnqual(LoadTy)); |
0 |
8198 |
PointerType::getUnqual(LoadTy)); |
0 |
| 8199 |
|
--- |
8199 |
|
--- |
| 8200 |
if (const Constant *LoadCst = |
0 |
8200 |
if (const Constant *LoadCst = |
0 |
| 8201 |
ConstantFoldLoadFromConstPtr(const_cast(LoadInput), |
0 |
8201 |
ConstantFoldLoadFromConstPtr(const_cast(LoadInput), |
0 |
| 8202 |
LoadTy, Builder.DAG.getDataLayout())) |
0 |
8202 |
LoadTy, Builder.DAG.getDataLayout())) |
0 |
| 8203 |
return Builder.getValue(LoadCst); |
0 |
8203 |
return Builder.getValue(LoadCst); |
0 |
| 8204 |
} |
--- |
8204 |
} |
--- |
| 8205 |
|
--- |
8205 |
|
--- |
| 8206 |
// Otherwise, we have to emit the load. If the pointer is to unfoldable but |
--- |
8206 |
// Otherwise, we have to emit the load. If the pointer is to unfoldable but |
--- |
| 8207 |
// still constant memory, the input chain can be the entry node. |
--- |
8207 |
// still constant memory, the input chain can be the entry node. |
--- |
| 8208 |
SDValue Root; |
0 |
8208 |
SDValue Root; |
0 |
| 8209 |
bool ConstantMemory = false; |
0 |
8209 |
bool ConstantMemory = false; |
0 |
| 8210 |
|
--- |
8210 |
|
--- |
| 8211 |
// Do not serialize (non-volatile) loads of constant memory with anything. |
--- |
8211 |
// Do not serialize (non-volatile) loads of constant memory with anything. |
--- |
| 8212 |
if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) { |
0 |
8212 |
if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) { |
0 |
| 8213 |
Root = Builder.DAG.getEntryNode(); |
0 |
8213 |
Root = Builder.DAG.getEntryNode(); |
0 |
| 8214 |
ConstantMemory = true; |
0 |
8214 |
ConstantMemory = true; |
0 |
| 8215 |
} else { |
--- |
8215 |
} else { |
--- |
| 8216 |
// Do not serialize non-volatile loads against each other. |
--- |
8216 |
// Do not serialize non-volatile loads against each other. |
--- |
| 8217 |
Root = Builder.DAG.getRoot(); |
0 |
8217 |
Root = Builder.DAG.getRoot(); |
0 |
| 8218 |
} |
--- |
8218 |
} |
--- |
| 8219 |
|
--- |
8219 |
|
--- |
| 8220 |
SDValue Ptr = Builder.getValue(PtrVal); |
0 |
8220 |
SDValue Ptr = Builder.getValue(PtrVal); |
0 |
| 8221 |
SDValue LoadVal = |
--- |
8221 |
SDValue LoadVal = |
--- |
| 8222 |
Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, |
0 |
8222 |
Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, |
0 |
| 8223 |
MachinePointerInfo(PtrVal), Align(1)); |
--- |
8223 |
MachinePointerInfo(PtrVal), Align(1)); |
--- |
| 8224 |
|
--- |
8224 |
|
--- |
| 8225 |
if (!ConstantMemory) |
0 |
8225 |
if (!ConstantMemory) |
0 |
| 8226 |
Builder.PendingLoads.push_back(LoadVal.getValue(1)); |
0 |
8226 |
Builder.PendingLoads.push_back(LoadVal.getValue(1)); |
0 |
| 8227 |
return LoadVal; |
0 |
8227 |
return LoadVal; |
0 |
| 8228 |
} |
--- |
8228 |
} |
--- |
| 8229 |
|
--- |
8229 |
|
--- |
| 8230 |
/// Record the value for an instruction that produces an integer result, |
--- |
8230 |
/// Record the value for an instruction that produces an integer result, |
--- |
| 8231 |
/// converting the type where necessary. |
--- |
8231 |
/// converting the type where necessary. |
--- |
| 8232 |
void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I, |
0 |
8232 |
void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I, |
0 |
| 8233 |
SDValue Value, |
--- |
8233 |
SDValue Value, |
--- |
| 8234 |
bool IsSigned) { |
--- |
8234 |
bool IsSigned) { |
--- |
| 8235 |
EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
8235 |
EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 8236 |
I.getType(), true); |
--- |
8236 |
I.getType(), true); |
--- |
| 8237 |
Value = DAG.getExtOrTrunc(IsSigned, Value, getCurSDLoc(), VT); |
0 |
8237 |
Value = DAG.getExtOrTrunc(IsSigned, Value, getCurSDLoc(), VT); |
0 |
| 8238 |
setValue(&I, Value); |
0 |
8238 |
setValue(&I, Value); |
0 |
| 8239 |
} |
0 |
8239 |
} |
0 |
| 8240 |
|
--- |
8240 |
|
--- |
| 8241 |
/// See if we can lower a memcmp/bcmp call into an optimized form. If so, return |
--- |
8241 |
/// See if we can lower a memcmp/bcmp call into an optimized form. If so, return |
--- |
| 8242 |
/// true and lower it. Otherwise return false, and it will be lowered like a |
--- |
8242 |
/// true and lower it. Otherwise return false, and it will be lowered like a |
--- |
| 8243 |
/// normal call. |
--- |
8243 |
/// normal call. |
--- |
| 8244 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8244 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8245 |
/// correct prototype. |
--- |
8245 |
/// correct prototype. |
--- |
| 8246 |
bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) { |
0 |
8246 |
bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) { |
0 |
| 8247 |
const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); |
0 |
8247 |
const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); |
0 |
| 8248 |
const Value *Size = I.getArgOperand(2); |
0 |
8248 |
const Value *Size = I.getArgOperand(2); |
0 |
| 8249 |
const ConstantSDNode *CSize = dyn_cast(getValue(Size)); |
0 |
8249 |
const ConstantSDNode *CSize = dyn_cast(getValue(Size)); |
0 |
| 8250 |
if (CSize && CSize->getZExtValue() == 0) { |
0 |
8250 |
if (CSize && CSize->getZExtValue() == 0) { |
0 |
| 8251 |
EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
8251 |
EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), |
0 |
| 8252 |
I.getType(), true); |
--- |
8252 |
I.getType(), true); |
--- |
| 8253 |
setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT)); |
0 |
8253 |
setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT)); |
0 |
| 8254 |
return true; |
0 |
8254 |
return true; |
0 |
| 8255 |
} |
--- |
8255 |
} |
--- |
| 8256 |
|
--- |
8256 |
|
--- |
| 8257 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
8257 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 8258 |
std::pair Res = TSI.EmitTargetCodeForMemcmp( |
0 |
8258 |
std::pair Res = TSI.EmitTargetCodeForMemcmp( |
0 |
| 8259 |
DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS), |
0 |
8259 |
DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS), |
0 |
| 8260 |
getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS)); |
--- |
8260 |
getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS)); |
--- |
| 8261 |
if (Res.first.getNode()) { |
0 |
8261 |
if (Res.first.getNode()) { |
0 |
| 8262 |
processIntegerCallValue(I, Res.first, true); |
0 |
8262 |
processIntegerCallValue(I, Res.first, true); |
0 |
| 8263 |
PendingLoads.push_back(Res.second); |
0 |
8263 |
PendingLoads.push_back(Res.second); |
0 |
| 8264 |
return true; |
0 |
8264 |
return true; |
0 |
| 8265 |
} |
--- |
8265 |
} |
--- |
| 8266 |
|
--- |
8266 |
|
--- |
| 8267 |
// memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 |
--- |
8267 |
// memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 |
--- |
| 8268 |
// memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 |
--- |
8268 |
// memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 |
--- |
| 8269 |
if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I)) |
0 |
8269 |
if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I)) |
0 |
| 8270 |
return false; |
0 |
8270 |
return false; |
0 |
| 8271 |
|
--- |
8271 |
|
--- |
| 8272 |
// If the target has a fast compare for the given size, it will return a |
--- |
8272 |
// If the target has a fast compare for the given size, it will return a |
--- |
| 8273 |
// preferred load type for that size. Require that the load VT is legal and |
--- |
8273 |
// preferred load type for that size. Require that the load VT is legal and |
--- |
| 8274 |
// that the target supports unaligned loads of that type. Otherwise, return |
--- |
8274 |
// that the target supports unaligned loads of that type. Otherwise, return |
--- |
| 8275 |
// INVALID. |
--- |
8275 |
// INVALID. |
--- |
| 8276 |
auto hasFastLoadsAndCompare = [&](unsigned NumBits) { |
0 |
8276 |
auto hasFastLoadsAndCompare = [&](unsigned NumBits) { |
0 |
| 8277 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
8277 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 8278 |
MVT LVT = TLI.hasFastEqualityCompare(NumBits); |
0 |
8278 |
MVT LVT = TLI.hasFastEqualityCompare(NumBits); |
0 |
| 8279 |
if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) { |
0 |
8279 |
if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) { |
0 |
| 8280 |
// TODO: Handle 5 byte compare as 4-byte + 1 byte. |
--- |
8280 |
// TODO: Handle 5 byte compare as 4-byte + 1 byte. |
--- |
| 8281 |
// TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. |
--- |
8281 |
// TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. |
--- |
| 8282 |
// TODO: Check alignment of src and dest ptrs. |
--- |
8282 |
// TODO: Check alignment of src and dest ptrs. |
--- |
| 8283 |
unsigned DstAS = LHS->getType()->getPointerAddressSpace(); |
0 |
8283 |
unsigned DstAS = LHS->getType()->getPointerAddressSpace(); |
0 |
| 8284 |
unsigned SrcAS = RHS->getType()->getPointerAddressSpace(); |
0 |
8284 |
unsigned SrcAS = RHS->getType()->getPointerAddressSpace(); |
0 |
| 8285 |
if (!TLI.isTypeLegal(LVT) || |
0 |
8285 |
if (!TLI.isTypeLegal(LVT) || |
0 |
| 8286 |
!TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) || |
0 |
8286 |
!TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) || |
0 |
| 8287 |
!TLI.allowsMisalignedMemoryAccesses(LVT, DstAS)) |
0 |
8287 |
!TLI.allowsMisalignedMemoryAccesses(LVT, DstAS)) |
0 |
| 8288 |
LVT = MVT::INVALID_SIMPLE_VALUE_TYPE; |
0 |
8288 |
LVT = MVT::INVALID_SIMPLE_VALUE_TYPE; |
0 |
| 8289 |
} |
--- |
8289 |
} |
--- |
| 8290 |
|
--- |
8290 |
|
--- |
| 8291 |
return LVT; |
0 |
8291 |
return LVT; |
0 |
| 8292 |
}; |
0 |
8292 |
}; |
0 |
| 8293 |
|
--- |
8293 |
|
--- |
| 8294 |
// This turns into unaligned loads. We only do this if the target natively |
--- |
8294 |
// This turns into unaligned loads. We only do this if the target natively |
--- |
| 8295 |
// supports the MVT we'll be loading or if it is small enough (<= 4) that |
--- |
8295 |
// supports the MVT we'll be loading or if it is small enough (<= 4) that |
--- |
| 8296 |
// we'll only produce a small number of byte loads. |
--- |
8296 |
// we'll only produce a small number of byte loads. |
--- |
| 8297 |
MVT LoadVT; |
0 |
8297 |
MVT LoadVT; |
0 |
| 8298 |
unsigned NumBitsToCompare = CSize->getZExtValue() * 8; |
0 |
8298 |
unsigned NumBitsToCompare = CSize->getZExtValue() * 8; |
0 |
| 8299 |
switch (NumBitsToCompare) { |
0 |
8299 |
switch (NumBitsToCompare) { |
0 |
| 8300 |
default: |
0 |
8300 |
default: |
0 |
| 8301 |
return false; |
0 |
8301 |
return false; |
0 |
| 8302 |
case 16: |
0 |
8302 |
case 16: |
0 |
| 8303 |
LoadVT = MVT::i16; |
0 |
8303 |
LoadVT = MVT::i16; |
0 |
| 8304 |
break; |
0 |
8304 |
break; |
0 |
| 8305 |
case 32: |
0 |
8305 |
case 32: |
0 |
| 8306 |
LoadVT = MVT::i32; |
0 |
8306 |
LoadVT = MVT::i32; |
0 |
| 8307 |
break; |
0 |
8307 |
break; |
0 |
| 8308 |
case 64: |
0 |
8308 |
case 64: |
0 |
| 8309 |
case 128: |
--- |
8309 |
case 128: |
--- |
| 8310 |
case 256: |
--- |
8310 |
case 256: |
--- |
| 8311 |
LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); |
0 |
8311 |
LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); |
0 |
| 8312 |
break; |
0 |
8312 |
break; |
0 |
| 8313 |
} |
--- |
8313 |
} |
--- |
| 8314 |
|
--- |
8314 |
|
--- |
| 8315 |
if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) |
0 |
8315 |
if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) |
0 |
| 8316 |
return false; |
0 |
8316 |
return false; |
0 |
| 8317 |
|
--- |
8317 |
|
--- |
| 8318 |
SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); |
0 |
8318 |
SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); |
0 |
| 8319 |
SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); |
0 |
8319 |
SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); |
0 |
| 8320 |
|
--- |
8320 |
|
--- |
| 8321 |
// Bitcast to a wide integer type if the loads are vectors. |
--- |
8321 |
// Bitcast to a wide integer type if the loads are vectors. |
--- |
| 8322 |
if (LoadVT.isVector()) { |
0 |
8322 |
if (LoadVT.isVector()) { |
0 |
| 8323 |
EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits()); |
0 |
8323 |
EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits()); |
0 |
| 8324 |
LoadL = DAG.getBitcast(CmpVT, LoadL); |
0 |
8324 |
LoadL = DAG.getBitcast(CmpVT, LoadL); |
0 |
| 8325 |
LoadR = DAG.getBitcast(CmpVT, LoadR); |
0 |
8325 |
LoadR = DAG.getBitcast(CmpVT, LoadR); |
0 |
| 8326 |
} |
--- |
8326 |
} |
--- |
| 8327 |
|
--- |
8327 |
|
--- |
| 8328 |
SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE); |
0 |
8328 |
SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE); |
0 |
| 8329 |
processIntegerCallValue(I, Cmp, false); |
0 |
8329 |
processIntegerCallValue(I, Cmp, false); |
0 |
| 8330 |
return true; |
0 |
8330 |
return true; |
0 |
| 8331 |
} |
--- |
8331 |
} |
--- |
| 8332 |
|
--- |
8332 |
|
--- |
| 8333 |
/// See if we can lower a memchr call into an optimized form. If so, return |
--- |
8333 |
/// See if we can lower a memchr call into an optimized form. If so, return |
--- |
| 8334 |
/// true and lower it. Otherwise return false, and it will be lowered like a |
--- |
8334 |
/// true and lower it. Otherwise return false, and it will be lowered like a |
--- |
| 8335 |
/// normal call. |
--- |
8335 |
/// normal call. |
--- |
| 8336 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8336 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8337 |
/// correct prototype. |
--- |
8337 |
/// correct prototype. |
--- |
| 8338 |
bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) { |
0 |
8338 |
bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) { |
0 |
| 8339 |
const Value *Src = I.getArgOperand(0); |
0 |
8339 |
const Value *Src = I.getArgOperand(0); |
0 |
| 8340 |
const Value *Char = I.getArgOperand(1); |
0 |
8340 |
const Value *Char = I.getArgOperand(1); |
0 |
| 8341 |
const Value *Length = I.getArgOperand(2); |
0 |
8341 |
const Value *Length = I.getArgOperand(2); |
0 |
| 8342 |
|
--- |
8342 |
|
--- |
| 8343 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
8343 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 8344 |
std::pair Res = |
--- |
8344 |
std::pair Res = |
--- |
| 8345 |
TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
8345 |
TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
| 8346 |
getValue(Src), getValue(Char), getValue(Length), |
--- |
8346 |
getValue(Src), getValue(Char), getValue(Length), |
--- |
| 8347 |
MachinePointerInfo(Src)); |
--- |
8347 |
MachinePointerInfo(Src)); |
--- |
| 8348 |
if (Res.first.getNode()) { |
0 |
8348 |
if (Res.first.getNode()) { |
0 |
| 8349 |
setValue(&I, Res.first); |
0 |
8349 |
setValue(&I, Res.first); |
0 |
| 8350 |
PendingLoads.push_back(Res.second); |
0 |
8350 |
PendingLoads.push_back(Res.second); |
0 |
| 8351 |
return true; |
0 |
8351 |
return true; |
0 |
| 8352 |
} |
--- |
8352 |
} |
--- |
| 8353 |
|
--- |
8353 |
|
--- |
| 8354 |
return false; |
0 |
8354 |
return false; |
0 |
| 8355 |
} |
--- |
8355 |
} |
--- |
| 8356 |
|
--- |
8356 |
|
--- |
| 8357 |
/// See if we can lower a mempcpy call into an optimized form. If so, return |
--- |
8357 |
/// See if we can lower a mempcpy call into an optimized form. If so, return |
--- |
| 8358 |
/// true and lower it. Otherwise return false, and it will be lowered like a |
--- |
8358 |
/// true and lower it. Otherwise return false, and it will be lowered like a |
--- |
| 8359 |
/// normal call. |
--- |
8359 |
/// normal call. |
--- |
| 8360 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8360 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8361 |
/// correct prototype. |
--- |
8361 |
/// correct prototype. |
--- |
| 8362 |
bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) { |
0 |
8362 |
bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) { |
0 |
| 8363 |
SDValue Dst = getValue(I.getArgOperand(0)); |
0 |
8363 |
SDValue Dst = getValue(I.getArgOperand(0)); |
0 |
| 8364 |
SDValue Src = getValue(I.getArgOperand(1)); |
0 |
8364 |
SDValue Src = getValue(I.getArgOperand(1)); |
0 |
| 8365 |
SDValue Size = getValue(I.getArgOperand(2)); |
0 |
8365 |
SDValue Size = getValue(I.getArgOperand(2)); |
0 |
| 8366 |
|
--- |
8366 |
|
--- |
| 8367 |
Align DstAlign = DAG.InferPtrAlign(Dst).valueOrOne(); |
0 |
8367 |
Align DstAlign = DAG.InferPtrAlign(Dst).valueOrOne(); |
0 |
| 8368 |
Align SrcAlign = DAG.InferPtrAlign(Src).valueOrOne(); |
0 |
8368 |
Align SrcAlign = DAG.InferPtrAlign(Src).valueOrOne(); |
0 |
| 8369 |
// DAG::getMemcpy needs Alignment to be defined. |
--- |
8369 |
// DAG::getMemcpy needs Alignment to be defined. |
--- |
| 8370 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
8370 |
Align Alignment = std::min(DstAlign, SrcAlign); |
0 |
| 8371 |
|
--- |
8371 |
|
--- |
| 8372 |
SDLoc sdl = getCurSDLoc(); |
0 |
8372 |
SDLoc sdl = getCurSDLoc(); |
0 |
| 8373 |
|
--- |
8373 |
|
--- |
| 8374 |
// In the mempcpy context we need to pass in a false value for isTailCall |
--- |
8374 |
// In the mempcpy context we need to pass in a false value for isTailCall |
--- |
| 8375 |
// because the return pointer needs to be adjusted by the size of |
--- |
8375 |
// because the return pointer needs to be adjusted by the size of |
--- |
| 8376 |
// the copied memory. |
--- |
8376 |
// the copied memory. |
--- |
| 8377 |
SDValue Root = getMemoryRoot(); |
0 |
8377 |
SDValue Root = getMemoryRoot(); |
0 |
| 8378 |
SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Alignment, false, false, |
0 |
8378 |
SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Alignment, false, false, |
0 |
| 8379 |
/*isTailCall=*/false, |
--- |
8379 |
/*isTailCall=*/false, |
--- |
| 8380 |
MachinePointerInfo(I.getArgOperand(0)), |
0 |
8380 |
MachinePointerInfo(I.getArgOperand(0)), |
0 |
| 8381 |
MachinePointerInfo(I.getArgOperand(1)), |
0 |
8381 |
MachinePointerInfo(I.getArgOperand(1)), |
0 |
| 8382 |
I.getAAMetadata()); |
0 |
8382 |
I.getAAMetadata()); |
0 |
| 8383 |
assert(MC.getNode() != nullptr && |
0 |
8383 |
assert(MC.getNode() != nullptr && |
0 |
| 8384 |
"** memcpy should not be lowered as TailCall in mempcpy context **"); |
--- |
8384 |
"** memcpy should not be lowered as TailCall in mempcpy context **"); |
--- |
| 8385 |
DAG.setRoot(MC); |
0 |
8385 |
DAG.setRoot(MC); |
0 |
| 8386 |
|
--- |
8386 |
|
--- |
| 8387 |
// Check if Size needs to be truncated or extended. |
--- |
8387 |
// Check if Size needs to be truncated or extended. |
--- |
| 8388 |
Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType()); |
0 |
8388 |
Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType()); |
0 |
| 8389 |
|
--- |
8389 |
|
--- |
| 8390 |
// Adjust return pointer to point just past the last dst byte. |
--- |
8390 |
// Adjust return pointer to point just past the last dst byte. |
--- |
| 8391 |
SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(), |
0 |
8391 |
SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(), |
0 |
| 8392 |
Dst, Size); |
--- |
8392 |
Dst, Size); |
--- |
| 8393 |
setValue(&I, DstPlusSize); |
0 |
8393 |
setValue(&I, DstPlusSize); |
0 |
| 8394 |
return true; |
0 |
8394 |
return true; |
0 |
| 8395 |
} |
0 |
8395 |
} |
0 |
| 8396 |
|
--- |
8396 |
|
--- |
| 8397 |
/// See if we can lower a strcpy call into an optimized form. If so, return |
--- |
8397 |
/// See if we can lower a strcpy call into an optimized form. If so, return |
--- |
| 8398 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
8398 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
| 8399 |
/// normal call. |
--- |
8399 |
/// normal call. |
--- |
| 8400 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8400 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8401 |
/// correct prototype. |
--- |
8401 |
/// correct prototype. |
--- |
| 8402 |
bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) { |
0 |
8402 |
bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) { |
0 |
| 8403 |
const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); |
0 |
8403 |
const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); |
0 |
| 8404 |
|
--- |
8404 |
|
--- |
| 8405 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
8405 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 8406 |
std::pair Res = |
--- |
8406 |
std::pair Res = |
--- |
| 8407 |
TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(), |
0 |
8407 |
TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(), |
0 |
| 8408 |
getValue(Arg0), getValue(Arg1), |
--- |
8408 |
getValue(Arg0), getValue(Arg1), |
--- |
| 8409 |
MachinePointerInfo(Arg0), |
--- |
8409 |
MachinePointerInfo(Arg0), |
--- |
| 8410 |
MachinePointerInfo(Arg1), isStpcpy); |
--- |
8410 |
MachinePointerInfo(Arg1), isStpcpy); |
--- |
| 8411 |
if (Res.first.getNode()) { |
0 |
8411 |
if (Res.first.getNode()) { |
0 |
| 8412 |
setValue(&I, Res.first); |
0 |
8412 |
setValue(&I, Res.first); |
0 |
| 8413 |
DAG.setRoot(Res.second); |
0 |
8413 |
DAG.setRoot(Res.second); |
0 |
| 8414 |
return true; |
0 |
8414 |
return true; |
0 |
| 8415 |
} |
--- |
8415 |
} |
--- |
| 8416 |
|
--- |
8416 |
|
--- |
| 8417 |
return false; |
0 |
8417 |
return false; |
0 |
| 8418 |
} |
--- |
8418 |
} |
--- |
| 8419 |
|
--- |
8419 |
|
--- |
| 8420 |
/// See if we can lower a strcmp call into an optimized form. If so, return |
--- |
8420 |
/// See if we can lower a strcmp call into an optimized form. If so, return |
--- |
| 8421 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
8421 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
| 8422 |
/// normal call. |
--- |
8422 |
/// normal call. |
--- |
| 8423 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8423 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8424 |
/// correct prototype. |
--- |
8424 |
/// correct prototype. |
--- |
| 8425 |
bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) { |
0 |
8425 |
bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) { |
0 |
| 8426 |
const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); |
0 |
8426 |
const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); |
0 |
| 8427 |
|
--- |
8427 |
|
--- |
| 8428 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
8428 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 8429 |
std::pair Res = |
--- |
8429 |
std::pair Res = |
--- |
| 8430 |
TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
8430 |
TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
| 8431 |
getValue(Arg0), getValue(Arg1), |
--- |
8431 |
getValue(Arg0), getValue(Arg1), |
--- |
| 8432 |
MachinePointerInfo(Arg0), |
--- |
8432 |
MachinePointerInfo(Arg0), |
--- |
| 8433 |
MachinePointerInfo(Arg1)); |
--- |
8433 |
MachinePointerInfo(Arg1)); |
--- |
| 8434 |
if (Res.first.getNode()) { |
0 |
8434 |
if (Res.first.getNode()) { |
0 |
| 8435 |
processIntegerCallValue(I, Res.first, true); |
0 |
8435 |
processIntegerCallValue(I, Res.first, true); |
0 |
| 8436 |
PendingLoads.push_back(Res.second); |
0 |
8436 |
PendingLoads.push_back(Res.second); |
0 |
| 8437 |
return true; |
0 |
8437 |
return true; |
0 |
| 8438 |
} |
--- |
8438 |
} |
--- |
| 8439 |
|
--- |
8439 |
|
--- |
| 8440 |
return false; |
0 |
8440 |
return false; |
0 |
| 8441 |
} |
--- |
8441 |
} |
--- |
| 8442 |
|
--- |
8442 |
|
--- |
| 8443 |
/// See if we can lower a strlen call into an optimized form. If so, return |
--- |
8443 |
/// See if we can lower a strlen call into an optimized form. If so, return |
--- |
| 8444 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
8444 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
| 8445 |
/// normal call. |
--- |
8445 |
/// normal call. |
--- |
| 8446 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8446 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8447 |
/// correct prototype. |
--- |
8447 |
/// correct prototype. |
--- |
| 8448 |
bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) { |
0 |
8448 |
bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) { |
0 |
| 8449 |
const Value *Arg0 = I.getArgOperand(0); |
0 |
8449 |
const Value *Arg0 = I.getArgOperand(0); |
0 |
| 8450 |
|
--- |
8450 |
|
--- |
| 8451 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
8451 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 8452 |
std::pair Res = |
--- |
8452 |
std::pair Res = |
--- |
| 8453 |
TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
8453 |
TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
| 8454 |
getValue(Arg0), MachinePointerInfo(Arg0)); |
--- |
8454 |
getValue(Arg0), MachinePointerInfo(Arg0)); |
--- |
| 8455 |
if (Res.first.getNode()) { |
0 |
8455 |
if (Res.first.getNode()) { |
0 |
| 8456 |
processIntegerCallValue(I, Res.first, false); |
0 |
8456 |
processIntegerCallValue(I, Res.first, false); |
0 |
| 8457 |
PendingLoads.push_back(Res.second); |
0 |
8457 |
PendingLoads.push_back(Res.second); |
0 |
| 8458 |
return true; |
0 |
8458 |
return true; |
0 |
| 8459 |
} |
--- |
8459 |
} |
--- |
| 8460 |
|
--- |
8460 |
|
--- |
| 8461 |
return false; |
0 |
8461 |
return false; |
0 |
| 8462 |
} |
--- |
8462 |
} |
--- |
| 8463 |
|
--- |
8463 |
|
--- |
| 8464 |
/// See if we can lower a strnlen call into an optimized form. If so, return |
--- |
8464 |
/// See if we can lower a strnlen call into an optimized form. If so, return |
--- |
| 8465 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
8465 |
/// true and lower it, otherwise return false and it will be lowered like a |
--- |
| 8466 |
/// normal call. |
--- |
8466 |
/// normal call. |
--- |
| 8467 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8467 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8468 |
/// correct prototype. |
--- |
8468 |
/// correct prototype. |
--- |
| 8469 |
bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) { |
0 |
8469 |
bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) { |
0 |
| 8470 |
const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); |
0 |
8470 |
const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); |
0 |
| 8471 |
|
--- |
8471 |
|
--- |
| 8472 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
8472 |
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); |
0 |
| 8473 |
std::pair Res = |
--- |
8473 |
std::pair Res = |
--- |
| 8474 |
TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
8474 |
TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(), |
0 |
| 8475 |
getValue(Arg0), getValue(Arg1), |
--- |
8475 |
getValue(Arg0), getValue(Arg1), |
--- |
| 8476 |
MachinePointerInfo(Arg0)); |
--- |
8476 |
MachinePointerInfo(Arg0)); |
--- |
| 8477 |
if (Res.first.getNode()) { |
0 |
8477 |
if (Res.first.getNode()) { |
0 |
| 8478 |
processIntegerCallValue(I, Res.first, false); |
0 |
8478 |
processIntegerCallValue(I, Res.first, false); |
0 |
| 8479 |
PendingLoads.push_back(Res.second); |
0 |
8479 |
PendingLoads.push_back(Res.second); |
0 |
| 8480 |
return true; |
0 |
8480 |
return true; |
0 |
| 8481 |
} |
--- |
8481 |
} |
--- |
| 8482 |
|
--- |
8482 |
|
--- |
| 8483 |
return false; |
0 |
8483 |
return false; |
0 |
| 8484 |
} |
--- |
8484 |
} |
--- |
| 8485 |
|
--- |
8485 |
|
--- |
| 8486 |
/// See if we can lower a unary floating-point operation into an SDNode with |
--- |
8486 |
/// See if we can lower a unary floating-point operation into an SDNode with |
--- |
| 8487 |
/// the specified Opcode. If so, return true and lower it, otherwise return |
--- |
8487 |
/// the specified Opcode. If so, return true and lower it, otherwise return |
--- |
| 8488 |
/// false and it will be lowered like a normal call. |
--- |
8488 |
/// false and it will be lowered like a normal call. |
--- |
| 8489 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8489 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8490 |
/// correct prototype. |
--- |
8490 |
/// correct prototype. |
--- |
| 8491 |
bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, |
0 |
8491 |
bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, |
0 |
| 8492 |
unsigned Opcode) { |
--- |
8492 |
unsigned Opcode) { |
--- |
| 8493 |
// We already checked this call's prototype; verify it doesn't modify errno. |
--- |
8493 |
// We already checked this call's prototype; verify it doesn't modify errno. |
--- |
| 8494 |
if (!I.onlyReadsMemory()) |
0 |
8494 |
if (!I.onlyReadsMemory()) |
0 |
| 8495 |
return false; |
0 |
8495 |
return false; |
0 |
| 8496 |
|
--- |
8496 |
|
--- |
| 8497 |
SDNodeFlags Flags; |
0 |
8497 |
SDNodeFlags Flags; |
0 |
| 8498 |
Flags.copyFMF(cast(I)); |
0 |
8498 |
Flags.copyFMF(cast(I)); |
0 |
| 8499 |
|
--- |
8499 |
|
--- |
| 8500 |
SDValue Tmp = getValue(I.getArgOperand(0)); |
0 |
8500 |
SDValue Tmp = getValue(I.getArgOperand(0)); |
0 |
| 8501 |
setValue(&I, |
0 |
8501 |
setValue(&I, |
0 |
| 8502 |
DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp, Flags)); |
0 |
8502 |
DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp, Flags)); |
0 |
| 8503 |
return true; |
0 |
8503 |
return true; |
0 |
| 8504 |
} |
--- |
8504 |
} |
--- |
| 8505 |
|
--- |
8505 |
|
--- |
| 8506 |
/// See if we can lower a binary floating-point operation into an SDNode with |
--- |
8506 |
/// See if we can lower a binary floating-point operation into an SDNode with |
--- |
| 8507 |
/// the specified Opcode. If so, return true and lower it. Otherwise return |
--- |
8507 |
/// the specified Opcode. If so, return true and lower it. Otherwise return |
--- |
| 8508 |
/// false, and it will be lowered like a normal call. |
--- |
8508 |
/// false, and it will be lowered like a normal call. |
--- |
| 8509 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
8509 |
/// The caller already checked that \p I calls the appropriate LibFunc with a |
--- |
| 8510 |
/// correct prototype. |
--- |
8510 |
/// correct prototype. |
--- |
| 8511 |
bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I, |
0 |
8511 |
bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I, |
0 |
| 8512 |
unsigned Opcode) { |
--- |
8512 |
unsigned Opcode) { |
--- |
| 8513 |
// We already checked this call's prototype; verify it doesn't modify errno. |
--- |
8513 |
// We already checked this call's prototype; verify it doesn't modify errno. |
--- |
| 8514 |
if (!I.onlyReadsMemory()) |
0 |
8514 |
if (!I.onlyReadsMemory()) |
0 |
| 8515 |
return false; |
0 |
8515 |
return false; |
0 |
| 8516 |
|
--- |
8516 |
|
--- |
| 8517 |
SDNodeFlags Flags; |
0 |
8517 |
SDNodeFlags Flags; |
0 |
| 8518 |
Flags.copyFMF(cast(I)); |
0 |
8518 |
Flags.copyFMF(cast(I)); |
0 |
| 8519 |
|
--- |
8519 |
|
--- |
| 8520 |
SDValue Tmp0 = getValue(I.getArgOperand(0)); |
0 |
8520 |
SDValue Tmp0 = getValue(I.getArgOperand(0)); |
0 |
| 8521 |
SDValue Tmp1 = getValue(I.getArgOperand(1)); |
0 |
8521 |
SDValue Tmp1 = getValue(I.getArgOperand(1)); |
0 |
| 8522 |
EVT VT = Tmp0.getValueType(); |
0 |
8522 |
EVT VT = Tmp0.getValueType(); |
0 |
| 8523 |
setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1, Flags)); |
0 |
8523 |
setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1, Flags)); |
0 |
| 8524 |
return true; |
0 |
8524 |
return true; |
0 |
| 8525 |
} |
--- |
8525 |
} |
--- |
| 8526 |
|
--- |
8526 |
|
--- |
| 8527 |
void SelectionDAGBuilder::visitCall(const CallInst &I) { |
3 |
8527 |
void SelectionDAGBuilder::visitCall(const CallInst &I) { |
0 |
| 8528 |
// Handle inline assembly differently. |
--- |
8528 |
// Handle inline assembly differently. |
--- |
| 8529 |
if (I.isInlineAsm()) { |
3 |
8529 |
if (I.isInlineAsm()) { |
0 |
| 8530 |
visitInlineAsm(I); |
0 |
8530 |
visitInlineAsm(I); |
0 |
| 8531 |
return; |
3 |
8531 |
return; |
0 |
| 8532 |
} |
--- |
8532 |
} |
--- |
| 8533 |
|
--- |
8533 |
|
--- |
| 8534 |
diagnoseDontCall(I); |
3 |
8534 |
diagnoseDontCall(I); |
0 |
| 8535 |
|
--- |
8535 |
|
--- |
| 8536 |
if (Function *F = I.getCalledFunction()) { |
3 |
8536 |
if (Function *F = I.getCalledFunction()) { |
0 |
| 8537 |
if (F->isDeclaration()) { |
3 |
8537 |
if (F->isDeclaration()) { |
0 |
| 8538 |
// Is this an LLVM intrinsic or a target-specific intrinsic? |
--- |
8538 |
// Is this an LLVM intrinsic or a target-specific intrinsic? |
--- |
| 8539 |
unsigned IID = F->getIntrinsicID(); |
3 |
8539 |
unsigned IID = F->getIntrinsicID(); |
0 |
| 8540 |
if (!IID) |
3 |
8540 |
if (!IID) |
0 |
| 8541 |
if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) |
0 |
8541 |
if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) |
0 |
| 8542 |
IID = II->getIntrinsicID(F); |
0 |
8542 |
IID = II->getIntrinsicID(F); |
0 |
| 8543 |
|
--- |
8543 |
|
--- |
| 8544 |
if (IID) { |
3 |
8544 |
if (IID) { |
0 |
| 8545 |
visitIntrinsicCall(I, IID); |
3 |
8545 |
visitIntrinsicCall(I, IID); |
0 |
| 8546 |
return; |
3 |
8546 |
return; |
0 |
| 8547 |
} |
--- |
8547 |
} |
--- |
| 8548 |
} |
--- |
8548 |
} |
--- |
| 8549 |
|
--- |
8549 |
|
--- |
| 8550 |
// Check for well-known libc/libm calls. If the function is internal, it |
--- |
8550 |
// Check for well-known libc/libm calls. If the function is internal, it |
--- |
| 8551 |
// can't be a library call. Don't do the check if marked as nobuiltin for |
--- |
8551 |
// can't be a library call. Don't do the check if marked as nobuiltin for |
--- |
| 8552 |
// some reason or the call site requires strict floating point semantics. |
--- |
8552 |
// some reason or the call site requires strict floating point semantics. |
--- |
| 8553 |
LibFunc Func; |
--- |
8553 |
LibFunc Func; |
--- |
| 8554 |
if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() && |
0 |
8554 |
if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() && |
0 |
| 8555 |
F->hasName() && LibInfo->getLibFunc(*F, Func) && |
0 |
8555 |
F->hasName() && LibInfo->getLibFunc(*F, Func) && |
0 |
| 8556 |
LibInfo->hasOptimizedCodeGen(Func)) { |
0 |
8556 |
LibInfo->hasOptimizedCodeGen(Func)) { |
0 |
| 8557 |
switch (Func) { |
0 |
8557 |
switch (Func) { |
0 |
| 8558 |
default: break; |
0 |
8558 |
default: break; |
0 |
| 8559 |
case LibFunc_bcmp: |
0 |
8559 |
case LibFunc_bcmp: |
0 |
| 8560 |
if (visitMemCmpBCmpCall(I)) |
0 |
8560 |
if (visitMemCmpBCmpCall(I)) |
0 |
| 8561 |
return; |
0 |
8561 |
return; |
0 |
| 8562 |
break; |
0 |
8562 |
break; |
0 |
| 8563 |
case LibFunc_copysign: |
0 |
8563 |
case LibFunc_copysign: |
0 |
| 8564 |
case LibFunc_copysignf: |
--- |
8564 |
case LibFunc_copysignf: |
--- |
| 8565 |
case LibFunc_copysignl: |
--- |
8565 |
case LibFunc_copysignl: |
--- |
| 8566 |
// We already checked this call's prototype; verify it doesn't modify |
--- |
8566 |
// We already checked this call's prototype; verify it doesn't modify |
--- |
| 8567 |
// errno. |
--- |
8567 |
// errno. |
--- |
| 8568 |
if (I.onlyReadsMemory()) { |
0 |
8568 |
if (I.onlyReadsMemory()) { |
0 |
| 8569 |
SDValue LHS = getValue(I.getArgOperand(0)); |
0 |
8569 |
SDValue LHS = getValue(I.getArgOperand(0)); |
0 |
| 8570 |
SDValue RHS = getValue(I.getArgOperand(1)); |
0 |
8570 |
SDValue RHS = getValue(I.getArgOperand(1)); |
0 |
| 8571 |
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), |
0 |
8571 |
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), |
0 |
| 8572 |
LHS.getValueType(), LHS, RHS)); |
--- |
8572 |
LHS.getValueType(), LHS, RHS)); |
--- |
| 8573 |
return; |
0 |
8573 |
return; |
0 |
| 8574 |
} |
--- |
8574 |
} |
--- |
| 8575 |
break; |
0 |
8575 |
break; |
0 |
| 8576 |
case LibFunc_fabs: |
0 |
8576 |
case LibFunc_fabs: |
0 |
| 8577 |
case LibFunc_fabsf: |
--- |
8577 |
case LibFunc_fabsf: |
--- |
| 8578 |
case LibFunc_fabsl: |
--- |
8578 |
case LibFunc_fabsl: |
--- |
| 8579 |
if (visitUnaryFloatCall(I, ISD::FABS)) |
0 |
8579 |
if (visitUnaryFloatCall(I, ISD::FABS)) |
0 |
| 8580 |
return; |
0 |
8580 |
return; |
0 |
| 8581 |
break; |
0 |
8581 |
break; |
0 |
| 8582 |
case LibFunc_fmin: |
0 |
8582 |
case LibFunc_fmin: |
0 |
| 8583 |
case LibFunc_fminf: |
--- |
8583 |
case LibFunc_fminf: |
--- |
| 8584 |
case LibFunc_fminl: |
--- |
8584 |
case LibFunc_fminl: |
--- |
| 8585 |
if (visitBinaryFloatCall(I, ISD::FMINNUM)) |
0 |
8585 |
if (visitBinaryFloatCall(I, ISD::FMINNUM)) |
0 |
| 8586 |
return; |
0 |
8586 |
return; |
0 |
| 8587 |
break; |
0 |
8587 |
break; |
0 |
| 8588 |
case LibFunc_fmax: |
0 |
8588 |
case LibFunc_fmax: |
0 |
| 8589 |
case LibFunc_fmaxf: |
--- |
8589 |
case LibFunc_fmaxf: |
--- |
| 8590 |
case LibFunc_fmaxl: |
--- |
8590 |
case LibFunc_fmaxl: |
--- |
| 8591 |
if (visitBinaryFloatCall(I, ISD::FMAXNUM)) |
0 |
8591 |
if (visitBinaryFloatCall(I, ISD::FMAXNUM)) |
0 |
| 8592 |
return; |
0 |
8592 |
return; |
0 |
| 8593 |
break; |
0 |
8593 |
break; |
0 |
| 8594 |
case LibFunc_sin: |
0 |
8594 |
case LibFunc_sin: |
0 |
| 8595 |
case LibFunc_sinf: |
--- |
8595 |
case LibFunc_sinf: |
--- |
| 8596 |
case LibFunc_sinl: |
--- |
8596 |
case LibFunc_sinl: |
--- |
| 8597 |
if (visitUnaryFloatCall(I, ISD::FSIN)) |
0 |
8597 |
if (visitUnaryFloatCall(I, ISD::FSIN)) |
0 |
| 8598 |
return; |
0 |
8598 |
return; |
0 |
| 8599 |
break; |
0 |
8599 |
break; |
0 |
| 8600 |
case LibFunc_cos: |
0 |
8600 |
case LibFunc_cos: |
0 |
| 8601 |
case LibFunc_cosf: |
--- |
8601 |
case LibFunc_cosf: |
--- |
| 8602 |
case LibFunc_cosl: |
--- |
8602 |
case LibFunc_cosl: |
--- |
| 8603 |
if (visitUnaryFloatCall(I, ISD::FCOS)) |
0 |
8603 |
if (visitUnaryFloatCall(I, ISD::FCOS)) |
0 |
| 8604 |
return; |
0 |
8604 |
return; |
0 |
| 8605 |
break; |
0 |
8605 |
break; |
0 |
| 8606 |
case LibFunc_sqrt: |
0 |
8606 |
case LibFunc_sqrt: |
0 |
| 8607 |
case LibFunc_sqrtf: |
--- |
8607 |
case LibFunc_sqrtf: |
--- |
| 8608 |
case LibFunc_sqrtl: |
--- |
8608 |
case LibFunc_sqrtl: |
--- |
| 8609 |
case LibFunc_sqrt_finite: |
--- |
8609 |
case LibFunc_sqrt_finite: |
--- |
| 8610 |
case LibFunc_sqrtf_finite: |
--- |
8610 |
case LibFunc_sqrtf_finite: |
--- |
| 8611 |
case LibFunc_sqrtl_finite: |
--- |
8611 |
case LibFunc_sqrtl_finite: |
--- |
| 8612 |
if (visitUnaryFloatCall(I, ISD::FSQRT)) |
0 |
8612 |
if (visitUnaryFloatCall(I, ISD::FSQRT)) |
0 |
| 8613 |
return; |
0 |
8613 |
return; |
0 |
| 8614 |
break; |
0 |
8614 |
break; |
0 |
| 8615 |
case LibFunc_floor: |
0 |
8615 |
case LibFunc_floor: |
0 |
| 8616 |
case LibFunc_floorf: |
--- |
8616 |
case LibFunc_floorf: |
--- |
| 8617 |
case LibFunc_floorl: |
--- |
8617 |
case LibFunc_floorl: |
--- |
| 8618 |
if (visitUnaryFloatCall(I, ISD::FFLOOR)) |
0 |
8618 |
if (visitUnaryFloatCall(I, ISD::FFLOOR)) |
0 |
| 8619 |
return; |
0 |
8619 |
return; |
0 |
| 8620 |
break; |
0 |
8620 |
break; |
0 |
| 8621 |
case LibFunc_nearbyint: |
0 |
8621 |
case LibFunc_nearbyint: |
0 |
| 8622 |
case LibFunc_nearbyintf: |
--- |
8622 |
case LibFunc_nearbyintf: |
--- |
| 8623 |
case LibFunc_nearbyintl: |
--- |
8623 |
case LibFunc_nearbyintl: |
--- |
| 8624 |
if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) |
0 |
8624 |
if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) |
0 |
| 8625 |
return; |
0 |
8625 |
return; |
0 |
| 8626 |
break; |
0 |
8626 |
break; |
0 |
| 8627 |
case LibFunc_ceil: |
0 |
8627 |
case LibFunc_ceil: |
0 |
| 8628 |
case LibFunc_ceilf: |
--- |
8628 |
case LibFunc_ceilf: |
--- |
| 8629 |
case LibFunc_ceill: |
--- |
8629 |
case LibFunc_ceill: |
--- |
| 8630 |
if (visitUnaryFloatCall(I, ISD::FCEIL)) |
0 |
8630 |
if (visitUnaryFloatCall(I, ISD::FCEIL)) |
0 |
| 8631 |
return; |
0 |
8631 |
return; |
0 |
| 8632 |
break; |
0 |
8632 |
break; |
0 |
| 8633 |
case LibFunc_rint: |
0 |
8633 |
case LibFunc_rint: |
0 |
| 8634 |
case LibFunc_rintf: |
--- |
8634 |
case LibFunc_rintf: |
--- |
| 8635 |
case LibFunc_rintl: |
--- |
8635 |
case LibFunc_rintl: |
--- |
| 8636 |
if (visitUnaryFloatCall(I, ISD::FRINT)) |
0 |
8636 |
if (visitUnaryFloatCall(I, ISD::FRINT)) |
0 |
| 8637 |
return; |
0 |
8637 |
return; |
0 |
| 8638 |
break; |
0 |
8638 |
break; |
0 |
| 8639 |
case LibFunc_round: |
0 |
8639 |
case LibFunc_round: |
0 |
| 8640 |
case LibFunc_roundf: |
--- |
8640 |
case LibFunc_roundf: |
--- |
| 8641 |
case LibFunc_roundl: |
--- |
8641 |
case LibFunc_roundl: |
--- |
| 8642 |
if (visitUnaryFloatCall(I, ISD::FROUND)) |
0 |
8642 |
if (visitUnaryFloatCall(I, ISD::FROUND)) |
0 |
| 8643 |
return; |
0 |
8643 |
return; |
0 |
| 8644 |
break; |
0 |
8644 |
break; |
0 |
| 8645 |
case LibFunc_trunc: |
0 |
8645 |
case LibFunc_trunc: |
0 |
| 8646 |
case LibFunc_truncf: |
--- |
8646 |
case LibFunc_truncf: |
--- |
| 8647 |
case LibFunc_truncl: |
--- |
8647 |
case LibFunc_truncl: |
--- |
| 8648 |
if (visitUnaryFloatCall(I, ISD::FTRUNC)) |
0 |
8648 |
if (visitUnaryFloatCall(I, ISD::FTRUNC)) |
0 |
| 8649 |
return; |
0 |
8649 |
return; |
0 |
| 8650 |
break; |
0 |
8650 |
break; |
0 |
| 8651 |
case LibFunc_log2: |
0 |
8651 |
case LibFunc_log2: |
0 |
| 8652 |
case LibFunc_log2f: |
--- |
8652 |
case LibFunc_log2f: |
--- |
| 8653 |
case LibFunc_log2l: |
--- |
8653 |
case LibFunc_log2l: |
--- |
| 8654 |
if (visitUnaryFloatCall(I, ISD::FLOG2)) |
0 |
8654 |
if (visitUnaryFloatCall(I, ISD::FLOG2)) |
0 |
| 8655 |
return; |
0 |
8655 |
return; |
0 |
| 8656 |
break; |
0 |
8656 |
break; |
0 |
| 8657 |
case LibFunc_exp2: |
0 |
8657 |
case LibFunc_exp2: |
0 |
| 8658 |
case LibFunc_exp2f: |
--- |
8658 |
case LibFunc_exp2f: |
--- |
| 8659 |
case LibFunc_exp2l: |
--- |
8659 |
case LibFunc_exp2l: |
--- |
| 8660 |
if (visitUnaryFloatCall(I, ISD::FEXP2)) |
0 |
8660 |
if (visitUnaryFloatCall(I, ISD::FEXP2)) |
0 |
| 8661 |
return; |
0 |
8661 |
return; |
0 |
| 8662 |
break; |
0 |
8662 |
break; |
0 |
| 8663 |
case LibFunc_ldexp: |
0 |
8663 |
case LibFunc_ldexp: |
0 |
| 8664 |
case LibFunc_ldexpf: |
--- |
8664 |
case LibFunc_ldexpf: |
--- |
| 8665 |
case LibFunc_ldexpl: |
--- |
8665 |
case LibFunc_ldexpl: |
--- |
| 8666 |
if (visitBinaryFloatCall(I, ISD::FLDEXP)) |
0 |
8666 |
if (visitBinaryFloatCall(I, ISD::FLDEXP)) |
0 |
| 8667 |
return; |
0 |
8667 |
return; |
0 |
| 8668 |
break; |
0 |
8668 |
break; |
0 |
| 8669 |
case LibFunc_memcmp: |
0 |
8669 |
case LibFunc_memcmp: |
0 |
| 8670 |
if (visitMemCmpBCmpCall(I)) |
0 |
8670 |
if (visitMemCmpBCmpCall(I)) |
0 |
| 8671 |
return; |
0 |
8671 |
return; |
0 |
| 8672 |
break; |
0 |
8672 |
break; |
0 |
| 8673 |
case LibFunc_mempcpy: |
0 |
8673 |
case LibFunc_mempcpy: |
0 |
| 8674 |
if (visitMemPCpyCall(I)) |
0 |
8674 |
if (visitMemPCpyCall(I)) |
0 |
| 8675 |
return; |
0 |
8675 |
return; |
0 |
| 8676 |
break; |
0 |
8676 |
break; |
0 |
| 8677 |
case LibFunc_memchr: |
0 |
8677 |
case LibFunc_memchr: |
0 |
| 8678 |
if (visitMemChrCall(I)) |
0 |
8678 |
if (visitMemChrCall(I)) |
0 |
| 8679 |
return; |
0 |
8679 |
return; |
0 |
| 8680 |
break; |
0 |
8680 |
break; |
0 |
| 8681 |
case LibFunc_strcpy: |
0 |
8681 |
case LibFunc_strcpy: |
0 |
| 8682 |
if (visitStrCpyCall(I, false)) |
0 |
8682 |
if (visitStrCpyCall(I, false)) |
0 |
| 8683 |
return; |
0 |
8683 |
return; |
0 |
| 8684 |
break; |
0 |
8684 |
break; |
0 |
| 8685 |
case LibFunc_stpcpy: |
0 |
8685 |
case LibFunc_stpcpy: |
0 |
| 8686 |
if (visitStrCpyCall(I, true)) |
0 |
8686 |
if (visitStrCpyCall(I, true)) |
0 |
| 8687 |
return; |
0 |
8687 |
return; |
0 |
| 8688 |
break; |
0 |
8688 |
break; |
0 |
| 8689 |
case LibFunc_strcmp: |
0 |
8689 |
case LibFunc_strcmp: |
0 |
| 8690 |
if (visitStrCmpCall(I)) |
0 |
8690 |
if (visitStrCmpCall(I)) |
0 |
| 8691 |
return; |
0 |
8691 |
return; |
0 |
| 8692 |
break; |
0 |
8692 |
break; |
0 |
| 8693 |
case LibFunc_strlen: |
0 |
8693 |
case LibFunc_strlen: |
0 |
| 8694 |
if (visitStrLenCall(I)) |
0 |
8694 |
if (visitStrLenCall(I)) |
0 |
| 8695 |
return; |
0 |
8695 |
return; |
0 |
| 8696 |
break; |
0 |
8696 |
break; |
0 |
| 8697 |
case LibFunc_strnlen: |
0 |
8697 |
case LibFunc_strnlen: |
0 |
| 8698 |
if (visitStrNLenCall(I)) |
0 |
8698 |
if (visitStrNLenCall(I)) |
0 |
| 8699 |
return; |
0 |
8699 |
return; |
0 |
| 8700 |
break; |
0 |
8700 |
break; |
0 |
| 8701 |
} |
--- |
8701 |
} |
--- |
| 8702 |
} |
--- |
8702 |
} |
--- |
| 8703 |
} |
--- |
8703 |
} |
--- |
| 8704 |
|
--- |
8704 |
|
--- |
| 8705 |
// Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't |
--- |
8705 |
// Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't |
--- |
| 8706 |
// have to do anything here to lower funclet bundles. |
--- |
8706 |
// have to do anything here to lower funclet bundles. |
--- |
| 8707 |
// CFGuardTarget bundles are lowered in LowerCallTo. |
--- |
8707 |
// CFGuardTarget bundles are lowered in LowerCallTo. |
--- |
| 8708 |
assert(!I.hasOperandBundlesOtherThan( |
0 |
8708 |
assert(!I.hasOperandBundlesOtherThan( |
0 |
| 8709 |
{LLVMContext::OB_deopt, LLVMContext::OB_funclet, |
--- |
8709 |
{LLVMContext::OB_deopt, LLVMContext::OB_funclet, |
--- |
| 8710 |
LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated, |
--- |
8710 |
LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated, |
--- |
| 8711 |
LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi}) && |
--- |
8711 |
LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi}) && |
--- |
| 8712 |
"Cannot lower calls with arbitrary operand bundles!"); |
--- |
8712 |
"Cannot lower calls with arbitrary operand bundles!"); |
--- |
| 8713 |
|
--- |
8713 |
|
--- |
| 8714 |
SDValue Callee = getValue(I.getCalledOperand()); |
0 |
8714 |
SDValue Callee = getValue(I.getCalledOperand()); |
0 |
| 8715 |
|
--- |
8715 |
|
--- |
| 8716 |
if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) |
0 |
8716 |
if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) |
0 |
| 8717 |
LowerCallSiteWithDeoptBundle(&I, Callee, nullptr); |
0 |
8717 |
LowerCallSiteWithDeoptBundle(&I, Callee, nullptr); |
0 |
| 8718 |
else |
--- |
8718 |
else |
--- |
| 8719 |
// Check if we can potentially perform a tail call. More detailed checking |
--- |
8719 |
// Check if we can potentially perform a tail call. More detailed checking |
--- |
| 8720 |
// is be done within LowerCallTo, after more information about the call is |
--- |
8720 |
// is be done within LowerCallTo, after more information about the call is |
--- |
| 8721 |
// known. |
--- |
8721 |
// known. |
--- |
| 8722 |
LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall()); |
0 |
8722 |
LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall()); |
0 |
| 8723 |
} |
--- |
8723 |
} |
--- |
| 8724 |
|
--- |
8724 |
|
--- |
| 8725 |
namespace { |
--- |
8725 |
namespace { |
--- |
| 8726 |
|
--- |
8726 |
|
--- |
| 8727 |
/// AsmOperandInfo - This contains information for each constraint that we are |
--- |
8727 |
/// AsmOperandInfo - This contains information for each constraint that we are |
--- |
| 8728 |
/// lowering. |
--- |
8728 |
/// lowering. |
--- |
| 8729 |
class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { |
--- |
8729 |
class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { |
--- |
| 8730 |
public: |
--- |
8730 |
public: |
--- |
| 8731 |
/// CallOperand - If this is the result output operand or a clobber |
--- |
8731 |
/// CallOperand - If this is the result output operand or a clobber |
--- |
| 8732 |
/// this is null, otherwise it is the incoming operand to the CallInst. |
--- |
8732 |
/// this is null, otherwise it is the incoming operand to the CallInst. |
--- |
| 8733 |
/// This gets modified as the asm is processed. |
--- |
8733 |
/// This gets modified as the asm is processed. |
--- |
| 8734 |
SDValue CallOperand; |
--- |
8734 |
SDValue CallOperand; |
--- |
| 8735 |
|
--- |
8735 |
|
--- |
| 8736 |
/// AssignedRegs - If this is a register or register class operand, this |
--- |
8736 |
/// AssignedRegs - If this is a register or register class operand, this |
--- |
| 8737 |
/// contains the set of register corresponding to the operand. |
--- |
8737 |
/// contains the set of register corresponding to the operand. |
--- |
| 8738 |
RegsForValue AssignedRegs; |
--- |
8738 |
RegsForValue AssignedRegs; |
--- |
| 8739 |
|
--- |
8739 |
|
--- |
| 8740 |
explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) |
0 |
8740 |
explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) |
0 |
| 8741 |
: TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) { |
0 |
8741 |
: TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) { |
0 |
| 8742 |
} |
0 |
8742 |
} |
0 |
| 8743 |
|
--- |
8743 |
|
--- |
| 8744 |
/// Whether or not this operand accesses memory |
--- |
8744 |
/// Whether or not this operand accesses memory |
--- |
| 8745 |
bool hasMemory(const TargetLowering &TLI) const { |
0 |
8745 |
bool hasMemory(const TargetLowering &TLI) const { |
0 |
| 8746 |
// Indirect operand accesses access memory. |
--- |
8746 |
// Indirect operand accesses access memory. |
--- |
| 8747 |
if (isIndirect) |
0 |
8747 |
if (isIndirect) |
0 |
| 8748 |
return true; |
0 |
8748 |
return true; |
0 |
| 8749 |
|
--- |
8749 |
|
--- |
| 8750 |
for (const auto &Code : Codes) |
0 |
8750 |
for (const auto &Code : Codes) |
0 |
| 8751 |
if (TLI.getConstraintType(Code) == TargetLowering::C_Memory) |
0 |
8751 |
if (TLI.getConstraintType(Code) == TargetLowering::C_Memory) |
0 |
| 8752 |
return true; |
0 |
8752 |
return true; |
0 |
| 8753 |
|
--- |
8753 |
|
--- |
| 8754 |
return false; |
0 |
8754 |
return false; |
0 |
| 8755 |
} |
--- |
8755 |
} |
--- |
| 8756 |
}; |
--- |
8756 |
}; |
--- |
| 8757 |
|
--- |
8757 |
|
--- |
| 8758 |
|
--- |
8758 |
|
--- |
| 8759 |
} // end anonymous namespace |
--- |
8759 |
} // end anonymous namespace |
--- |
| 8760 |
|
--- |
8760 |
|
--- |
| 8761 |
/// Make sure that the output operand \p OpInfo and its corresponding input |
--- |
8761 |
/// Make sure that the output operand \p OpInfo and its corresponding input |
--- |
| 8762 |
/// operand \p MatchingOpInfo have compatible constraint types (otherwise error |
--- |
8762 |
/// operand \p MatchingOpInfo have compatible constraint types (otherwise error |
--- |
| 8763 |
/// out). |
--- |
8763 |
/// out). |
--- |
| 8764 |
static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, |
0 |
8764 |
static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, |
0 |
| 8765 |
SDISelAsmOperandInfo &MatchingOpInfo, |
--- |
8765 |
SDISelAsmOperandInfo &MatchingOpInfo, |
--- |
| 8766 |
SelectionDAG &DAG) { |
--- |
8766 |
SelectionDAG &DAG) { |
--- |
| 8767 |
if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT) |
0 |
8767 |
if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT) |
0 |
| 8768 |
return; |
0 |
8768 |
return; |
0 |
| 8769 |
|
--- |
8769 |
|
--- |
| 8770 |
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); |
0 |
8770 |
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); |
0 |
| 8771 |
const auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
8771 |
const auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 8772 |
|
--- |
8772 |
|
--- |
| 8773 |
std::pair MatchRC = |
--- |
8773 |
std::pair MatchRC = |
--- |
| 8774 |
TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, |
0 |
8774 |
TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, |
0 |
| 8775 |
OpInfo.ConstraintVT); |
--- |
8775 |
OpInfo.ConstraintVT); |
--- |
| 8776 |
std::pair InputRC = |
--- |
8776 |
std::pair InputRC = |
--- |
| 8777 |
TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode, |
0 |
8777 |
TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode, |
0 |
| 8778 |
MatchingOpInfo.ConstraintVT); |
--- |
8778 |
MatchingOpInfo.ConstraintVT); |
--- |
| 8779 |
if ((OpInfo.ConstraintVT.isInteger() != |
0 |
8779 |
if ((OpInfo.ConstraintVT.isInteger() != |
0 |
| 8780 |
MatchingOpInfo.ConstraintVT.isInteger()) || |
0 |
8780 |
MatchingOpInfo.ConstraintVT.isInteger()) || |
0 |
| 8781 |
(MatchRC.second != InputRC.second)) { |
0 |
8781 |
(MatchRC.second != InputRC.second)) { |
0 |
| 8782 |
// FIXME: error out in a more elegant fashion |
--- |
8782 |
// FIXME: error out in a more elegant fashion |
--- |
| 8783 |
report_fatal_error("Unsupported asm: input constraint" |
0 |
8783 |
report_fatal_error("Unsupported asm: input constraint" |
0 |
| 8784 |
" with a matching output constraint of" |
--- |
8784 |
" with a matching output constraint of" |
--- |
| 8785 |
" incompatible type!"); |
--- |
8785 |
" incompatible type!"); |
--- |
| 8786 |
} |
--- |
8786 |
} |
--- |
| 8787 |
MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT; |
0 |
8787 |
MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT; |
0 |
| 8788 |
} |
--- |
8788 |
} |
--- |
| 8789 |
|
--- |
8789 |
|
--- |
| 8790 |
/// Get a direct memory input to behave well as an indirect operand. |
--- |
8790 |
/// Get a direct memory input to behave well as an indirect operand. |
--- |
| 8791 |
/// This may introduce stores, hence the need for a \p Chain. |
--- |
8791 |
/// This may introduce stores, hence the need for a \p Chain. |
--- |
| 8792 |
/// \return The (possibly updated) chain. |
--- |
8792 |
/// \return The (possibly updated) chain. |
--- |
| 8793 |
static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, |
0 |
8793 |
static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, |
0 |
| 8794 |
SDISelAsmOperandInfo &OpInfo, |
--- |
8794 |
SDISelAsmOperandInfo &OpInfo, |
--- |
| 8795 |
SelectionDAG &DAG) { |
--- |
8795 |
SelectionDAG &DAG) { |
--- |
| 8796 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
8796 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 8797 |
|
--- |
8797 |
|
--- |
| 8798 |
// If we don't have an indirect input, put it in the constpool if we can, |
--- |
8798 |
// If we don't have an indirect input, put it in the constpool if we can, |
--- |
| 8799 |
// otherwise spill it to a stack slot. |
--- |
8799 |
// otherwise spill it to a stack slot. |
--- |
| 8800 |
// TODO: This isn't quite right. We need to handle these according to |
--- |
8800 |
// TODO: This isn't quite right. We need to handle these according to |
--- |
| 8801 |
// the addressing mode that the constraint wants. Also, this may take |
--- |
8801 |
// the addressing mode that the constraint wants. Also, this may take |
--- |
| 8802 |
// an additional register for the computation and we don't want that |
--- |
8802 |
// an additional register for the computation and we don't want that |
--- |
| 8803 |
// either. |
--- |
8803 |
// either. |
--- |
| 8804 |
|
--- |
8804 |
|
--- |
| 8805 |
// If the operand is a float, integer, or vector constant, spill to a |
--- |
8805 |
// If the operand is a float, integer, or vector constant, spill to a |
--- |
| 8806 |
// constant pool entry to get its address. |
--- |
8806 |
// constant pool entry to get its address. |
--- |
| 8807 |
const Value *OpVal = OpInfo.CallOperandVal; |
0 |
8807 |
const Value *OpVal = OpInfo.CallOperandVal; |
0 |
| 8808 |
if (isa(OpVal) || isa(OpVal) || |
0 |
8808 |
if (isa(OpVal) || isa(OpVal) || |
0 |
| 8809 |
isa(OpVal) || isa(OpVal)) { |
0 |
8809 |
isa(OpVal) || isa(OpVal)) { |
0 |
| 8810 |
OpInfo.CallOperand = DAG.getConstantPool( |
0 |
8810 |
OpInfo.CallOperand = DAG.getConstantPool( |
0 |
| 8811 |
cast(OpVal), TLI.getPointerTy(DAG.getDataLayout())); |
0 |
8811 |
cast(OpVal), TLI.getPointerTy(DAG.getDataLayout())); |
0 |
| 8812 |
return Chain; |
0 |
8812 |
return Chain; |
0 |
| 8813 |
} |
--- |
8813 |
} |
--- |
| 8814 |
|
--- |
8814 |
|
--- |
| 8815 |
// Otherwise, create a stack slot and emit a store to it before the asm. |
--- |
8815 |
// Otherwise, create a stack slot and emit a store to it before the asm. |
--- |
| 8816 |
Type *Ty = OpVal->getType(); |
0 |
8816 |
Type *Ty = OpVal->getType(); |
0 |
| 8817 |
auto &DL = DAG.getDataLayout(); |
0 |
8817 |
auto &DL = DAG.getDataLayout(); |
0 |
| 8818 |
uint64_t TySize = DL.getTypeAllocSize(Ty); |
0 |
8818 |
uint64_t TySize = DL.getTypeAllocSize(Ty); |
0 |
| 8819 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
8819 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 8820 |
int SSFI = MF.getFrameInfo().CreateStackObject( |
0 |
8820 |
int SSFI = MF.getFrameInfo().CreateStackObject( |
0 |
| 8821 |
TySize, DL.getPrefTypeAlign(Ty), false); |
--- |
8821 |
TySize, DL.getPrefTypeAlign(Ty), false); |
--- |
| 8822 |
SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL)); |
0 |
8822 |
SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL)); |
0 |
| 8823 |
Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot, |
0 |
8823 |
Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot, |
0 |
| 8824 |
MachinePointerInfo::getFixedStack(MF, SSFI), |
--- |
8824 |
MachinePointerInfo::getFixedStack(MF, SSFI), |
--- |
| 8825 |
TLI.getMemValueType(DL, Ty)); |
--- |
8825 |
TLI.getMemValueType(DL, Ty)); |
--- |
| 8826 |
OpInfo.CallOperand = StackSlot; |
0 |
8826 |
OpInfo.CallOperand = StackSlot; |
0 |
| 8827 |
|
--- |
8827 |
|
--- |
| 8828 |
return Chain; |
0 |
8828 |
return Chain; |
0 |
| 8829 |
} |
--- |
8829 |
} |
--- |
| 8830 |
|
--- |
8830 |
|
--- |
| 8831 |
/// GetRegistersForValue - Assign registers (virtual or physical) for the |
--- |
8831 |
/// GetRegistersForValue - Assign registers (virtual or physical) for the |
--- |
| 8832 |
/// specified operand. We prefer to assign virtual registers, to allow the |
--- |
8832 |
/// specified operand. We prefer to assign virtual registers, to allow the |
--- |
| 8833 |
/// register allocator to handle the assignment process. However, if the asm |
--- |
8833 |
/// register allocator to handle the assignment process. However, if the asm |
--- |
| 8834 |
/// uses features that we can't model on machineinstrs, we have SDISel do the |
--- |
8834 |
/// uses features that we can't model on machineinstrs, we have SDISel do the |
--- |
| 8835 |
/// allocation. This produces generally horrible, but correct, code. |
--- |
8835 |
/// allocation. This produces generally horrible, but correct, code. |
--- |
| 8836 |
/// |
--- |
8836 |
/// |
--- |
| 8837 |
/// OpInfo describes the operand |
--- |
8837 |
/// OpInfo describes the operand |
--- |
| 8838 |
/// RefOpInfo describes the matching operand if any, the operand otherwise |
--- |
8838 |
/// RefOpInfo describes the matching operand if any, the operand otherwise |
--- |
| 8839 |
static std::optional |
--- |
8839 |
static std::optional |
--- |
| 8840 |
getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL, |
0 |
8840 |
getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL, |
0 |
| 8841 |
SDISelAsmOperandInfo &OpInfo, |
--- |
8841 |
SDISelAsmOperandInfo &OpInfo, |
--- |
| 8842 |
SDISelAsmOperandInfo &RefOpInfo) { |
--- |
8842 |
SDISelAsmOperandInfo &RefOpInfo) { |
--- |
| 8843 |
LLVMContext &Context = *DAG.getContext(); |
0 |
8843 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 8844 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
8844 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 8845 |
|
--- |
8845 |
|
--- |
| 8846 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
8846 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 8847 |
SmallVector Regs; |
0 |
8847 |
SmallVector Regs; |
0 |
| 8848 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
8848 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
| 8849 |
|
--- |
8849 |
|
--- |
| 8850 |
// No work to do for memory/address operands. |
--- |
8850 |
// No work to do for memory/address operands. |
--- |
| 8851 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory || |
0 |
8851 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory || |
0 |
| 8852 |
OpInfo.ConstraintType == TargetLowering::C_Address) |
0 |
8852 |
OpInfo.ConstraintType == TargetLowering::C_Address) |
0 |
| 8853 |
return std::nullopt; |
0 |
8853 |
return std::nullopt; |
0 |
| 8854 |
|
--- |
8854 |
|
--- |
| 8855 |
// If this is a constraint for a single physreg, or a constraint for a |
--- |
8855 |
// If this is a constraint for a single physreg, or a constraint for a |
--- |
| 8856 |
// register class, find it. |
--- |
8856 |
// register class, find it. |
--- |
| 8857 |
unsigned AssignedReg; |
--- |
8857 |
unsigned AssignedReg; |
--- |
| 8858 |
const TargetRegisterClass *RC; |
--- |
8858 |
const TargetRegisterClass *RC; |
--- |
| 8859 |
std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( |
0 |
8859 |
std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( |
0 |
| 8860 |
&TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT); |
0 |
8860 |
&TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT); |
0 |
| 8861 |
// RC is unset only on failure. Return immediately. |
--- |
8861 |
// RC is unset only on failure. Return immediately. |
--- |
| 8862 |
if (!RC) |
0 |
8862 |
if (!RC) |
0 |
| 8863 |
return std::nullopt; |
0 |
8863 |
return std::nullopt; |
0 |
| 8864 |
|
--- |
8864 |
|
--- |
| 8865 |
// Get the actual register value type. This is important, because the user |
--- |
8865 |
// Get the actual register value type. This is important, because the user |
--- |
| 8866 |
// may have asked for (e.g.) the AX register in i32 type. We need to |
--- |
8866 |
// may have asked for (e.g.) the AX register in i32 type. We need to |
--- |
| 8867 |
// remember that AX is actually i16 to get the right extension. |
--- |
8867 |
// remember that AX is actually i16 to get the right extension. |
--- |
| 8868 |
const MVT RegVT = *TRI.legalclasstypes_begin(*RC); |
0 |
8868 |
const MVT RegVT = *TRI.legalclasstypes_begin(*RC); |
0 |
| 8869 |
|
--- |
8869 |
|
--- |
| 8870 |
if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { |
0 |
8870 |
if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { |
0 |
| 8871 |
// If this is an FP operand in an integer register (or visa versa), or more |
--- |
8871 |
// If this is an FP operand in an integer register (or visa versa), or more |
--- |
| 8872 |
// generally if the operand value disagrees with the register class we plan |
--- |
8872 |
// generally if the operand value disagrees with the register class we plan |
--- |
| 8873 |
// to stick it in, fix the operand type. |
--- |
8873 |
// to stick it in, fix the operand type. |
--- |
| 8874 |
// |
--- |
8874 |
// |
--- |
| 8875 |
// If this is an input value, the bitcast to the new type is done now. |
--- |
8875 |
// If this is an input value, the bitcast to the new type is done now. |
--- |
| 8876 |
// Bitcast for output value is done at the end of visitInlineAsm(). |
--- |
8876 |
// Bitcast for output value is done at the end of visitInlineAsm(). |
--- |
| 8877 |
if ((OpInfo.Type == InlineAsm::isOutput || |
0 |
8877 |
if ((OpInfo.Type == InlineAsm::isOutput || |
0 |
| 8878 |
OpInfo.Type == InlineAsm::isInput) && |
0 |
8878 |
OpInfo.Type == InlineAsm::isInput) && |
0 |
| 8879 |
!TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) { |
0 |
8879 |
!TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) { |
0 |
| 8880 |
// Try to convert to the first EVT that the reg class contains. If the |
--- |
8880 |
// Try to convert to the first EVT that the reg class contains. If the |
--- |
| 8881 |
// types are identical size, use a bitcast to convert (e.g. two differing |
--- |
8881 |
// types are identical size, use a bitcast to convert (e.g. two differing |
--- |
| 8882 |
// vector types). Note: output bitcast is done at the end of |
--- |
8882 |
// vector types). Note: output bitcast is done at the end of |
--- |
| 8883 |
// visitInlineAsm(). |
--- |
8883 |
// visitInlineAsm(). |
--- |
| 8884 |
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { |
0 |
8884 |
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { |
0 |
| 8885 |
// Exclude indirect inputs while they are unsupported because the code |
--- |
8885 |
// Exclude indirect inputs while they are unsupported because the code |
--- |
| 8886 |
// to perform the load is missing and thus OpInfo.CallOperand still |
--- |
8886 |
// to perform the load is missing and thus OpInfo.CallOperand still |
--- |
| 8887 |
// refers to the input address rather than the pointed-to value. |
--- |
8887 |
// refers to the input address rather than the pointed-to value. |
--- |
| 8888 |
if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect) |
0 |
8888 |
if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect) |
0 |
| 8889 |
OpInfo.CallOperand = |
0 |
8889 |
OpInfo.CallOperand = |
0 |
| 8890 |
DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); |
0 |
8890 |
DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); |
0 |
| 8891 |
OpInfo.ConstraintVT = RegVT; |
0 |
8891 |
OpInfo.ConstraintVT = RegVT; |
0 |
| 8892 |
// If the operand is an FP value and we want it in integer registers, |
--- |
8892 |
// If the operand is an FP value and we want it in integer registers, |
--- |
| 8893 |
// use the corresponding integer type. This turns an f64 value into |
--- |
8893 |
// use the corresponding integer type. This turns an f64 value into |
--- |
| 8894 |
// i64, which can be passed with two i32 values on a 32-bit machine. |
--- |
8894 |
// i64, which can be passed with two i32 values on a 32-bit machine. |
--- |
| 8895 |
} else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { |
0 |
8895 |
} else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { |
0 |
| 8896 |
MVT VT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); |
0 |
8896 |
MVT VT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); |
0 |
| 8897 |
if (OpInfo.Type == InlineAsm::isInput) |
0 |
8897 |
if (OpInfo.Type == InlineAsm::isInput) |
0 |
| 8898 |
OpInfo.CallOperand = |
0 |
8898 |
OpInfo.CallOperand = |
0 |
| 8899 |
DAG.getNode(ISD::BITCAST, DL, VT, OpInfo.CallOperand); |
0 |
8899 |
DAG.getNode(ISD::BITCAST, DL, VT, OpInfo.CallOperand); |
0 |
| 8900 |
OpInfo.ConstraintVT = VT; |
0 |
8900 |
OpInfo.ConstraintVT = VT; |
0 |
| 8901 |
} |
--- |
8901 |
} |
--- |
| 8902 |
} |
--- |
8902 |
} |
--- |
| 8903 |
} |
--- |
8903 |
} |
--- |
| 8904 |
|
--- |
8904 |
|
--- |
| 8905 |
// No need to allocate a matching input constraint since the constraint it's |
--- |
8905 |
// No need to allocate a matching input constraint since the constraint it's |
--- |
| 8906 |
// matching to has already been allocated. |
--- |
8906 |
// matching to has already been allocated. |
--- |
| 8907 |
if (OpInfo.isMatchingInputConstraint()) |
0 |
8907 |
if (OpInfo.isMatchingInputConstraint()) |
0 |
| 8908 |
return std::nullopt; |
0 |
8908 |
return std::nullopt; |
0 |
| 8909 |
|
--- |
8909 |
|
--- |
| 8910 |
EVT ValueVT = OpInfo.ConstraintVT; |
0 |
8910 |
EVT ValueVT = OpInfo.ConstraintVT; |
0 |
| 8911 |
if (OpInfo.ConstraintVT == MVT::Other) |
0 |
8911 |
if (OpInfo.ConstraintVT == MVT::Other) |
0 |
| 8912 |
ValueVT = RegVT; |
0 |
8912 |
ValueVT = RegVT; |
0 |
| 8913 |
|
--- |
8913 |
|
--- |
| 8914 |
// Initialize NumRegs. |
--- |
8914 |
// Initialize NumRegs. |
--- |
| 8915 |
unsigned NumRegs = 1; |
0 |
8915 |
unsigned NumRegs = 1; |
0 |
| 8916 |
if (OpInfo.ConstraintVT != MVT::Other) |
0 |
8916 |
if (OpInfo.ConstraintVT != MVT::Other) |
0 |
| 8917 |
NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT, RegVT); |
0 |
8917 |
NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT, RegVT); |
0 |
| 8918 |
|
--- |
8918 |
|
--- |
| 8919 |
// If this is a constraint for a specific physical register, like {r17}, |
--- |
8919 |
// If this is a constraint for a specific physical register, like {r17}, |
--- |
| 8920 |
// assign it now. |
--- |
8920 |
// assign it now. |
--- |
| 8921 |
|
--- |
8921 |
|
--- |
| 8922 |
// If this associated to a specific register, initialize iterator to correct |
--- |
8922 |
// If this associated to a specific register, initialize iterator to correct |
--- |
| 8923 |
// place. If virtual, make sure we have enough registers |
--- |
8923 |
// place. If virtual, make sure we have enough registers |
--- |
| 8924 |
|
--- |
8924 |
|
--- |
| 8925 |
// Initialize iterator if necessary |
--- |
8925 |
// Initialize iterator if necessary |
--- |
| 8926 |
TargetRegisterClass::iterator I = RC->begin(); |
0 |
8926 |
TargetRegisterClass::iterator I = RC->begin(); |
0 |
| 8927 |
MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
0 |
8927 |
MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
0 |
| 8928 |
|
--- |
8928 |
|
--- |
| 8929 |
// Do not check for single registers. |
--- |
8929 |
// Do not check for single registers. |
--- |
| 8930 |
if (AssignedReg) { |
0 |
8930 |
if (AssignedReg) { |
0 |
| 8931 |
I = std::find(I, RC->end(), AssignedReg); |
0 |
8931 |
I = std::find(I, RC->end(), AssignedReg); |
0 |
| 8932 |
if (I == RC->end()) { |
0 |
8932 |
if (I == RC->end()) { |
0 |
| 8933 |
// RC does not contain the selected register, which indicates a |
--- |
8933 |
// RC does not contain the selected register, which indicates a |
--- |
| 8934 |
// mismatch between the register and the required type/bitwidth. |
--- |
8934 |
// mismatch between the register and the required type/bitwidth. |
--- |
| 8935 |
return {AssignedReg}; |
0 |
8935 |
return {AssignedReg}; |
0 |
| 8936 |
} |
--- |
8936 |
} |
--- |
| 8937 |
} |
--- |
8937 |
} |
--- |
| 8938 |
|
--- |
8938 |
|
--- |
| 8939 |
for (; NumRegs; --NumRegs, ++I) { |
0 |
8939 |
for (; NumRegs; --NumRegs, ++I) { |
0 |
| 8940 |
assert(I != RC->end() && "Ran out of registers to allocate!"); |
0 |
8940 |
assert(I != RC->end() && "Ran out of registers to allocate!"); |
0 |
| 8941 |
Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); |
0 |
8941 |
Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); |
0 |
| 8942 |
Regs.push_back(R); |
0 |
8942 |
Regs.push_back(R); |
0 |
| 8943 |
} |
--- |
8943 |
} |
--- |
| 8944 |
|
--- |
8944 |
|
--- |
| 8945 |
OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); |
0 |
8945 |
OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); |
0 |
| 8946 |
return std::nullopt; |
0 |
8946 |
return std::nullopt; |
0 |
| 8947 |
} |
0 |
8947 |
} |
0 |
| 8948 |
|
--- |
8948 |
|
--- |
| 8949 |
static unsigned |
--- |
8949 |
static unsigned |
--- |
| 8950 |
findMatchingInlineAsmOperand(unsigned OperandNo, |
0 |
8950 |
findMatchingInlineAsmOperand(unsigned OperandNo, |
0 |
| 8951 |
const std::vector &AsmNodeOperands) { |
--- |
8951 |
const std::vector &AsmNodeOperands) { |
--- |
| 8952 |
// Scan until we find the definition we already emitted of this operand. |
--- |
8952 |
// Scan until we find the definition we already emitted of this operand. |
--- |
| 8953 |
unsigned CurOp = InlineAsm::Op_FirstOperand; |
0 |
8953 |
unsigned CurOp = InlineAsm::Op_FirstOperand; |
0 |
| 8954 |
for (; OperandNo; --OperandNo) { |
0 |
8954 |
for (; OperandNo; --OperandNo) { |
0 |
| 8955 |
// Advance to the next operand. |
--- |
8955 |
// Advance to the next operand. |
--- |
| 8956 |
unsigned OpFlag = |
--- |
8956 |
unsigned OpFlag = |
--- |
| 8957 |
cast(AsmNodeOperands[CurOp])->getZExtValue(); |
0 |
8957 |
cast(AsmNodeOperands[CurOp])->getZExtValue(); |
0 |
| 8958 |
assert((InlineAsm::isRegDefKind(OpFlag) || |
0 |
8958 |
assert((InlineAsm::isRegDefKind(OpFlag) || |
0 |
| 8959 |
InlineAsm::isRegDefEarlyClobberKind(OpFlag) || |
--- |
8959 |
InlineAsm::isRegDefEarlyClobberKind(OpFlag) || |
--- |
| 8960 |
InlineAsm::isMemKind(OpFlag)) && |
--- |
8960 |
InlineAsm::isMemKind(OpFlag)) && |
--- |
| 8961 |
"Skipped past definitions?"); |
--- |
8961 |
"Skipped past definitions?"); |
--- |
| 8962 |
CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1; |
0 |
8962 |
CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1; |
0 |
| 8963 |
} |
--- |
8963 |
} |
--- |
| 8964 |
return CurOp; |
0 |
8964 |
return CurOp; |
0 |
| 8965 |
} |
--- |
8965 |
} |
--- |
| 8966 |
|
--- |
8966 |
|
--- |
| 8967 |
namespace { |
--- |
8967 |
namespace { |
--- |
| 8968 |
|
--- |
8968 |
|
--- |
| 8969 |
class ExtraFlags { |
--- |
8969 |
class ExtraFlags { |
--- |
| 8970 |
unsigned Flags = 0; |
--- |
8970 |
unsigned Flags = 0; |
--- |
| 8971 |
|
--- |
8971 |
|
--- |
| 8972 |
public: |
--- |
8972 |
public: |
--- |
| 8973 |
explicit ExtraFlags(const CallBase &Call) { |
0 |
8973 |
explicit ExtraFlags(const CallBase &Call) { |
0 |
| 8974 |
const InlineAsm *IA = cast(Call.getCalledOperand()); |
0 |
8974 |
const InlineAsm *IA = cast(Call.getCalledOperand()); |
0 |
| 8975 |
if (IA->hasSideEffects()) |
0 |
8975 |
if (IA->hasSideEffects()) |
0 |
| 8976 |
Flags |= InlineAsm::Extra_HasSideEffects; |
0 |
8976 |
Flags |= InlineAsm::Extra_HasSideEffects; |
0 |
| 8977 |
if (IA->isAlignStack()) |
0 |
8977 |
if (IA->isAlignStack()) |
0 |
| 8978 |
Flags |= InlineAsm::Extra_IsAlignStack; |
0 |
8978 |
Flags |= InlineAsm::Extra_IsAlignStack; |
0 |
| 8979 |
if (Call.isConvergent()) |
0 |
8979 |
if (Call.isConvergent()) |
0 |
| 8980 |
Flags |= InlineAsm::Extra_IsConvergent; |
0 |
8980 |
Flags |= InlineAsm::Extra_IsConvergent; |
0 |
| 8981 |
Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect; |
0 |
8981 |
Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect; |
0 |
| 8982 |
} |
0 |
8982 |
} |
0 |
| 8983 |
|
--- |
8983 |
|
--- |
| 8984 |
void update(const TargetLowering::AsmOperandInfo &OpInfo) { |
0 |
8984 |
void update(const TargetLowering::AsmOperandInfo &OpInfo) { |
0 |
| 8985 |
// Ideally, we would only check against memory constraints. However, the |
--- |
8985 |
// Ideally, we would only check against memory constraints. However, the |
--- |
| 8986 |
// meaning of an Other constraint can be target-specific and we can't easily |
--- |
8986 |
// meaning of an Other constraint can be target-specific and we can't easily |
--- |
| 8987 |
// reason about it. Therefore, be conservative and set MayLoad/MayStore |
--- |
8987 |
// reason about it. Therefore, be conservative and set MayLoad/MayStore |
--- |
| 8988 |
// for Other constraints as well. |
--- |
8988 |
// for Other constraints as well. |
--- |
| 8989 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory || |
0 |
8989 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory || |
0 |
| 8990 |
OpInfo.ConstraintType == TargetLowering::C_Other) { |
0 |
8990 |
OpInfo.ConstraintType == TargetLowering::C_Other) { |
0 |
| 8991 |
if (OpInfo.Type == InlineAsm::isInput) |
0 |
8991 |
if (OpInfo.Type == InlineAsm::isInput) |
0 |
| 8992 |
Flags |= InlineAsm::Extra_MayLoad; |
0 |
8992 |
Flags |= InlineAsm::Extra_MayLoad; |
0 |
| 8993 |
else if (OpInfo.Type == InlineAsm::isOutput) |
0 |
8993 |
else if (OpInfo.Type == InlineAsm::isOutput) |
0 |
| 8994 |
Flags |= InlineAsm::Extra_MayStore; |
0 |
8994 |
Flags |= InlineAsm::Extra_MayStore; |
0 |
| 8995 |
else if (OpInfo.Type == InlineAsm::isClobber) |
0 |
8995 |
else if (OpInfo.Type == InlineAsm::isClobber) |
0 |
| 8996 |
Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); |
0 |
8996 |
Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); |
0 |
| 8997 |
} |
--- |
8997 |
} |
--- |
| 8998 |
} |
0 |
8998 |
} |
0 |
| 8999 |
|
--- |
8999 |
|
--- |
| 9000 |
unsigned get() const { return Flags; } |
0 |
9000 |
unsigned get() const { return Flags; } |
0 |
| 9001 |
}; |
--- |
9001 |
}; |
--- |
| 9002 |
|
--- |
9002 |
|
--- |
| 9003 |
} // end anonymous namespace |
--- |
9003 |
} // end anonymous namespace |
--- |
| 9004 |
|
--- |
9004 |
|
--- |
| 9005 |
static bool isFunction(SDValue Op) { |
0 |
9005 |
static bool isFunction(SDValue Op) { |
0 |
| 9006 |
if (Op && Op.getOpcode() == ISD::GlobalAddress) { |
0 |
9006 |
if (Op && Op.getOpcode() == ISD::GlobalAddress) { |
0 |
| 9007 |
if (auto *GA = dyn_cast(Op)) { |
0 |
9007 |
if (auto *GA = dyn_cast(Op)) { |
0 |
| 9008 |
auto Fn = dyn_cast_or_null(GA->getGlobal()); |
0 |
9008 |
auto Fn = dyn_cast_or_null(GA->getGlobal()); |
0 |
| 9009 |
|
--- |
9009 |
|
--- |
| 9010 |
// In normal "call dllimport func" instruction (non-inlineasm) it force |
--- |
9010 |
// In normal "call dllimport func" instruction (non-inlineasm) it force |
--- |
| 9011 |
// indirect access by specifing call opcode. And usually specially print |
--- |
9011 |
// indirect access by specifing call opcode. And usually specially print |
--- |
| 9012 |
// asm with indirect symbol (i.g: "*") according to opcode. Inline asm can |
--- |
9012 |
// asm with indirect symbol (i.g: "*") according to opcode. Inline asm can |
--- |
| 9013 |
// not do in this way now. (In fact, this is similar with "Data Access" |
--- |
9013 |
// not do in this way now. (In fact, this is similar with "Data Access" |
--- |
| 9014 |
// action). So here we ignore dllimport function. |
--- |
9014 |
// action). So here we ignore dllimport function. |
--- |
| 9015 |
if (Fn && !Fn->hasDLLImportStorageClass()) |
0 |
9015 |
if (Fn && !Fn->hasDLLImportStorageClass()) |
0 |
| 9016 |
return true; |
0 |
9016 |
return true; |
0 |
| 9017 |
} |
--- |
9017 |
} |
--- |
| 9018 |
} |
--- |
9018 |
} |
--- |
| 9019 |
return false; |
0 |
9019 |
return false; |
0 |
| 9020 |
} |
--- |
9020 |
} |
--- |
| 9021 |
|
--- |
9021 |
|
--- |
| 9022 |
/// visitInlineAsm - Handle a call to an InlineAsm object. |
--- |
9022 |
/// visitInlineAsm - Handle a call to an InlineAsm object. |
--- |
| 9023 |
void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, |
0 |
9023 |
void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, |
0 |
| 9024 |
const BasicBlock *EHPadBB) { |
--- |
9024 |
const BasicBlock *EHPadBB) { |
--- |
| 9025 |
const InlineAsm *IA = cast(Call.getCalledOperand()); |
0 |
9025 |
const InlineAsm *IA = cast(Call.getCalledOperand()); |
0 |
| 9026 |
|
--- |
9026 |
|
--- |
| 9027 |
/// ConstraintOperands - Information about all of the constraints. |
--- |
9027 |
/// ConstraintOperands - Information about all of the constraints. |
--- |
| 9028 |
SmallVector ConstraintOperands; |
0 |
9028 |
SmallVector ConstraintOperands; |
0 |
| 9029 |
|
--- |
9029 |
|
--- |
| 9030 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
9030 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 9031 |
TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints( |
0 |
9031 |
TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints( |
0 |
| 9032 |
DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), Call); |
0 |
9032 |
DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), Call); |
0 |
| 9033 |
|
--- |
9033 |
|
--- |
| 9034 |
// First Pass: Calculate HasSideEffects and ExtraFlags (AlignStack, |
--- |
9034 |
// First Pass: Calculate HasSideEffects and ExtraFlags (AlignStack, |
--- |
| 9035 |
// AsmDialect, MayLoad, MayStore). |
--- |
9035 |
// AsmDialect, MayLoad, MayStore). |
--- |
| 9036 |
bool HasSideEffect = IA->hasSideEffects(); |
0 |
9036 |
bool HasSideEffect = IA->hasSideEffects(); |
0 |
| 9037 |
ExtraFlags ExtraInfo(Call); |
0 |
9037 |
ExtraFlags ExtraInfo(Call); |
0 |
| 9038 |
|
--- |
9038 |
|
--- |
| 9039 |
for (auto &T : TargetConstraints) { |
0 |
9039 |
for (auto &T : TargetConstraints) { |
0 |
| 9040 |
ConstraintOperands.push_back(SDISelAsmOperandInfo(T)); |
0 |
9040 |
ConstraintOperands.push_back(SDISelAsmOperandInfo(T)); |
0 |
| 9041 |
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); |
0 |
9041 |
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); |
0 |
| 9042 |
|
--- |
9042 |
|
--- |
| 9043 |
if (OpInfo.CallOperandVal) |
0 |
9043 |
if (OpInfo.CallOperandVal) |
0 |
| 9044 |
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); |
0 |
9044 |
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); |
0 |
| 9045 |
|
--- |
9045 |
|
--- |
| 9046 |
if (!HasSideEffect) |
0 |
9046 |
if (!HasSideEffect) |
0 |
| 9047 |
HasSideEffect = OpInfo.hasMemory(TLI); |
0 |
9047 |
HasSideEffect = OpInfo.hasMemory(TLI); |
0 |
| 9048 |
|
--- |
9048 |
|
--- |
| 9049 |
// Determine if this InlineAsm MayLoad or MayStore based on the constraints. |
--- |
9049 |
// Determine if this InlineAsm MayLoad or MayStore based on the constraints. |
--- |
| 9050 |
// FIXME: Could we compute this on OpInfo rather than T? |
--- |
9050 |
// FIXME: Could we compute this on OpInfo rather than T? |
--- |
| 9051 |
|
--- |
9051 |
|
--- |
| 9052 |
// Compute the constraint code and ConstraintType to use. |
--- |
9052 |
// Compute the constraint code and ConstraintType to use. |
--- |
| 9053 |
TLI.ComputeConstraintToUse(T, SDValue()); |
0 |
9053 |
TLI.ComputeConstraintToUse(T, SDValue()); |
0 |
| 9054 |
|
--- |
9054 |
|
--- |
| 9055 |
if (T.ConstraintType == TargetLowering::C_Immediate && |
0 |
9055 |
if (T.ConstraintType == TargetLowering::C_Immediate && |
0 |
| 9056 |
OpInfo.CallOperand && !isa(OpInfo.CallOperand)) |
0 |
9056 |
OpInfo.CallOperand && !isa(OpInfo.CallOperand)) |
0 |
| 9057 |
// We've delayed emitting a diagnostic like the "n" constraint because |
--- |
9057 |
// We've delayed emitting a diagnostic like the "n" constraint because |
--- |
| 9058 |
// inlining could cause an integer showing up. |
--- |
9058 |
// inlining could cause an integer showing up. |
--- |
| 9059 |
return emitInlineAsmError(Call, "constraint '" + Twine(T.ConstraintCode) + |
0 |
9059 |
return emitInlineAsmError(Call, "constraint '" + Twine(T.ConstraintCode) + |
0 |
| 9060 |
"' expects an integer constant " |
--- |
9060 |
"' expects an integer constant " |
--- |
| 9061 |
"expression"); |
0 |
9061 |
"expression"); |
0 |
| 9062 |
|
--- |
9062 |
|
--- |
| 9063 |
ExtraInfo.update(T); |
0 |
9063 |
ExtraInfo.update(T); |
0 |
| 9064 |
} |
--- |
9064 |
} |
--- |
| 9065 |
|
--- |
9065 |
|
--- |
| 9066 |
// We won't need to flush pending loads if this asm doesn't touch |
--- |
9066 |
// We won't need to flush pending loads if this asm doesn't touch |
--- |
| 9067 |
// memory and is nonvolatile. |
--- |
9067 |
// memory and is nonvolatile. |
--- |
| 9068 |
SDValue Glue, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot(); |
0 |
9068 |
SDValue Glue, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot(); |
0 |
| 9069 |
|
--- |
9069 |
|
--- |
| 9070 |
bool EmitEHLabels = isa(Call); |
0 |
9070 |
bool EmitEHLabels = isa(Call); |
0 |
| 9071 |
if (EmitEHLabels) { |
0 |
9071 |
if (EmitEHLabels) { |
0 |
| 9072 |
assert(EHPadBB && "InvokeInst must have an EHPadBB"); |
0 |
9072 |
assert(EHPadBB && "InvokeInst must have an EHPadBB"); |
0 |
| 9073 |
} |
--- |
9073 |
} |
--- |
| 9074 |
bool IsCallBr = isa(Call); |
0 |
9074 |
bool IsCallBr = isa(Call); |
0 |
| 9075 |
|
--- |
9075 |
|
--- |
| 9076 |
if (IsCallBr || EmitEHLabels) { |
0 |
9076 |
if (IsCallBr || EmitEHLabels) { |
0 |
| 9077 |
// If this is a callbr or invoke we need to flush pending exports since |
--- |
9077 |
// If this is a callbr or invoke we need to flush pending exports since |
--- |
| 9078 |
// inlineasm_br and invoke are terminators. |
--- |
9078 |
// inlineasm_br and invoke are terminators. |
--- |
| 9079 |
// We need to do this before nodes are glued to the inlineasm_br node. |
--- |
9079 |
// We need to do this before nodes are glued to the inlineasm_br node. |
--- |
| 9080 |
Chain = getControlRoot(); |
0 |
9080 |
Chain = getControlRoot(); |
0 |
| 9081 |
} |
--- |
9081 |
} |
--- |
| 9082 |
|
--- |
9082 |
|
--- |
| 9083 |
MCSymbol *BeginLabel = nullptr; |
0 |
9083 |
MCSymbol *BeginLabel = nullptr; |
0 |
| 9084 |
if (EmitEHLabels) { |
0 |
9084 |
if (EmitEHLabels) { |
0 |
| 9085 |
Chain = lowerStartEH(Chain, EHPadBB, BeginLabel); |
0 |
9085 |
Chain = lowerStartEH(Chain, EHPadBB, BeginLabel); |
0 |
| 9086 |
} |
--- |
9086 |
} |
--- |
| 9087 |
|
--- |
9087 |
|
--- |
| 9088 |
int OpNo = -1; |
0 |
9088 |
int OpNo = -1; |
0 |
| 9089 |
SmallVector AsmStrs; |
0 |
9089 |
SmallVector AsmStrs; |
0 |
| 9090 |
IA->collectAsmStrs(AsmStrs); |
0 |
9090 |
IA->collectAsmStrs(AsmStrs); |
0 |
| 9091 |
|
--- |
9091 |
|
--- |
| 9092 |
// Second pass over the constraints: compute which constraint option to use. |
--- |
9092 |
// Second pass over the constraints: compute which constraint option to use. |
--- |
| 9093 |
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { |
0 |
9093 |
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { |
0 |
| 9094 |
if (OpInfo.hasArg() || OpInfo.Type == InlineAsm::isOutput) |
0 |
9094 |
if (OpInfo.hasArg() || OpInfo.Type == InlineAsm::isOutput) |
0 |
| 9095 |
OpNo++; |
0 |
9095 |
OpNo++; |
0 |
| 9096 |
|
--- |
9096 |
|
--- |
| 9097 |
// If this is an output operand with a matching input operand, look up the |
--- |
9097 |
// If this is an output operand with a matching input operand, look up the |
--- |
| 9098 |
// matching input. If their types mismatch, e.g. one is an integer, the |
--- |
9098 |
// matching input. If their types mismatch, e.g. one is an integer, the |
--- |
| 9099 |
// other is floating point, or their sizes are different, flag it as an |
--- |
9099 |
// other is floating point, or their sizes are different, flag it as an |
--- |
| 9100 |
// error. |
--- |
9100 |
// error. |
--- |
| 9101 |
if (OpInfo.hasMatchingInput()) { |
0 |
9101 |
if (OpInfo.hasMatchingInput()) { |
0 |
| 9102 |
SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; |
0 |
9102 |
SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; |
0 |
| 9103 |
patchMatchingInput(OpInfo, Input, DAG); |
0 |
9103 |
patchMatchingInput(OpInfo, Input, DAG); |
0 |
| 9104 |
} |
--- |
9104 |
} |
--- |
| 9105 |
|
--- |
9105 |
|
--- |
| 9106 |
// Compute the constraint code and ConstraintType to use. |
--- |
9106 |
// Compute the constraint code and ConstraintType to use. |
--- |
| 9107 |
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); |
0 |
9107 |
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); |
0 |
| 9108 |
|
--- |
9108 |
|
--- |
| 9109 |
if ((OpInfo.ConstraintType == TargetLowering::C_Memory && |
0 |
9109 |
if ((OpInfo.ConstraintType == TargetLowering::C_Memory && |
0 |
| 9110 |
OpInfo.Type == InlineAsm::isClobber) || |
0 |
9110 |
OpInfo.Type == InlineAsm::isClobber) || |
0 |
| 9111 |
OpInfo.ConstraintType == TargetLowering::C_Address) |
0 |
9111 |
OpInfo.ConstraintType == TargetLowering::C_Address) |
0 |
| 9112 |
continue; |
0 |
9112 |
continue; |
0 |
| 9113 |
|
--- |
9113 |
|
--- |
| 9114 |
// In Linux PIC model, there are 4 cases about value/label addressing: |
--- |
9114 |
// In Linux PIC model, there are 4 cases about value/label addressing: |
--- |
| 9115 |
// |
--- |
9115 |
// |
--- |
| 9116 |
// 1: Function call or Label jmp inside the module. |
--- |
9116 |
// 1: Function call or Label jmp inside the module. |
--- |
| 9117 |
// 2: Data access (such as global variable, static variable) inside module. |
--- |
9117 |
// 2: Data access (such as global variable, static variable) inside module. |
--- |
| 9118 |
// 3: Function call or Label jmp outside the module. |
--- |
9118 |
// 3: Function call or Label jmp outside the module. |
--- |
| 9119 |
// 4: Data access (such as global variable) outside the module. |
--- |
9119 |
// 4: Data access (such as global variable) outside the module. |
--- |
| 9120 |
// |
--- |
9120 |
// |
--- |
| 9121 |
// Due to current llvm inline asm architecture designed to not "recognize" |
--- |
9121 |
// Due to current llvm inline asm architecture designed to not "recognize" |
--- |
| 9122 |
// the asm code, there are quite troubles for us to treat mem addressing |
--- |
9122 |
// the asm code, there are quite troubles for us to treat mem addressing |
--- |
| 9123 |
// differently for same value/adress used in different instuctions. |
--- |
9123 |
// differently for same value/adress used in different instuctions. |
--- |
| 9124 |
// For example, in pic model, call a func may in plt way or direclty |
--- |
9124 |
// For example, in pic model, call a func may in plt way or direclty |
--- |
| 9125 |
// pc-related, but lea/mov a function adress may use got. |
--- |
9125 |
// pc-related, but lea/mov a function adress may use got. |
--- |
| 9126 |
// |
--- |
9126 |
// |
--- |
| 9127 |
// Here we try to "recognize" function call for the case 1 and case 3 in |
--- |
9127 |
// Here we try to "recognize" function call for the case 1 and case 3 in |
--- |
| 9128 |
// inline asm. And try to adjust the constraint for them. |
--- |
9128 |
// inline asm. And try to adjust the constraint for them. |
--- |
| 9129 |
// |
--- |
9129 |
// |
--- |
| 9130 |
// TODO: Due to current inline asm didn't encourage to jmp to the outsider |
--- |
9130 |
// TODO: Due to current inline asm didn't encourage to jmp to the outsider |
--- |
| 9131 |
// label, so here we don't handle jmp function label now, but we need to |
--- |
9131 |
// label, so here we don't handle jmp function label now, but we need to |
--- |
| 9132 |
// enhance it (especilly in PIC model) if we meet meaningful requirements. |
--- |
9132 |
// enhance it (especilly in PIC model) if we meet meaningful requirements. |
--- |
| 9133 |
if (OpInfo.isIndirect && isFunction(OpInfo.CallOperand) && |
0 |
9133 |
if (OpInfo.isIndirect && isFunction(OpInfo.CallOperand) && |
0 |
| 9134 |
TLI.isInlineAsmTargetBranch(AsmStrs, OpNo) && |
0 |
9134 |
TLI.isInlineAsmTargetBranch(AsmStrs, OpNo) && |
0 |
| 9135 |
TM.getCodeModel() != CodeModel::Large) { |
0 |
9135 |
TM.getCodeModel() != CodeModel::Large) { |
0 |
| 9136 |
OpInfo.isIndirect = false; |
0 |
9136 |
OpInfo.isIndirect = false; |
0 |
| 9137 |
OpInfo.ConstraintType = TargetLowering::C_Address; |
0 |
9137 |
OpInfo.ConstraintType = TargetLowering::C_Address; |
0 |
| 9138 |
} |
--- |
9138 |
} |
--- |
| 9139 |
|
--- |
9139 |
|
--- |
| 9140 |
// If this is a memory input, and if the operand is not indirect, do what we |
--- |
9140 |
// If this is a memory input, and if the operand is not indirect, do what we |
--- |
| 9141 |
// need to provide an address for the memory input. |
--- |
9141 |
// need to provide an address for the memory input. |
--- |
| 9142 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory && |
0 |
9142 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory && |
0 |
| 9143 |
!OpInfo.isIndirect) { |
0 |
9143 |
!OpInfo.isIndirect) { |
0 |
| 9144 |
assert((OpInfo.isMultipleAlternative || |
0 |
9144 |
assert((OpInfo.isMultipleAlternative || |
0 |
| 9145 |
(OpInfo.Type == InlineAsm::isInput)) && |
--- |
9145 |
(OpInfo.Type == InlineAsm::isInput)) && |
--- |
| 9146 |
"Can only indirectify direct input operands!"); |
--- |
9146 |
"Can only indirectify direct input operands!"); |
--- |
| 9147 |
|
--- |
9147 |
|
--- |
| 9148 |
// Memory operands really want the address of the value. |
--- |
9148 |
// Memory operands really want the address of the value. |
--- |
| 9149 |
Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG); |
0 |
9149 |
Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG); |
0 |
| 9150 |
|
--- |
9150 |
|
--- |
| 9151 |
// There is no longer a Value* corresponding to this operand. |
--- |
9151 |
// There is no longer a Value* corresponding to this operand. |
--- |
| 9152 |
OpInfo.CallOperandVal = nullptr; |
0 |
9152 |
OpInfo.CallOperandVal = nullptr; |
0 |
| 9153 |
|
--- |
9153 |
|
--- |
| 9154 |
// It is now an indirect operand. |
--- |
9154 |
// It is now an indirect operand. |
--- |
| 9155 |
OpInfo.isIndirect = true; |
0 |
9155 |
OpInfo.isIndirect = true; |
0 |
| 9156 |
} |
--- |
9156 |
} |
--- |
| 9157 |
|
--- |
9157 |
|
--- |
| 9158 |
} |
--- |
9158 |
} |
--- |
| 9159 |
|
--- |
9159 |
|
--- |
| 9160 |
// AsmNodeOperands - The operands for the ISD::INLINEASM node. |
--- |
9160 |
// AsmNodeOperands - The operands for the ISD::INLINEASM node. |
--- |
| 9161 |
std::vector AsmNodeOperands; |
0 |
9161 |
std::vector AsmNodeOperands; |
0 |
| 9162 |
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain |
0 |
9162 |
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain |
0 |
| 9163 |
AsmNodeOperands.push_back(DAG.getTargetExternalSymbol( |
0 |
9163 |
AsmNodeOperands.push_back(DAG.getTargetExternalSymbol( |
0 |
| 9164 |
IA->getAsmString().c_str(), TLI.getProgramPointerTy(DAG.getDataLayout()))); |
0 |
9164 |
IA->getAsmString().c_str(), TLI.getProgramPointerTy(DAG.getDataLayout()))); |
0 |
| 9165 |
|
--- |
9165 |
|
--- |
| 9166 |
// If we have a !srcloc metadata node associated with it, we want to attach |
--- |
9166 |
// If we have a !srcloc metadata node associated with it, we want to attach |
--- |
| 9167 |
// this to the ultimately generated inline asm machineinstr. To do this, we |
--- |
9167 |
// this to the ultimately generated inline asm machineinstr. To do this, we |
--- |
| 9168 |
// pass in the third operand as this (potentially null) inline asm MDNode. |
--- |
9168 |
// pass in the third operand as this (potentially null) inline asm MDNode. |
--- |
| 9169 |
const MDNode *SrcLoc = Call.getMetadata("srcloc"); |
0 |
9169 |
const MDNode *SrcLoc = Call.getMetadata("srcloc"); |
0 |
| 9170 |
AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); |
0 |
9170 |
AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); |
0 |
| 9171 |
|
--- |
9171 |
|
--- |
| 9172 |
// Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore |
--- |
9172 |
// Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore |
--- |
| 9173 |
// bits as operand 3. |
--- |
9173 |
// bits as operand 3. |
--- |
| 9174 |
AsmNodeOperands.push_back(DAG.getTargetConstant( |
0 |
9174 |
AsmNodeOperands.push_back(DAG.getTargetConstant( |
0 |
| 9175 |
ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
9175 |
ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 9176 |
|
--- |
9176 |
|
--- |
| 9177 |
// Third pass: Loop over operands to prepare DAG-level operands.. As part of |
--- |
9177 |
// Third pass: Loop over operands to prepare DAG-level operands.. As part of |
--- |
| 9178 |
// this, assign virtual and physical registers for inputs and otput. |
--- |
9178 |
// this, assign virtual and physical registers for inputs and otput. |
--- |
| 9179 |
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { |
0 |
9179 |
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { |
0 |
| 9180 |
// Assign Registers. |
--- |
9180 |
// Assign Registers. |
--- |
| 9181 |
SDISelAsmOperandInfo &RefOpInfo = |
--- |
9181 |
SDISelAsmOperandInfo &RefOpInfo = |
--- |
| 9182 |
OpInfo.isMatchingInputConstraint() |
0 |
9182 |
OpInfo.isMatchingInputConstraint() |
0 |
| 9183 |
? ConstraintOperands[OpInfo.getMatchedOperand()] |
0 |
9183 |
? ConstraintOperands[OpInfo.getMatchedOperand()] |
0 |
| 9184 |
: OpInfo; |
0 |
9184 |
: OpInfo; |
0 |
| 9185 |
const auto RegError = |
--- |
9185 |
const auto RegError = |
--- |
| 9186 |
getRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo); |
0 |
9186 |
getRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo); |
0 |
| 9187 |
if (RegError) { |
0 |
9187 |
if (RegError) { |
0 |
| 9188 |
const MachineFunction &MF = DAG.getMachineFunction(); |
0 |
9188 |
const MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 9189 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
9189 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
| 9190 |
const char *RegName = TRI.getName(*RegError); |
0 |
9190 |
const char *RegName = TRI.getName(*RegError); |
0 |
| 9191 |
emitInlineAsmError(Call, "register '" + Twine(RegName) + |
0 |
9191 |
emitInlineAsmError(Call, "register '" + Twine(RegName) + |
0 |
| 9192 |
"' allocated for constraint '" + |
0 |
9192 |
"' allocated for constraint '" + |
0 |
| 9193 |
Twine(OpInfo.ConstraintCode) + |
0 |
9193 |
Twine(OpInfo.ConstraintCode) + |
0 |
| 9194 |
"' does not match required type"); |
0 |
9194 |
"' does not match required type"); |
0 |
| 9195 |
return; |
0 |
9195 |
return; |
0 |
| 9196 |
} |
--- |
9196 |
} |
--- |
| 9197 |
|
--- |
9197 |
|
--- |
| 9198 |
auto DetectWriteToReservedRegister = [&]() { |
0 |
9198 |
auto DetectWriteToReservedRegister = [&]() { |
0 |
| 9199 |
const MachineFunction &MF = DAG.getMachineFunction(); |
0 |
9199 |
const MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 9200 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
9200 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
| 9201 |
for (unsigned Reg : OpInfo.AssignedRegs.Regs) { |
0 |
9201 |
for (unsigned Reg : OpInfo.AssignedRegs.Regs) { |
0 |
| 9202 |
if (Register::isPhysicalRegister(Reg) && |
0 |
9202 |
if (Register::isPhysicalRegister(Reg) && |
0 |
| 9203 |
TRI.isInlineAsmReadOnlyReg(MF, Reg)) { |
0 |
9203 |
TRI.isInlineAsmReadOnlyReg(MF, Reg)) { |
0 |
| 9204 |
const char *RegName = TRI.getName(Reg); |
0 |
9204 |
const char *RegName = TRI.getName(Reg); |
0 |
| 9205 |
emitInlineAsmError(Call, "write to reserved register '" + |
0 |
9205 |
emitInlineAsmError(Call, "write to reserved register '" + |
0 |
| 9206 |
Twine(RegName) + "'"); |
0 |
9206 |
Twine(RegName) + "'"); |
0 |
| 9207 |
return true; |
0 |
9207 |
return true; |
0 |
| 9208 |
} |
--- |
9208 |
} |
--- |
| 9209 |
} |
--- |
9209 |
} |
--- |
| 9210 |
return false; |
0 |
9210 |
return false; |
0 |
| 9211 |
}; |
0 |
9211 |
}; |
0 |
| 9212 |
assert((OpInfo.ConstraintType != TargetLowering::C_Address || |
0 |
9212 |
assert((OpInfo.ConstraintType != TargetLowering::C_Address || |
0 |
| 9213 |
(OpInfo.Type == InlineAsm::isInput && |
--- |
9213 |
(OpInfo.Type == InlineAsm::isInput && |
--- |
| 9214 |
!OpInfo.isMatchingInputConstraint())) && |
--- |
9214 |
!OpInfo.isMatchingInputConstraint())) && |
--- |
| 9215 |
"Only address as input operand is allowed."); |
--- |
9215 |
"Only address as input operand is allowed."); |
--- |
| 9216 |
|
--- |
9216 |
|
--- |
| 9217 |
switch (OpInfo.Type) { |
0 |
9217 |
switch (OpInfo.Type) { |
0 |
| 9218 |
case InlineAsm::isOutput: |
0 |
9218 |
case InlineAsm::isOutput: |
0 |
| 9219 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory) { |
0 |
9219 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory) { |
0 |
| 9220 |
unsigned ConstraintID = |
--- |
9220 |
unsigned ConstraintID = |
--- |
| 9221 |
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); |
0 |
9221 |
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); |
0 |
| 9222 |
assert(ConstraintID != InlineAsm::Constraint_Unknown && |
0 |
9222 |
assert(ConstraintID != InlineAsm::Constraint_Unknown && |
0 |
| 9223 |
"Failed to convert memory constraint code to constraint id."); |
--- |
9223 |
"Failed to convert memory constraint code to constraint id."); |
--- |
| 9224 |
|
--- |
9224 |
|
--- |
| 9225 |
// Add information to the INLINEASM node to know about this output. |
--- |
9225 |
// Add information to the INLINEASM node to know about this output. |
--- |
| 9226 |
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); |
0 |
9226 |
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); |
0 |
| 9227 |
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); |
0 |
9227 |
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); |
0 |
| 9228 |
AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(), |
0 |
9228 |
AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(), |
0 |
| 9229 |
MVT::i32)); |
--- |
9229 |
MVT::i32)); |
--- |
| 9230 |
AsmNodeOperands.push_back(OpInfo.CallOperand); |
0 |
9230 |
AsmNodeOperands.push_back(OpInfo.CallOperand); |
0 |
| 9231 |
} else { |
--- |
9231 |
} else { |
--- |
| 9232 |
// Otherwise, this outputs to a register (directly for C_Register / |
--- |
9232 |
// Otherwise, this outputs to a register (directly for C_Register / |
--- |
| 9233 |
// C_RegisterClass, and a target-defined fashion for |
--- |
9233 |
// C_RegisterClass, and a target-defined fashion for |
--- |
| 9234 |
// C_Immediate/C_Other). Find a register that we can use. |
--- |
9234 |
// C_Immediate/C_Other). Find a register that we can use. |
--- |
| 9235 |
if (OpInfo.AssignedRegs.Regs.empty()) { |
0 |
9235 |
if (OpInfo.AssignedRegs.Regs.empty()) { |
0 |
| 9236 |
emitInlineAsmError( |
0 |
9236 |
emitInlineAsmError( |
0 |
| 9237 |
Call, "couldn't allocate output register for constraint '" + |
0 |
9237 |
Call, "couldn't allocate output register for constraint '" + |
0 |
| 9238 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
9238 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
| 9239 |
return; |
0 |
9239 |
return; |
0 |
| 9240 |
} |
--- |
9240 |
} |
--- |
| 9241 |
|
--- |
9241 |
|
--- |
| 9242 |
if (DetectWriteToReservedRegister()) |
0 |
9242 |
if (DetectWriteToReservedRegister()) |
0 |
| 9243 |
return; |
0 |
9243 |
return; |
0 |
| 9244 |
|
--- |
9244 |
|
--- |
| 9245 |
// Add information to the INLINEASM node to know that this register is |
--- |
9245 |
// Add information to the INLINEASM node to know that this register is |
--- |
| 9246 |
// set. |
--- |
9246 |
// set. |
--- |
| 9247 |
OpInfo.AssignedRegs.AddInlineAsmOperands( |
0 |
9247 |
OpInfo.AssignedRegs.AddInlineAsmOperands( |
0 |
| 9248 |
OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber |
0 |
9248 |
OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber |
0 |
| 9249 |
: InlineAsm::Kind_RegDef, |
--- |
9249 |
: InlineAsm::Kind_RegDef, |
--- |
| 9250 |
false, 0, getCurSDLoc(), DAG, AsmNodeOperands); |
0 |
9250 |
false, 0, getCurSDLoc(), DAG, AsmNodeOperands); |
0 |
| 9251 |
} |
--- |
9251 |
} |
--- |
| 9252 |
break; |
0 |
9252 |
break; |
0 |
| 9253 |
|
--- |
9253 |
|
--- |
| 9254 |
case InlineAsm::isInput: |
0 |
9254 |
case InlineAsm::isInput: |
0 |
| 9255 |
case InlineAsm::isLabel: { |
--- |
9255 |
case InlineAsm::isLabel: { |
--- |
| 9256 |
SDValue InOperandVal = OpInfo.CallOperand; |
0 |
9256 |
SDValue InOperandVal = OpInfo.CallOperand; |
0 |
| 9257 |
|
--- |
9257 |
|
--- |
| 9258 |
if (OpInfo.isMatchingInputConstraint()) { |
0 |
9258 |
if (OpInfo.isMatchingInputConstraint()) { |
0 |
| 9259 |
// If this is required to match an output register we have already set, |
--- |
9259 |
// If this is required to match an output register we have already set, |
--- |
| 9260 |
// just use its register. |
--- |
9260 |
// just use its register. |
--- |
| 9261 |
auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(), |
0 |
9261 |
auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(), |
0 |
| 9262 |
AsmNodeOperands); |
--- |
9262 |
AsmNodeOperands); |
--- |
| 9263 |
unsigned OpFlag = |
--- |
9263 |
unsigned OpFlag = |
--- |
| 9264 |
cast(AsmNodeOperands[CurOp])->getZExtValue(); |
0 |
9264 |
cast(AsmNodeOperands[CurOp])->getZExtValue(); |
0 |
| 9265 |
if (InlineAsm::isRegDefKind(OpFlag) || |
0 |
9265 |
if (InlineAsm::isRegDefKind(OpFlag) || |
0 |
| 9266 |
InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { |
0 |
9266 |
InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { |
0 |
| 9267 |
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs. |
--- |
9267 |
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs. |
--- |
| 9268 |
if (OpInfo.isIndirect) { |
0 |
9268 |
if (OpInfo.isIndirect) { |
0 |
| 9269 |
// This happens on gcc/testsuite/gcc.dg/pr8788-1.c |
--- |
9269 |
// This happens on gcc/testsuite/gcc.dg/pr8788-1.c |
--- |
| 9270 |
emitInlineAsmError(Call, "inline asm not supported yet: " |
0 |
9270 |
emitInlineAsmError(Call, "inline asm not supported yet: " |
0 |
| 9271 |
"don't know how to handle tied " |
--- |
9271 |
"don't know how to handle tied " |
--- |
| 9272 |
"indirect register inputs"); |
--- |
9272 |
"indirect register inputs"); |
--- |
| 9273 |
return; |
0 |
9273 |
return; |
0 |
| 9274 |
} |
--- |
9274 |
} |
--- |
| 9275 |
|
--- |
9275 |
|
--- |
| 9276 |
SmallVector Regs; |
0 |
9276 |
SmallVector Regs; |
0 |
| 9277 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
9277 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 9278 |
MachineRegisterInfo &MRI = MF.getRegInfo(); |
0 |
9278 |
MachineRegisterInfo &MRI = MF.getRegInfo(); |
0 |
| 9279 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
9279 |
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
0 |
| 9280 |
auto *R = cast(AsmNodeOperands[CurOp+1]); |
0 |
9280 |
auto *R = cast(AsmNodeOperands[CurOp+1]); |
0 |
| 9281 |
Register TiedReg = R->getReg(); |
0 |
9281 |
Register TiedReg = R->getReg(); |
0 |
| 9282 |
MVT RegVT = R->getSimpleValueType(0); |
0 |
9282 |
MVT RegVT = R->getSimpleValueType(0); |
0 |
| 9283 |
const TargetRegisterClass *RC = |
--- |
9283 |
const TargetRegisterClass *RC = |
--- |
| 9284 |
TiedReg.isVirtual() ? MRI.getRegClass(TiedReg) |
0 |
9284 |
TiedReg.isVirtual() ? MRI.getRegClass(TiedReg) |
0 |
| 9285 |
: RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) |
0 |
9285 |
: RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) |
0 |
| 9286 |
: TRI.getMinimalPhysRegClass(TiedReg); |
0 |
9286 |
: TRI.getMinimalPhysRegClass(TiedReg); |
0 |
| 9287 |
unsigned NumRegs = InlineAsm::getNumOperandRegisters(OpFlag); |
0 |
9287 |
unsigned NumRegs = InlineAsm::getNumOperandRegisters(OpFlag); |
0 |
| 9288 |
for (unsigned i = 0; i != NumRegs; ++i) |
0 |
9288 |
for (unsigned i = 0; i != NumRegs; ++i) |
0 |
| 9289 |
Regs.push_back(MRI.createVirtualRegister(RC)); |
0 |
9289 |
Regs.push_back(MRI.createVirtualRegister(RC)); |
0 |
| 9290 |
|
--- |
9290 |
|
--- |
| 9291 |
RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); |
0 |
9291 |
RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); |
0 |
| 9292 |
|
--- |
9292 |
|
--- |
| 9293 |
SDLoc dl = getCurSDLoc(); |
0 |
9293 |
SDLoc dl = getCurSDLoc(); |
0 |
| 9294 |
// Use the produced MatchedRegs object to |
--- |
9294 |
// Use the produced MatchedRegs object to |
--- |
| 9295 |
MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, &Call); |
0 |
9295 |
MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, &Call); |
0 |
| 9296 |
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, |
0 |
9296 |
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, |
0 |
| 9297 |
true, OpInfo.getMatchedOperand(), dl, |
--- |
9297 |
true, OpInfo.getMatchedOperand(), dl, |
--- |
| 9298 |
DAG, AsmNodeOperands); |
--- |
9298 |
DAG, AsmNodeOperands); |
--- |
| 9299 |
break; |
0 |
9299 |
break; |
0 |
| 9300 |
} |
0 |
9300 |
} |
0 |
| 9301 |
|
--- |
9301 |
|
--- |
| 9302 |
assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); |
0 |
9302 |
assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); |
0 |
| 9303 |
assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && |
0 |
9303 |
assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && |
0 |
| 9304 |
"Unexpected number of operands"); |
--- |
9304 |
"Unexpected number of operands"); |
--- |
| 9305 |
// Add information to the INLINEASM node to know about this input. |
--- |
9305 |
// Add information to the INLINEASM node to know about this input. |
--- |
| 9306 |
// See InlineAsm.h isUseOperandTiedToDef. |
--- |
9306 |
// See InlineAsm.h isUseOperandTiedToDef. |
--- |
| 9307 |
OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag); |
0 |
9307 |
OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag); |
0 |
| 9308 |
OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, |
0 |
9308 |
OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, |
0 |
| 9309 |
OpInfo.getMatchedOperand()); |
--- |
9309 |
OpInfo.getMatchedOperand()); |
--- |
| 9310 |
AsmNodeOperands.push_back(DAG.getTargetConstant( |
0 |
9310 |
AsmNodeOperands.push_back(DAG.getTargetConstant( |
0 |
| 9311 |
OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
9311 |
OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 9312 |
AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); |
0 |
9312 |
AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); |
0 |
| 9313 |
break; |
0 |
9313 |
break; |
0 |
| 9314 |
} |
--- |
9314 |
} |
--- |
| 9315 |
|
--- |
9315 |
|
--- |
| 9316 |
// Treat indirect 'X' constraint as memory. |
--- |
9316 |
// Treat indirect 'X' constraint as memory. |
--- |
| 9317 |
if (OpInfo.ConstraintType == TargetLowering::C_Other && |
0 |
9317 |
if (OpInfo.ConstraintType == TargetLowering::C_Other && |
0 |
| 9318 |
OpInfo.isIndirect) |
0 |
9318 |
OpInfo.isIndirect) |
0 |
| 9319 |
OpInfo.ConstraintType = TargetLowering::C_Memory; |
0 |
9319 |
OpInfo.ConstraintType = TargetLowering::C_Memory; |
0 |
| 9320 |
|
--- |
9320 |
|
--- |
| 9321 |
if (OpInfo.ConstraintType == TargetLowering::C_Immediate || |
0 |
9321 |
if (OpInfo.ConstraintType == TargetLowering::C_Immediate || |
0 |
| 9322 |
OpInfo.ConstraintType == TargetLowering::C_Other) { |
0 |
9322 |
OpInfo.ConstraintType == TargetLowering::C_Other) { |
0 |
| 9323 |
std::vector Ops; |
0 |
9323 |
std::vector Ops; |
0 |
| 9324 |
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, |
0 |
9324 |
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, |
0 |
| 9325 |
Ops, DAG); |
--- |
9325 |
Ops, DAG); |
--- |
| 9326 |
if (Ops.empty()) { |
0 |
9326 |
if (Ops.empty()) { |
0 |
| 9327 |
if (OpInfo.ConstraintType == TargetLowering::C_Immediate) |
0 |
9327 |
if (OpInfo.ConstraintType == TargetLowering::C_Immediate) |
0 |
| 9328 |
if (isa(InOperandVal)) { |
0 |
9328 |
if (isa(InOperandVal)) { |
0 |
| 9329 |
emitInlineAsmError(Call, "value out of range for constraint '" + |
0 |
9329 |
emitInlineAsmError(Call, "value out of range for constraint '" + |
0 |
| 9330 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
9330 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
| 9331 |
return; |
0 |
9331 |
return; |
0 |
| 9332 |
} |
--- |
9332 |
} |
--- |
| 9333 |
|
--- |
9333 |
|
--- |
| 9334 |
emitInlineAsmError(Call, |
0 |
9334 |
emitInlineAsmError(Call, |
0 |
| 9335 |
"invalid operand for inline asm constraint '" + |
0 |
9335 |
"invalid operand for inline asm constraint '" + |
0 |
| 9336 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
9336 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
| 9337 |
return; |
0 |
9337 |
return; |
0 |
| 9338 |
} |
--- |
9338 |
} |
--- |
| 9339 |
|
--- |
9339 |
|
--- |
| 9340 |
// Add information to the INLINEASM node to know about this input. |
--- |
9340 |
// Add information to the INLINEASM node to know about this input. |
--- |
| 9341 |
unsigned ResOpType = |
--- |
9341 |
unsigned ResOpType = |
--- |
| 9342 |
InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); |
0 |
9342 |
InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); |
0 |
| 9343 |
AsmNodeOperands.push_back(DAG.getTargetConstant( |
0 |
9343 |
AsmNodeOperands.push_back(DAG.getTargetConstant( |
0 |
| 9344 |
ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
9344 |
ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); |
0 |
| 9345 |
llvm::append_range(AsmNodeOperands, Ops); |
0 |
9345 |
llvm::append_range(AsmNodeOperands, Ops); |
0 |
| 9346 |
break; |
0 |
9346 |
break; |
0 |
| 9347 |
} |
0 |
9347 |
} |
0 |
| 9348 |
|
--- |
9348 |
|
--- |
| 9349 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory) { |
0 |
9349 |
if (OpInfo.ConstraintType == TargetLowering::C_Memory) { |
0 |
| 9350 |
assert((OpInfo.isIndirect || |
0 |
9350 |
assert((OpInfo.isIndirect || |
0 |
| 9351 |
OpInfo.ConstraintType != TargetLowering::C_Memory) && |
--- |
9351 |
OpInfo.ConstraintType != TargetLowering::C_Memory) && |
--- |
| 9352 |
"Operand must be indirect to be a mem!"); |
--- |
9352 |
"Operand must be indirect to be a mem!"); |
--- |
| 9353 |
assert(InOperandVal.getValueType() == |
0 |
9353 |
assert(InOperandVal.getValueType() == |
0 |
| 9354 |
TLI.getPointerTy(DAG.getDataLayout()) && |
--- |
9354 |
TLI.getPointerTy(DAG.getDataLayout()) && |
--- |
| 9355 |
"Memory operands expect pointer values"); |
--- |
9355 |
"Memory operands expect pointer values"); |
--- |
| 9356 |
|
--- |
9356 |
|
--- |
| 9357 |
unsigned ConstraintID = |
--- |
9357 |
unsigned ConstraintID = |
--- |
| 9358 |
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); |
0 |
9358 |
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); |
0 |
| 9359 |
assert(ConstraintID != InlineAsm::Constraint_Unknown && |
0 |
9359 |
assert(ConstraintID != InlineAsm::Constraint_Unknown && |
0 |
| 9360 |
"Failed to convert memory constraint code to constraint id."); |
--- |
9360 |
"Failed to convert memory constraint code to constraint id."); |
--- |
| 9361 |
|
--- |
9361 |
|
--- |
| 9362 |
// Add information to the INLINEASM node to know about this input. |
--- |
9362 |
// Add information to the INLINEASM node to know about this input. |
--- |
| 9363 |
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); |
0 |
9363 |
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); |
0 |
| 9364 |
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); |
0 |
9364 |
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); |
0 |
| 9365 |
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, |
0 |
9365 |
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, |
0 |
| 9366 |
getCurSDLoc(), |
0 |
9366 |
getCurSDLoc(), |
0 |
| 9367 |
MVT::i32)); |
--- |
9367 |
MVT::i32)); |
--- |
| 9368 |
AsmNodeOperands.push_back(InOperandVal); |
0 |
9368 |
AsmNodeOperands.push_back(InOperandVal); |
0 |
| 9369 |
break; |
0 |
9369 |
break; |
0 |
| 9370 |
} |
--- |
9370 |
} |
--- |
| 9371 |
|
--- |
9371 |
|
--- |
| 9372 |
if (OpInfo.ConstraintType == TargetLowering::C_Address) { |
0 |
9372 |
if (OpInfo.ConstraintType == TargetLowering::C_Address) { |
0 |
| 9373 |
unsigned ConstraintID = |
--- |
9373 |
unsigned ConstraintID = |
--- |
| 9374 |
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); |
0 |
9374 |
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); |
0 |
| 9375 |
assert(ConstraintID != InlineAsm::Constraint_Unknown && |
0 |
9375 |
assert(ConstraintID != InlineAsm::Constraint_Unknown && |
0 |
| 9376 |
"Failed to convert memory constraint code to constraint id."); |
--- |
9376 |
"Failed to convert memory constraint code to constraint id."); |
--- |
| 9377 |
|
--- |
9377 |
|
--- |
| 9378 |
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); |
0 |
9378 |
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); |
0 |
| 9379 |
|
--- |
9379 |
|
--- |
| 9380 |
SDValue AsmOp = InOperandVal; |
0 |
9380 |
SDValue AsmOp = InOperandVal; |
0 |
| 9381 |
if (isFunction(InOperandVal)) { |
0 |
9381 |
if (isFunction(InOperandVal)) { |
0 |
| 9382 |
auto *GA = cast(InOperandVal); |
0 |
9382 |
auto *GA = cast(InOperandVal); |
0 |
| 9383 |
ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Func, 1); |
0 |
9383 |
ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Func, 1); |
0 |
| 9384 |
AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(), |
0 |
9384 |
AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(), |
0 |
| 9385 |
InOperandVal.getValueType(), |
--- |
9385 |
InOperandVal.getValueType(), |
--- |
| 9386 |
GA->getOffset()); |
--- |
9386 |
GA->getOffset()); |
--- |
| 9387 |
} |
--- |
9387 |
} |
--- |
| 9388 |
|
--- |
9388 |
|
--- |
| 9389 |
// Add information to the INLINEASM node to know about this input. |
--- |
9389 |
// Add information to the INLINEASM node to know about this input. |
--- |
| 9390 |
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); |
0 |
9390 |
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); |
0 |
| 9391 |
|
--- |
9391 |
|
--- |
| 9392 |
AsmNodeOperands.push_back( |
0 |
9392 |
AsmNodeOperands.push_back( |
0 |
| 9393 |
DAG.getTargetConstant(ResOpType, getCurSDLoc(), MVT::i32)); |
0 |
9393 |
DAG.getTargetConstant(ResOpType, getCurSDLoc(), MVT::i32)); |
0 |
| 9394 |
|
--- |
9394 |
|
--- |
| 9395 |
AsmNodeOperands.push_back(AsmOp); |
0 |
9395 |
AsmNodeOperands.push_back(AsmOp); |
0 |
| 9396 |
break; |
0 |
9396 |
break; |
0 |
| 9397 |
} |
--- |
9397 |
} |
--- |
| 9398 |
|
--- |
9398 |
|
--- |
| 9399 |
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || |
0 |
9399 |
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || |
0 |
| 9400 |
OpInfo.ConstraintType == TargetLowering::C_Register) && |
--- |
9400 |
OpInfo.ConstraintType == TargetLowering::C_Register) && |
--- |
| 9401 |
"Unknown constraint type!"); |
--- |
9401 |
"Unknown constraint type!"); |
--- |
| 9402 |
|
--- |
9402 |
|
--- |
| 9403 |
// TODO: Support this. |
--- |
9403 |
// TODO: Support this. |
--- |
| 9404 |
if (OpInfo.isIndirect) { |
0 |
9404 |
if (OpInfo.isIndirect) { |
0 |
| 9405 |
emitInlineAsmError( |
0 |
9405 |
emitInlineAsmError( |
0 |
| 9406 |
Call, "Don't know how to handle indirect register inputs yet " |
--- |
9406 |
Call, "Don't know how to handle indirect register inputs yet " |
--- |
| 9407 |
"for constraint '" + |
0 |
9407 |
"for constraint '" + |
0 |
| 9408 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
9408 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
| 9409 |
return; |
0 |
9409 |
return; |
0 |
| 9410 |
} |
--- |
9410 |
} |
--- |
| 9411 |
|
--- |
9411 |
|
--- |
| 9412 |
// Copy the input into the appropriate registers. |
--- |
9412 |
// Copy the input into the appropriate registers. |
--- |
| 9413 |
if (OpInfo.AssignedRegs.Regs.empty()) { |
0 |
9413 |
if (OpInfo.AssignedRegs.Regs.empty()) { |
0 |
| 9414 |
emitInlineAsmError(Call, |
0 |
9414 |
emitInlineAsmError(Call, |
0 |
| 9415 |
"couldn't allocate input reg for constraint '" + |
0 |
9415 |
"couldn't allocate input reg for constraint '" + |
0 |
| 9416 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
9416 |
Twine(OpInfo.ConstraintCode) + "'"); |
0 |
| 9417 |
return; |
0 |
9417 |
return; |
0 |
| 9418 |
} |
--- |
9418 |
} |
--- |
| 9419 |
|
--- |
9419 |
|
--- |
| 9420 |
if (DetectWriteToReservedRegister()) |
0 |
9420 |
if (DetectWriteToReservedRegister()) |
0 |
| 9421 |
return; |
0 |
9421 |
return; |
0 |
| 9422 |
|
--- |
9422 |
|
--- |
| 9423 |
SDLoc dl = getCurSDLoc(); |
0 |
9423 |
SDLoc dl = getCurSDLoc(); |
0 |
| 9424 |
|
--- |
9424 |
|
--- |
| 9425 |
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, |
0 |
9425 |
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, |
0 |
| 9426 |
&Call); |
--- |
9426 |
&Call); |
--- |
| 9427 |
|
--- |
9427 |
|
--- |
| 9428 |
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, |
0 |
9428 |
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, |
0 |
| 9429 |
dl, DAG, AsmNodeOperands); |
--- |
9429 |
dl, DAG, AsmNodeOperands); |
--- |
| 9430 |
break; |
0 |
9430 |
break; |
0 |
| 9431 |
} |
0 |
9431 |
} |
0 |
| 9432 |
case InlineAsm::isClobber: |
0 |
9432 |
case InlineAsm::isClobber: |
0 |
| 9433 |
// Add the clobbered value to the operand list, so that the register |
--- |
9433 |
// Add the clobbered value to the operand list, so that the register |
--- |
| 9434 |
// allocator is aware that the physreg got clobbered. |
--- |
9434 |
// allocator is aware that the physreg got clobbered. |
--- |
| 9435 |
if (!OpInfo.AssignedRegs.Regs.empty()) |
0 |
9435 |
if (!OpInfo.AssignedRegs.Regs.empty()) |
0 |
| 9436 |
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, |
0 |
9436 |
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, |
0 |
| 9437 |
false, 0, getCurSDLoc(), DAG, |
0 |
9437 |
false, 0, getCurSDLoc(), DAG, |
0 |
| 9438 |
AsmNodeOperands); |
--- |
9438 |
AsmNodeOperands); |
--- |
| 9439 |
break; |
0 |
9439 |
break; |
0 |
| 9440 |
} |
--- |
9440 |
} |
--- |
| 9441 |
} |
--- |
9441 |
} |
--- |
| 9442 |
|
--- |
9442 |
|
--- |
| 9443 |
// Finish up input operands. Set the input chain and add the flag last. |
--- |
9443 |
// Finish up input operands. Set the input chain and add the flag last. |
--- |
| 9444 |
AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; |
0 |
9444 |
AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; |
0 |
| 9445 |
if (Glue.getNode()) AsmNodeOperands.push_back(Glue); |
0 |
9445 |
if (Glue.getNode()) AsmNodeOperands.push_back(Glue); |
0 |
| 9446 |
|
--- |
9446 |
|
--- |
| 9447 |
unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM; |
0 |
9447 |
unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM; |
0 |
| 9448 |
Chain = DAG.getNode(ISDOpc, getCurSDLoc(), |
0 |
9448 |
Chain = DAG.getNode(ISDOpc, getCurSDLoc(), |
0 |
| 9449 |
DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands); |
0 |
9449 |
DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands); |
0 |
| 9450 |
Glue = Chain.getValue(1); |
0 |
9450 |
Glue = Chain.getValue(1); |
0 |
| 9451 |
|
--- |
9451 |
|
--- |
| 9452 |
// Do additional work to generate outputs. |
--- |
9452 |
// Do additional work to generate outputs. |
--- |
| 9453 |
|
--- |
9453 |
|
--- |
| 9454 |
SmallVector ResultVTs; |
0 |
9454 |
SmallVector ResultVTs; |
0 |
| 9455 |
SmallVector ResultValues; |
0 |
9455 |
SmallVector ResultValues; |
0 |
| 9456 |
SmallVector OutChains; |
0 |
9456 |
SmallVector OutChains; |
0 |
| 9457 |
|
--- |
9457 |
|
--- |
| 9458 |
llvm::Type *CallResultType = Call.getType(); |
0 |
9458 |
llvm::Type *CallResultType = Call.getType(); |
0 |
| 9459 |
ArrayRef ResultTypes; |
0 |
9459 |
ArrayRef ResultTypes; |
0 |
| 9460 |
if (StructType *StructResult = dyn_cast(CallResultType)) |
0 |
9460 |
if (StructType *StructResult = dyn_cast(CallResultType)) |
0 |
| 9461 |
ResultTypes = StructResult->elements(); |
0 |
9461 |
ResultTypes = StructResult->elements(); |
0 |
| 9462 |
else if (!CallResultType->isVoidTy()) |
0 |
9462 |
else if (!CallResultType->isVoidTy()) |
0 |
| 9463 |
ResultTypes = ArrayRef(CallResultType); |
0 |
9463 |
ResultTypes = ArrayRef(CallResultType); |
0 |
| 9464 |
|
--- |
9464 |
|
--- |
| 9465 |
auto CurResultType = ResultTypes.begin(); |
0 |
9465 |
auto CurResultType = ResultTypes.begin(); |
0 |
| 9466 |
auto handleRegAssign = [&](SDValue V) { |
0 |
9466 |
auto handleRegAssign = [&](SDValue V) { |
0 |
| 9467 |
assert(CurResultType != ResultTypes.end() && "Unexpected value"); |
0 |
9467 |
assert(CurResultType != ResultTypes.end() && "Unexpected value"); |
0 |
| 9468 |
assert((*CurResultType)->isSized() && "Unexpected unsized type"); |
0 |
9468 |
assert((*CurResultType)->isSized() && "Unexpected unsized type"); |
0 |
| 9469 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), *CurResultType); |
0 |
9469 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), *CurResultType); |
0 |
| 9470 |
++CurResultType; |
0 |
9470 |
++CurResultType; |
0 |
| 9471 |
// If the type of the inline asm call site return value is different but has |
--- |
9471 |
// If the type of the inline asm call site return value is different but has |
--- |
| 9472 |
// same size as the type of the asm output bitcast it. One example of this |
--- |
9472 |
// same size as the type of the asm output bitcast it. One example of this |
--- |
| 9473 |
// is for vectors with different width / number of elements. This can |
--- |
9473 |
// is for vectors with different width / number of elements. This can |
--- |
| 9474 |
// happen for register classes that can contain multiple different value |
--- |
9474 |
// happen for register classes that can contain multiple different value |
--- |
| 9475 |
// types. The preg or vreg allocated may not have the same VT as was |
--- |
9475 |
// types. The preg or vreg allocated may not have the same VT as was |
--- |
| 9476 |
// expected. |
--- |
9476 |
// expected. |
--- |
| 9477 |
// |
--- |
9477 |
// |
--- |
| 9478 |
// This can also happen for a return value that disagrees with the register |
--- |
9478 |
// This can also happen for a return value that disagrees with the register |
--- |
| 9479 |
// class it is put in, eg. a double in a general-purpose register on a |
--- |
9479 |
// class it is put in, eg. a double in a general-purpose register on a |
--- |
| 9480 |
// 32-bit machine. |
--- |
9480 |
// 32-bit machine. |
--- |
| 9481 |
if (ResultVT != V.getValueType() && |
0 |
9481 |
if (ResultVT != V.getValueType() && |
0 |
| 9482 |
ResultVT.getSizeInBits() == V.getValueSizeInBits()) |
0 |
9482 |
ResultVT.getSizeInBits() == V.getValueSizeInBits()) |
0 |
| 9483 |
V = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, V); |
0 |
9483 |
V = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, V); |
0 |
| 9484 |
else if (ResultVT != V.getValueType() && ResultVT.isInteger() && |
0 |
9484 |
else if (ResultVT != V.getValueType() && ResultVT.isInteger() && |
0 |
| 9485 |
V.getValueType().isInteger()) { |
0 |
9485 |
V.getValueType().isInteger()) { |
0 |
| 9486 |
// If a result value was tied to an input value, the computed result |
--- |
9486 |
// If a result value was tied to an input value, the computed result |
--- |
| 9487 |
// may have a wider width than the expected result. Extract the |
--- |
9487 |
// may have a wider width than the expected result. Extract the |
--- |
| 9488 |
// relevant portion. |
--- |
9488 |
// relevant portion. |
--- |
| 9489 |
V = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, V); |
0 |
9489 |
V = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, V); |
0 |
| 9490 |
} |
--- |
9490 |
} |
--- |
| 9491 |
assert(ResultVT == V.getValueType() && "Asm result value mismatch!"); |
0 |
9491 |
assert(ResultVT == V.getValueType() && "Asm result value mismatch!"); |
0 |
| 9492 |
ResultVTs.push_back(ResultVT); |
0 |
9492 |
ResultVTs.push_back(ResultVT); |
0 |
| 9493 |
ResultValues.push_back(V); |
0 |
9493 |
ResultValues.push_back(V); |
0 |
| 9494 |
}; |
0 |
9494 |
}; |
0 |
| 9495 |
|
--- |
9495 |
|
--- |
| 9496 |
// Deal with output operands. |
--- |
9496 |
// Deal with output operands. |
--- |
| 9497 |
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { |
0 |
9497 |
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { |
0 |
| 9498 |
if (OpInfo.Type == InlineAsm::isOutput) { |
0 |
9498 |
if (OpInfo.Type == InlineAsm::isOutput) { |
0 |
| 9499 |
SDValue Val; |
0 |
9499 |
SDValue Val; |
0 |
| 9500 |
// Skip trivial output operands. |
--- |
9500 |
// Skip trivial output operands. |
--- |
| 9501 |
if (OpInfo.AssignedRegs.Regs.empty()) |
0 |
9501 |
if (OpInfo.AssignedRegs.Regs.empty()) |
0 |
| 9502 |
continue; |
0 |
9502 |
continue; |
0 |
| 9503 |
|
--- |
9503 |
|
--- |
| 9504 |
switch (OpInfo.ConstraintType) { |
0 |
9504 |
switch (OpInfo.ConstraintType) { |
0 |
| 9505 |
case TargetLowering::C_Register: |
0 |
9505 |
case TargetLowering::C_Register: |
0 |
| 9506 |
case TargetLowering::C_RegisterClass: |
--- |
9506 |
case TargetLowering::C_RegisterClass: |
--- |
| 9507 |
Val = OpInfo.AssignedRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), |
0 |
9507 |
Val = OpInfo.AssignedRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), |
0 |
| 9508 |
Chain, &Glue, &Call); |
--- |
9508 |
Chain, &Glue, &Call); |
--- |
| 9509 |
break; |
0 |
9509 |
break; |
0 |
| 9510 |
case TargetLowering::C_Immediate: |
0 |
9510 |
case TargetLowering::C_Immediate: |
0 |
| 9511 |
case TargetLowering::C_Other: |
--- |
9511 |
case TargetLowering::C_Other: |
--- |
| 9512 |
Val = TLI.LowerAsmOutputForConstraint(Chain, Glue, getCurSDLoc(), |
0 |
9512 |
Val = TLI.LowerAsmOutputForConstraint(Chain, Glue, getCurSDLoc(), |
0 |
| 9513 |
OpInfo, DAG); |
--- |
9513 |
OpInfo, DAG); |
--- |
| 9514 |
break; |
0 |
9514 |
break; |
0 |
| 9515 |
case TargetLowering::C_Memory: |
0 |
9515 |
case TargetLowering::C_Memory: |
0 |
| 9516 |
break; // Already handled. |
0 |
9516 |
break; // Already handled. |
0 |
| 9517 |
case TargetLowering::C_Address: |
0 |
9517 |
case TargetLowering::C_Address: |
0 |
| 9518 |
break; // Silence warning. |
0 |
9518 |
break; // Silence warning. |
0 |
| 9519 |
case TargetLowering::C_Unknown: |
0 |
9519 |
case TargetLowering::C_Unknown: |
0 |
| 9520 |
assert(false && "Unexpected unknown constraint"); |
0 |
9520 |
assert(false && "Unexpected unknown constraint"); |
0 |
| 9521 |
} |
--- |
9521 |
} |
--- |
| 9522 |
|
--- |
9522 |
|
--- |
| 9523 |
// Indirect output manifest as stores. Record output chains. |
--- |
9523 |
// Indirect output manifest as stores. Record output chains. |
--- |
| 9524 |
if (OpInfo.isIndirect) { |
0 |
9524 |
if (OpInfo.isIndirect) { |
0 |
| 9525 |
const Value *Ptr = OpInfo.CallOperandVal; |
0 |
9525 |
const Value *Ptr = OpInfo.CallOperandVal; |
0 |
| 9526 |
assert(Ptr && "Expected value CallOperandVal for indirect asm operand"); |
0 |
9526 |
assert(Ptr && "Expected value CallOperandVal for indirect asm operand"); |
0 |
| 9527 |
SDValue Store = DAG.getStore(Chain, getCurSDLoc(), Val, getValue(Ptr), |
0 |
9527 |
SDValue Store = DAG.getStore(Chain, getCurSDLoc(), Val, getValue(Ptr), |
0 |
| 9528 |
MachinePointerInfo(Ptr)); |
--- |
9528 |
MachinePointerInfo(Ptr)); |
--- |
| 9529 |
OutChains.push_back(Store); |
0 |
9529 |
OutChains.push_back(Store); |
0 |
| 9530 |
} else { |
--- |
9530 |
} else { |
--- |
| 9531 |
// generate CopyFromRegs to associated registers. |
--- |
9531 |
// generate CopyFromRegs to associated registers. |
--- |
| 9532 |
assert(!Call.getType()->isVoidTy() && "Bad inline asm!"); |
0 |
9532 |
assert(!Call.getType()->isVoidTy() && "Bad inline asm!"); |
0 |
| 9533 |
if (Val.getOpcode() == ISD::MERGE_VALUES) { |
0 |
9533 |
if (Val.getOpcode() == ISD::MERGE_VALUES) { |
0 |
| 9534 |
for (const SDValue &V : Val->op_values()) |
0 |
9534 |
for (const SDValue &V : Val->op_values()) |
0 |
| 9535 |
handleRegAssign(V); |
0 |
9535 |
handleRegAssign(V); |
0 |
| 9536 |
} else |
--- |
9536 |
} else |
--- |
| 9537 |
handleRegAssign(Val); |
0 |
9537 |
handleRegAssign(Val); |
0 |
| 9538 |
} |
--- |
9538 |
} |
--- |
| 9539 |
} |
--- |
9539 |
} |
--- |
| 9540 |
} |
--- |
9540 |
} |
--- |
| 9541 |
|
--- |
9541 |
|
--- |
| 9542 |
// Set results. |
--- |
9542 |
// Set results. |
--- |
| 9543 |
if (!ResultValues.empty()) { |
0 |
9543 |
if (!ResultValues.empty()) { |
0 |
| 9544 |
assert(CurResultType == ResultTypes.end() && |
0 |
9544 |
assert(CurResultType == ResultTypes.end() && |
0 |
| 9545 |
"Mismatch in number of ResultTypes"); |
--- |
9545 |
"Mismatch in number of ResultTypes"); |
--- |
| 9546 |
assert(ResultValues.size() == ResultTypes.size() && |
0 |
9546 |
assert(ResultValues.size() == ResultTypes.size() && |
0 |
| 9547 |
"Mismatch in number of output operands in asm result"); |
--- |
9547 |
"Mismatch in number of output operands in asm result"); |
--- |
| 9548 |
|
--- |
9548 |
|
--- |
| 9549 |
SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
9549 |
SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
| 9550 |
DAG.getVTList(ResultVTs), ResultValues); |
0 |
9550 |
DAG.getVTList(ResultVTs), ResultValues); |
0 |
| 9551 |
setValue(&Call, V); |
0 |
9551 |
setValue(&Call, V); |
0 |
| 9552 |
} |
--- |
9552 |
} |
--- |
| 9553 |
|
--- |
9553 |
|
--- |
| 9554 |
// Collect store chains. |
--- |
9554 |
// Collect store chains. |
--- |
| 9555 |
if (!OutChains.empty()) |
0 |
9555 |
if (!OutChains.empty()) |
0 |
| 9556 |
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains); |
0 |
9556 |
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains); |
0 |
| 9557 |
|
--- |
9557 |
|
--- |
| 9558 |
if (EmitEHLabels) { |
0 |
9558 |
if (EmitEHLabels) { |
0 |
| 9559 |
Chain = lowerEndEH(Chain, cast(&Call), EHPadBB, BeginLabel); |
0 |
9559 |
Chain = lowerEndEH(Chain, cast(&Call), EHPadBB, BeginLabel); |
0 |
| 9560 |
} |
--- |
9560 |
} |
--- |
| 9561 |
|
--- |
9561 |
|
--- |
| 9562 |
// Only Update Root if inline assembly has a memory effect. |
--- |
9562 |
// Only Update Root if inline assembly has a memory effect. |
--- |
| 9563 |
if (ResultValues.empty() || HasSideEffect || !OutChains.empty() || IsCallBr || |
0 |
9563 |
if (ResultValues.empty() || HasSideEffect || !OutChains.empty() || IsCallBr || |
0 |
| 9564 |
EmitEHLabels) |
--- |
9564 |
EmitEHLabels) |
--- |
| 9565 |
DAG.setRoot(Chain); |
0 |
9565 |
DAG.setRoot(Chain); |
0 |
| 9566 |
} |
0 |
9566 |
} |
0 |
| 9567 |
|
--- |
9567 |
|
--- |
| 9568 |
void SelectionDAGBuilder::emitInlineAsmError(const CallBase &Call, |
0 |
9568 |
void SelectionDAGBuilder::emitInlineAsmError(const CallBase &Call, |
0 |
| 9569 |
const Twine &Message) { |
--- |
9569 |
const Twine &Message) { |
--- |
| 9570 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
9570 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
| 9571 |
Ctx.emitError(&Call, Message); |
0 |
9571 |
Ctx.emitError(&Call, Message); |
0 |
| 9572 |
|
--- |
9572 |
|
--- |
| 9573 |
// Make sure we leave the DAG in a valid state |
--- |
9573 |
// Make sure we leave the DAG in a valid state |
--- |
| 9574 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
9574 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 9575 |
SmallVector ValueVTs; |
0 |
9575 |
SmallVector ValueVTs; |
0 |
| 9576 |
ComputeValueVTs(TLI, DAG.getDataLayout(), Call.getType(), ValueVTs); |
0 |
9576 |
ComputeValueVTs(TLI, DAG.getDataLayout(), Call.getType(), ValueVTs); |
0 |
| 9577 |
|
--- |
9577 |
|
--- |
| 9578 |
if (ValueVTs.empty()) |
0 |
9578 |
if (ValueVTs.empty()) |
0 |
| 9579 |
return; |
0 |
9579 |
return; |
0 |
| 9580 |
|
--- |
9580 |
|
--- |
| 9581 |
SmallVector Ops; |
0 |
9581 |
SmallVector Ops; |
0 |
| 9582 |
for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i) |
0 |
9582 |
for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i) |
0 |
| 9583 |
Ops.push_back(DAG.getUNDEF(ValueVTs[i])); |
0 |
9583 |
Ops.push_back(DAG.getUNDEF(ValueVTs[i])); |
0 |
| 9584 |
|
--- |
9584 |
|
--- |
| 9585 |
setValue(&Call, DAG.getMergeValues(Ops, getCurSDLoc())); |
0 |
9585 |
setValue(&Call, DAG.getMergeValues(Ops, getCurSDLoc())); |
0 |
| 9586 |
} |
0 |
9586 |
} |
0 |
| 9587 |
|
--- |
9587 |
|
--- |
| 9588 |
void SelectionDAGBuilder::visitVAStart(const CallInst &I) { |
0 |
9588 |
void SelectionDAGBuilder::visitVAStart(const CallInst &I) { |
0 |
| 9589 |
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), |
0 |
9589 |
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), |
0 |
| 9590 |
MVT::Other, getRoot(), |
--- |
9590 |
MVT::Other, getRoot(), |
--- |
| 9591 |
getValue(I.getArgOperand(0)), |
0 |
9591 |
getValue(I.getArgOperand(0)), |
0 |
| 9592 |
DAG.getSrcValue(I.getArgOperand(0)))); |
0 |
9592 |
DAG.getSrcValue(I.getArgOperand(0)))); |
0 |
| 9593 |
} |
0 |
9593 |
} |
0 |
| 9594 |
|
--- |
9594 |
|
--- |
| 9595 |
void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { |
0 |
9595 |
void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { |
0 |
| 9596 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
9596 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 9597 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
9597 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
| 9598 |
SDValue V = DAG.getVAArg( |
0 |
9598 |
SDValue V = DAG.getVAArg( |
0 |
| 9599 |
TLI.getMemValueType(DAG.getDataLayout(), I.getType()), getCurSDLoc(), |
0 |
9599 |
TLI.getMemValueType(DAG.getDataLayout(), I.getType()), getCurSDLoc(), |
0 |
| 9600 |
getRoot(), getValue(I.getOperand(0)), DAG.getSrcValue(I.getOperand(0)), |
0 |
9600 |
getRoot(), getValue(I.getOperand(0)), DAG.getSrcValue(I.getOperand(0)), |
0 |
| 9601 |
DL.getABITypeAlign(I.getType()).value()); |
0 |
9601 |
DL.getABITypeAlign(I.getType()).value()); |
0 |
| 9602 |
DAG.setRoot(V.getValue(1)); |
0 |
9602 |
DAG.setRoot(V.getValue(1)); |
0 |
| 9603 |
|
--- |
9603 |
|
--- |
| 9604 |
if (I.getType()->isPointerTy()) |
0 |
9604 |
if (I.getType()->isPointerTy()) |
0 |
| 9605 |
V = DAG.getPtrExtOrTrunc( |
0 |
9605 |
V = DAG.getPtrExtOrTrunc( |
0 |
| 9606 |
V, getCurSDLoc(), TLI.getValueType(DAG.getDataLayout(), I.getType())); |
0 |
9606 |
V, getCurSDLoc(), TLI.getValueType(DAG.getDataLayout(), I.getType())); |
0 |
| 9607 |
setValue(&I, V); |
0 |
9607 |
setValue(&I, V); |
0 |
| 9608 |
} |
0 |
9608 |
} |
0 |
| 9609 |
|
--- |
9609 |
|
--- |
| 9610 |
void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { |
0 |
9610 |
void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { |
0 |
| 9611 |
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), |
0 |
9611 |
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), |
0 |
| 9612 |
MVT::Other, getRoot(), |
--- |
9612 |
MVT::Other, getRoot(), |
--- |
| 9613 |
getValue(I.getArgOperand(0)), |
0 |
9613 |
getValue(I.getArgOperand(0)), |
0 |
| 9614 |
DAG.getSrcValue(I.getArgOperand(0)))); |
0 |
9614 |
DAG.getSrcValue(I.getArgOperand(0)))); |
0 |
| 9615 |
} |
0 |
9615 |
} |
0 |
| 9616 |
|
--- |
9616 |
|
--- |
| 9617 |
void SelectionDAGBuilder::visitVACopy(const CallInst &I) { |
0 |
9617 |
void SelectionDAGBuilder::visitVACopy(const CallInst &I) { |
0 |
| 9618 |
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), |
0 |
9618 |
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), |
0 |
| 9619 |
MVT::Other, getRoot(), |
--- |
9619 |
MVT::Other, getRoot(), |
--- |
| 9620 |
getValue(I.getArgOperand(0)), |
0 |
9620 |
getValue(I.getArgOperand(0)), |
0 |
| 9621 |
getValue(I.getArgOperand(1)), |
0 |
9621 |
getValue(I.getArgOperand(1)), |
0 |
| 9622 |
DAG.getSrcValue(I.getArgOperand(0)), |
0 |
9622 |
DAG.getSrcValue(I.getArgOperand(0)), |
0 |
| 9623 |
DAG.getSrcValue(I.getArgOperand(1)))); |
0 |
9623 |
DAG.getSrcValue(I.getArgOperand(1)))); |
0 |
| 9624 |
} |
0 |
9624 |
} |
0 |
| 9625 |
|
--- |
9625 |
|
--- |
| 9626 |
SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, |
0 |
9626 |
SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, |
0 |
| 9627 |
const Instruction &I, |
--- |
9627 |
const Instruction &I, |
--- |
| 9628 |
SDValue Op) { |
--- |
9628 |
SDValue Op) { |
--- |
| 9629 |
const MDNode *Range = I.getMetadata(LLVMContext::MD_range); |
0 |
9629 |
const MDNode *Range = I.getMetadata(LLVMContext::MD_range); |
0 |
| 9630 |
if (!Range) |
0 |
9630 |
if (!Range) |
0 |
| 9631 |
return Op; |
0 |
9631 |
return Op; |
0 |
| 9632 |
|
--- |
9632 |
|
--- |
| 9633 |
ConstantRange CR = getConstantRangeFromMetadata(*Range); |
0 |
9633 |
ConstantRange CR = getConstantRangeFromMetadata(*Range); |
0 |
| 9634 |
if (CR.isFullSet() || CR.isEmptySet() || CR.isUpperWrapped()) |
0 |
9634 |
if (CR.isFullSet() || CR.isEmptySet() || CR.isUpperWrapped()) |
0 |
| 9635 |
return Op; |
0 |
9635 |
return Op; |
0 |
| 9636 |
|
--- |
9636 |
|
--- |
| 9637 |
APInt Lo = CR.getUnsignedMin(); |
0 |
9637 |
APInt Lo = CR.getUnsignedMin(); |
0 |
| 9638 |
if (!Lo.isMinValue()) |
0 |
9638 |
if (!Lo.isMinValue()) |
0 |
| 9639 |
return Op; |
0 |
9639 |
return Op; |
0 |
| 9640 |
|
--- |
9640 |
|
--- |
| 9641 |
APInt Hi = CR.getUnsignedMax(); |
0 |
9641 |
APInt Hi = CR.getUnsignedMax(); |
0 |
| 9642 |
unsigned Bits = std::max(Hi.getActiveBits(), |
0 |
9642 |
unsigned Bits = std::max(Hi.getActiveBits(), |
0 |
| 9643 |
static_cast(IntegerType::MIN_INT_BITS)); |
0 |
9643 |
static_cast(IntegerType::MIN_INT_BITS)); |
0 |
| 9644 |
|
--- |
9644 |
|
--- |
| 9645 |
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); |
0 |
9645 |
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); |
0 |
| 9646 |
|
--- |
9646 |
|
--- |
| 9647 |
SDLoc SL = getCurSDLoc(); |
0 |
9647 |
SDLoc SL = getCurSDLoc(); |
0 |
| 9648 |
|
--- |
9648 |
|
--- |
| 9649 |
SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, |
0 |
9649 |
SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, |
0 |
| 9650 |
DAG.getValueType(SmallVT)); |
--- |
9650 |
DAG.getValueType(SmallVT)); |
--- |
| 9651 |
unsigned NumVals = Op.getNode()->getNumValues(); |
0 |
9651 |
unsigned NumVals = Op.getNode()->getNumValues(); |
0 |
| 9652 |
if (NumVals == 1) |
0 |
9652 |
if (NumVals == 1) |
0 |
| 9653 |
return ZExt; |
0 |
9653 |
return ZExt; |
0 |
| 9654 |
|
--- |
9654 |
|
--- |
| 9655 |
SmallVector Ops; |
0 |
9655 |
SmallVector Ops; |
0 |
| 9656 |
|
--- |
9656 |
|
--- |
| 9657 |
Ops.push_back(ZExt); |
0 |
9657 |
Ops.push_back(ZExt); |
0 |
| 9658 |
for (unsigned I = 1; I != NumVals; ++I) |
0 |
9658 |
for (unsigned I = 1; I != NumVals; ++I) |
0 |
| 9659 |
Ops.push_back(Op.getValue(I)); |
0 |
9659 |
Ops.push_back(Op.getValue(I)); |
0 |
| 9660 |
|
--- |
9660 |
|
--- |
| 9661 |
return DAG.getMergeValues(Ops, SL); |
0 |
9661 |
return DAG.getMergeValues(Ops, SL); |
0 |
| 9662 |
} |
0 |
9662 |
} |
0 |
| 9663 |
|
--- |
9663 |
|
--- |
| 9664 |
/// Populate a CallLowerinInfo (into \p CLI) based on the properties of |
--- |
9664 |
/// Populate a CallLowerinInfo (into \p CLI) based on the properties of |
--- |
| 9665 |
/// the call being lowered. |
--- |
9665 |
/// the call being lowered. |
--- |
| 9666 |
/// |
--- |
9666 |
/// |
--- |
| 9667 |
/// This is a helper for lowering intrinsics that follow a target calling |
--- |
9667 |
/// This is a helper for lowering intrinsics that follow a target calling |
--- |
| 9668 |
/// convention or require stack pointer adjustment. Only a subset of the |
--- |
9668 |
/// convention or require stack pointer adjustment. Only a subset of the |
--- |
| 9669 |
/// intrinsic's operands need to participate in the calling convention. |
--- |
9669 |
/// intrinsic's operands need to participate in the calling convention. |
--- |
| 9670 |
void SelectionDAGBuilder::populateCallLoweringInfo( |
0 |
9670 |
void SelectionDAGBuilder::populateCallLoweringInfo( |
0 |
| 9671 |
TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, |
--- |
9671 |
TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, |
--- |
| 9672 |
unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, |
--- |
9672 |
unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, |
--- |
| 9673 |
bool IsPatchPoint) { |
--- |
9673 |
bool IsPatchPoint) { |
--- |
| 9674 |
TargetLowering::ArgListTy Args; |
0 |
9674 |
TargetLowering::ArgListTy Args; |
0 |
| 9675 |
Args.reserve(NumArgs); |
0 |
9675 |
Args.reserve(NumArgs); |
0 |
| 9676 |
|
--- |
9676 |
|
--- |
| 9677 |
// Populate the argument list. |
--- |
9677 |
// Populate the argument list. |
--- |
| 9678 |
// Attributes for args start at offset 1, after the return attribute. |
--- |
9678 |
// Attributes for args start at offset 1, after the return attribute. |
--- |
| 9679 |
for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; |
0 |
9679 |
for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; |
0 |
| 9680 |
ArgI != ArgE; ++ArgI) { |
0 |
9680 |
ArgI != ArgE; ++ArgI) { |
0 |
| 9681 |
const Value *V = Call->getOperand(ArgI); |
0 |
9681 |
const Value *V = Call->getOperand(ArgI); |
0 |
| 9682 |
|
--- |
9682 |
|
--- |
| 9683 |
assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."); |
0 |
9683 |
assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."); |
0 |
| 9684 |
|
--- |
9684 |
|
--- |
| 9685 |
TargetLowering::ArgListEntry Entry; |
0 |
9685 |
TargetLowering::ArgListEntry Entry; |
0 |
| 9686 |
Entry.Node = getValue(V); |
0 |
9686 |
Entry.Node = getValue(V); |
0 |
| 9687 |
Entry.Ty = V->getType(); |
0 |
9687 |
Entry.Ty = V->getType(); |
0 |
| 9688 |
Entry.setAttributes(Call, ArgI); |
0 |
9688 |
Entry.setAttributes(Call, ArgI); |
0 |
| 9689 |
Args.push_back(Entry); |
0 |
9689 |
Args.push_back(Entry); |
0 |
| 9690 |
} |
--- |
9690 |
} |
--- |
| 9691 |
|
--- |
9691 |
|
--- |
| 9692 |
CLI.setDebugLoc(getCurSDLoc()) |
0 |
9692 |
CLI.setDebugLoc(getCurSDLoc()) |
0 |
| 9693 |
.setChain(getRoot()) |
0 |
9693 |
.setChain(getRoot()) |
0 |
| 9694 |
.setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args)) |
0 |
9694 |
.setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args)) |
0 |
| 9695 |
.setDiscardResult(Call->use_empty()) |
0 |
9695 |
.setDiscardResult(Call->use_empty()) |
0 |
| 9696 |
.setIsPatchPoint(IsPatchPoint) |
0 |
9696 |
.setIsPatchPoint(IsPatchPoint) |
0 |
| 9697 |
.setIsPreallocated( |
0 |
9697 |
.setIsPreallocated( |
0 |
| 9698 |
Call->countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0); |
0 |
9698 |
Call->countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0); |
0 |
| 9699 |
} |
0 |
9699 |
} |
0 |
| 9700 |
|
--- |
9700 |
|
--- |
| 9701 |
/// Add a stack map intrinsic call's live variable operands to a stackmap |
--- |
9701 |
/// Add a stack map intrinsic call's live variable operands to a stackmap |
--- |
| 9702 |
/// or patchpoint target node's operand list. |
--- |
9702 |
/// or patchpoint target node's operand list. |
--- |
| 9703 |
/// |
--- |
9703 |
/// |
--- |
| 9704 |
/// Constants are converted to TargetConstants purely as an optimization to |
--- |
9704 |
/// Constants are converted to TargetConstants purely as an optimization to |
--- |
| 9705 |
/// avoid constant materialization and register allocation. |
--- |
9705 |
/// avoid constant materialization and register allocation. |
--- |
| 9706 |
/// |
--- |
9706 |
/// |
--- |
| 9707 |
/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not |
--- |
9707 |
/// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not |
--- |
| 9708 |
/// generate addess computation nodes, and so FinalizeISel can convert the |
--- |
9708 |
/// generate addess computation nodes, and so FinalizeISel can convert the |
--- |
| 9709 |
/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids |
--- |
9709 |
/// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids |
--- |
| 9710 |
/// address materialization and register allocation, but may also be required |
--- |
9710 |
/// address materialization and register allocation, but may also be required |
--- |
| 9711 |
/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an |
--- |
9711 |
/// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an |
--- |
| 9712 |
/// alloca in the entry block, then the runtime may assume that the alloca's |
--- |
9712 |
/// alloca in the entry block, then the runtime may assume that the alloca's |
--- |
| 9713 |
/// StackMap location can be read immediately after compilation and that the |
--- |
9713 |
/// StackMap location can be read immediately after compilation and that the |
--- |
| 9714 |
/// location is valid at any point during execution (this is similar to the |
--- |
9714 |
/// location is valid at any point during execution (this is similar to the |
--- |
| 9715 |
/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were |
--- |
9715 |
/// assumption made by the llvm.gcroot intrinsic). If the alloca's location were |
--- |
| 9716 |
/// only available in a register, then the runtime would need to trap when |
--- |
9716 |
/// only available in a register, then the runtime would need to trap when |
--- |
| 9717 |
/// execution reaches the StackMap in order to read the alloca's location. |
--- |
9717 |
/// execution reaches the StackMap in order to read the alloca's location. |
--- |
| 9718 |
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, |
0 |
9718 |
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, |
0 |
| 9719 |
const SDLoc &DL, SmallVectorImpl &Ops, |
--- |
9719 |
const SDLoc &DL, SmallVectorImpl &Ops, |
--- |
| 9720 |
SelectionDAGBuilder &Builder) { |
--- |
9720 |
SelectionDAGBuilder &Builder) { |
--- |
| 9721 |
SelectionDAG &DAG = Builder.DAG; |
0 |
9721 |
SelectionDAG &DAG = Builder.DAG; |
0 |
| 9722 |
for (unsigned I = StartIdx; I < Call.arg_size(); I++) { |
0 |
9722 |
for (unsigned I = StartIdx; I < Call.arg_size(); I++) { |
0 |
| 9723 |
SDValue Op = Builder.getValue(Call.getArgOperand(I)); |
0 |
9723 |
SDValue Op = Builder.getValue(Call.getArgOperand(I)); |
0 |
| 9724 |
|
--- |
9724 |
|
--- |
| 9725 |
// Things on the stack are pointer-typed, meaning that they are already |
--- |
9725 |
// Things on the stack are pointer-typed, meaning that they are already |
--- |
| 9726 |
// legal and can be emitted directly to target nodes. |
--- |
9726 |
// legal and can be emitted directly to target nodes. |
--- |
| 9727 |
if (FrameIndexSDNode *FI = dyn_cast(Op)) { |
0 |
9727 |
if (FrameIndexSDNode *FI = dyn_cast(Op)) { |
0 |
| 9728 |
Ops.push_back(DAG.getTargetFrameIndex(FI->getIndex(), Op.getValueType())); |
0 |
9728 |
Ops.push_back(DAG.getTargetFrameIndex(FI->getIndex(), Op.getValueType())); |
0 |
| 9729 |
} else { |
--- |
9729 |
} else { |
--- |
| 9730 |
// Otherwise emit a target independent node to be legalised. |
--- |
9730 |
// Otherwise emit a target independent node to be legalised. |
--- |
| 9731 |
Ops.push_back(Builder.getValue(Call.getArgOperand(I))); |
0 |
9731 |
Ops.push_back(Builder.getValue(Call.getArgOperand(I))); |
0 |
| 9732 |
} |
--- |
9732 |
} |
--- |
| 9733 |
} |
--- |
9733 |
} |
--- |
| 9734 |
} |
0 |
9734 |
} |
0 |
| 9735 |
|
--- |
9735 |
|
--- |
| 9736 |
/// Lower llvm.experimental.stackmap. |
--- |
9736 |
/// Lower llvm.experimental.stackmap. |
--- |
| 9737 |
void SelectionDAGBuilder::visitStackmap(const CallInst &CI) { |
0 |
9737 |
void SelectionDAGBuilder::visitStackmap(const CallInst &CI) { |
0 |
| 9738 |
// void @llvm.experimental.stackmap(i64 , i32 , |
--- |
9738 |
// void @llvm.experimental.stackmap(i64 , i32 , |
--- |
| 9739 |
// [live variables...]) |
--- |
9739 |
// [live variables...]) |
--- |
| 9740 |
|
--- |
9740 |
|
--- |
| 9741 |
assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value."); |
0 |
9741 |
assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value."); |
0 |
| 9742 |
|
--- |
9742 |
|
--- |
| 9743 |
SDValue Chain, InGlue, Callee; |
0 |
9743 |
SDValue Chain, InGlue, Callee; |
0 |
| 9744 |
SmallVector Ops; |
0 |
9744 |
SmallVector Ops; |
0 |
| 9745 |
|
--- |
9745 |
|
--- |
| 9746 |
SDLoc DL = getCurSDLoc(); |
0 |
9746 |
SDLoc DL = getCurSDLoc(); |
0 |
| 9747 |
Callee = getValue(CI.getCalledOperand()); |
0 |
9747 |
Callee = getValue(CI.getCalledOperand()); |
0 |
| 9748 |
|
--- |
9748 |
|
--- |
| 9749 |
// The stackmap intrinsic only records the live variables (the arguments |
--- |
9749 |
// The stackmap intrinsic only records the live variables (the arguments |
--- |
| 9750 |
// passed to it) and emits NOPS (if requested). Unlike the patchpoint |
--- |
9750 |
// passed to it) and emits NOPS (if requested). Unlike the patchpoint |
--- |
| 9751 |
// intrinsic, this won't be lowered to a function call. This means we don't |
--- |
9751 |
// intrinsic, this won't be lowered to a function call. This means we don't |
--- |
| 9752 |
// have to worry about calling conventions and target specific lowering code. |
--- |
9752 |
// have to worry about calling conventions and target specific lowering code. |
--- |
| 9753 |
// Instead we perform the call lowering right here. |
--- |
9753 |
// Instead we perform the call lowering right here. |
--- |
| 9754 |
// |
--- |
9754 |
// |
--- |
| 9755 |
// chain, flag = CALLSEQ_START(chain, 0, 0) |
--- |
9755 |
// chain, flag = CALLSEQ_START(chain, 0, 0) |
--- |
| 9756 |
// chain, flag = STACKMAP(id, nbytes, ..., chain, flag) |
--- |
9756 |
// chain, flag = STACKMAP(id, nbytes, ..., chain, flag) |
--- |
| 9757 |
// chain, flag = CALLSEQ_END(chain, 0, 0, flag) |
--- |
9757 |
// chain, flag = CALLSEQ_END(chain, 0, 0, flag) |
--- |
| 9758 |
// |
--- |
9758 |
// |
--- |
| 9759 |
Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL); |
0 |
9759 |
Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL); |
0 |
| 9760 |
InGlue = Chain.getValue(1); |
0 |
9760 |
InGlue = Chain.getValue(1); |
0 |
| 9761 |
|
--- |
9761 |
|
--- |
| 9762 |
// Add the STACKMAP operands, starting with DAG house-keeping. |
--- |
9762 |
// Add the STACKMAP operands, starting with DAG house-keeping. |
--- |
| 9763 |
Ops.push_back(Chain); |
0 |
9763 |
Ops.push_back(Chain); |
0 |
| 9764 |
Ops.push_back(InGlue); |
0 |
9764 |
Ops.push_back(InGlue); |
0 |
| 9765 |
|
--- |
9765 |
|
--- |
| 9766 |
// Add the , operands. |
--- |
9766 |
// Add the , operands. |
--- |
| 9767 |
// |
--- |
9767 |
// |
--- |
| 9768 |
// These do not require legalisation, and can be emitted directly to target |
--- |
9768 |
// These do not require legalisation, and can be emitted directly to target |
--- |
| 9769 |
// constant nodes. |
--- |
9769 |
// constant nodes. |
--- |
| 9770 |
SDValue ID = getValue(CI.getArgOperand(0)); |
0 |
9770 |
SDValue ID = getValue(CI.getArgOperand(0)); |
0 |
| 9771 |
assert(ID.getValueType() == MVT::i64); |
0 |
9771 |
assert(ID.getValueType() == MVT::i64); |
0 |
| 9772 |
SDValue IDConst = DAG.getTargetConstant( |
0 |
9772 |
SDValue IDConst = DAG.getTargetConstant( |
0 |
| 9773 |
cast(ID)->getZExtValue(), DL, ID.getValueType()); |
--- |
9773 |
cast(ID)->getZExtValue(), DL, ID.getValueType()); |
--- |
| 9774 |
Ops.push_back(IDConst); |
0 |
9774 |
Ops.push_back(IDConst); |
0 |
| 9775 |
|
--- |
9775 |
|
--- |
| 9776 |
SDValue Shad = getValue(CI.getArgOperand(1)); |
0 |
9776 |
SDValue Shad = getValue(CI.getArgOperand(1)); |
0 |
| 9777 |
assert(Shad.getValueType() == MVT::i32); |
0 |
9777 |
assert(Shad.getValueType() == MVT::i32); |
0 |
| 9778 |
SDValue ShadConst = DAG.getTargetConstant( |
0 |
9778 |
SDValue ShadConst = DAG.getTargetConstant( |
0 |
| 9779 |
cast(Shad)->getZExtValue(), DL, Shad.getValueType()); |
--- |
9779 |
cast(Shad)->getZExtValue(), DL, Shad.getValueType()); |
--- |
| 9780 |
Ops.push_back(ShadConst); |
0 |
9780 |
Ops.push_back(ShadConst); |
0 |
| 9781 |
|
--- |
9781 |
|
--- |
| 9782 |
// Add the live variables. |
--- |
9782 |
// Add the live variables. |
--- |
| 9783 |
addStackMapLiveVars(CI, 2, DL, Ops, *this); |
0 |
9783 |
addStackMapLiveVars(CI, 2, DL, Ops, *this); |
0 |
| 9784 |
|
--- |
9784 |
|
--- |
| 9785 |
// Create the STACKMAP node. |
--- |
9785 |
// Create the STACKMAP node. |
--- |
| 9786 |
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
9786 |
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
| 9787 |
Chain = DAG.getNode(ISD::STACKMAP, DL, NodeTys, Ops); |
0 |
9787 |
Chain = DAG.getNode(ISD::STACKMAP, DL, NodeTys, Ops); |
0 |
| 9788 |
InGlue = Chain.getValue(1); |
0 |
9788 |
InGlue = Chain.getValue(1); |
0 |
| 9789 |
|
--- |
9789 |
|
--- |
| 9790 |
Chain = DAG.getCALLSEQ_END(Chain, 0, 0, InGlue, DL); |
0 |
9790 |
Chain = DAG.getCALLSEQ_END(Chain, 0, 0, InGlue, DL); |
0 |
| 9791 |
|
--- |
9791 |
|
--- |
| 9792 |
// Stackmaps don't generate values, so nothing goes into the NodeMap. |
--- |
9792 |
// Stackmaps don't generate values, so nothing goes into the NodeMap. |
--- |
| 9793 |
|
--- |
9793 |
|
--- |
| 9794 |
// Set the root to the target-lowered call chain. |
--- |
9794 |
// Set the root to the target-lowered call chain. |
--- |
| 9795 |
DAG.setRoot(Chain); |
0 |
9795 |
DAG.setRoot(Chain); |
0 |
| 9796 |
|
--- |
9796 |
|
--- |
| 9797 |
// Inform the Frame Information that we have a stackmap in this function. |
--- |
9797 |
// Inform the Frame Information that we have a stackmap in this function. |
--- |
| 9798 |
FuncInfo.MF->getFrameInfo().setHasStackMap(); |
0 |
9798 |
FuncInfo.MF->getFrameInfo().setHasStackMap(); |
0 |
| 9799 |
} |
0 |
9799 |
} |
0 |
| 9800 |
|
--- |
9800 |
|
--- |
| 9801 |
/// Lower llvm.experimental.patchpoint directly to its target opcode. |
--- |
9801 |
/// Lower llvm.experimental.patchpoint directly to its target opcode. |
--- |
| 9802 |
void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB, |
0 |
9802 |
void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB, |
0 |
| 9803 |
const BasicBlock *EHPadBB) { |
--- |
9803 |
const BasicBlock *EHPadBB) { |
--- |
| 9804 |
// void|i64 @llvm.experimental.patchpoint.void|i64(i64 , |
--- |
9804 |
// void|i64 @llvm.experimental.patchpoint.void|i64(i64 , |
--- |
| 9805 |
// i32 , |
--- |
9805 |
// i32 , |
--- |
| 9806 |
// i8* , |
--- |
9806 |
// i8* , |
--- |
| 9807 |
// i32 , |
--- |
9807 |
// i32 , |
--- |
| 9808 |
// [Args...], |
--- |
9808 |
// [Args...], |
--- |
| 9809 |
// [live variables...]) |
--- |
9809 |
// [live variables...]) |
--- |
| 9810 |
|
--- |
9810 |
|
--- |
| 9811 |
CallingConv::ID CC = CB.getCallingConv(); |
0 |
9811 |
CallingConv::ID CC = CB.getCallingConv(); |
0 |
| 9812 |
bool IsAnyRegCC = CC == CallingConv::AnyReg; |
0 |
9812 |
bool IsAnyRegCC = CC == CallingConv::AnyReg; |
0 |
| 9813 |
bool HasDef = !CB.getType()->isVoidTy(); |
0 |
9813 |
bool HasDef = !CB.getType()->isVoidTy(); |
0 |
| 9814 |
SDLoc dl = getCurSDLoc(); |
0 |
9814 |
SDLoc dl = getCurSDLoc(); |
0 |
| 9815 |
SDValue Callee = getValue(CB.getArgOperand(PatchPointOpers::TargetPos)); |
0 |
9815 |
SDValue Callee = getValue(CB.getArgOperand(PatchPointOpers::TargetPos)); |
0 |
| 9816 |
|
--- |
9816 |
|
--- |
| 9817 |
// Handle immediate and symbolic callees. |
--- |
9817 |
// Handle immediate and symbolic callees. |
--- |
| 9818 |
if (auto* ConstCallee = dyn_cast(Callee)) |
0 |
9818 |
if (auto* ConstCallee = dyn_cast(Callee)) |
0 |
| 9819 |
Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl, |
0 |
9819 |
Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl, |
0 |
| 9820 |
/*isTarget=*/true); |
--- |
9820 |
/*isTarget=*/true); |
--- |
| 9821 |
else if (auto* SymbolicCallee = dyn_cast(Callee)) |
0 |
9821 |
else if (auto* SymbolicCallee = dyn_cast(Callee)) |
0 |
| 9822 |
Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(), |
0 |
9822 |
Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(), |
0 |
| 9823 |
SDLoc(SymbolicCallee), |
0 |
9823 |
SDLoc(SymbolicCallee), |
0 |
| 9824 |
SymbolicCallee->getValueType(0)); |
--- |
9824 |
SymbolicCallee->getValueType(0)); |
--- |
| 9825 |
|
--- |
9825 |
|
--- |
| 9826 |
// Get the real number of arguments participating in the call |
--- |
9826 |
// Get the real number of arguments participating in the call |
--- |
| 9827 |
SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos)); |
0 |
9827 |
SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos)); |
0 |
| 9828 |
unsigned NumArgs = cast(NArgVal)->getZExtValue(); |
0 |
9828 |
unsigned NumArgs = cast(NArgVal)->getZExtValue(); |
0 |
| 9829 |
|
--- |
9829 |
|
--- |
| 9830 |
// Skip the four meta args: , , , |
--- |
9830 |
// Skip the four meta args: , , , |
--- |
| 9831 |
// Intrinsics include all meta-operands up to but not including CC. |
--- |
9831 |
// Intrinsics include all meta-operands up to but not including CC. |
--- |
| 9832 |
unsigned NumMetaOpers = PatchPointOpers::CCPos; |
0 |
9832 |
unsigned NumMetaOpers = PatchPointOpers::CCPos; |
0 |
| 9833 |
assert(CB.arg_size() >= NumMetaOpers + NumArgs && |
0 |
9833 |
assert(CB.arg_size() >= NumMetaOpers + NumArgs && |
0 |
| 9834 |
"Not enough arguments provided to the patchpoint intrinsic"); |
--- |
9834 |
"Not enough arguments provided to the patchpoint intrinsic"); |
--- |
| 9835 |
|
--- |
9835 |
|
--- |
| 9836 |
// For AnyRegCC the arguments are lowered later on manually. |
--- |
9836 |
// For AnyRegCC the arguments are lowered later on manually. |
--- |
| 9837 |
unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs; |
0 |
9837 |
unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs; |
0 |
| 9838 |
Type *ReturnTy = |
--- |
9838 |
Type *ReturnTy = |
--- |
| 9839 |
IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CB.getType(); |
0 |
9839 |
IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CB.getType(); |
0 |
| 9840 |
|
--- |
9840 |
|
--- |
| 9841 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
9841 |
TargetLowering::CallLoweringInfo CLI(DAG); |
0 |
| 9842 |
populateCallLoweringInfo(CLI, &CB, NumMetaOpers, NumCallArgs, Callee, |
0 |
9842 |
populateCallLoweringInfo(CLI, &CB, NumMetaOpers, NumCallArgs, Callee, |
0 |
| 9843 |
ReturnTy, true); |
--- |
9843 |
ReturnTy, true); |
--- |
| 9844 |
std::pair Result = lowerInvokable(CLI, EHPadBB); |
0 |
9844 |
std::pair Result = lowerInvokable(CLI, EHPadBB); |
0 |
| 9845 |
|
--- |
9845 |
|
--- |
| 9846 |
SDNode *CallEnd = Result.second.getNode(); |
0 |
9846 |
SDNode *CallEnd = Result.second.getNode(); |
0 |
| 9847 |
if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) |
0 |
9847 |
if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) |
0 |
| 9848 |
CallEnd = CallEnd->getOperand(0).getNode(); |
0 |
9848 |
CallEnd = CallEnd->getOperand(0).getNode(); |
0 |
| 9849 |
|
--- |
9849 |
|
--- |
| 9850 |
/// Get a call instruction from the call sequence chain. |
--- |
9850 |
/// Get a call instruction from the call sequence chain. |
--- |
| 9851 |
/// Tail calls are not allowed. |
--- |
9851 |
/// Tail calls are not allowed. |
--- |
| 9852 |
assert(CallEnd->getOpcode() == ISD::CALLSEQ_END && |
0 |
9852 |
assert(CallEnd->getOpcode() == ISD::CALLSEQ_END && |
0 |
| 9853 |
"Expected a callseq node."); |
--- |
9853 |
"Expected a callseq node."); |
--- |
| 9854 |
SDNode *Call = CallEnd->getOperand(0).getNode(); |
0 |
9854 |
SDNode *Call = CallEnd->getOperand(0).getNode(); |
0 |
| 9855 |
bool HasGlue = Call->getGluedNode(); |
0 |
9855 |
bool HasGlue = Call->getGluedNode(); |
0 |
| 9856 |
|
--- |
9856 |
|
--- |
| 9857 |
// Replace the target specific call node with the patchable intrinsic. |
--- |
9857 |
// Replace the target specific call node with the patchable intrinsic. |
--- |
| 9858 |
SmallVector Ops; |
0 |
9858 |
SmallVector Ops; |
0 |
| 9859 |
|
--- |
9859 |
|
--- |
| 9860 |
// Push the chain. |
--- |
9860 |
// Push the chain. |
--- |
| 9861 |
Ops.push_back(*(Call->op_begin())); |
0 |
9861 |
Ops.push_back(*(Call->op_begin())); |
0 |
| 9862 |
|
--- |
9862 |
|
--- |
| 9863 |
// Optionally, push the glue (if any). |
--- |
9863 |
// Optionally, push the glue (if any). |
--- |
| 9864 |
if (HasGlue) |
0 |
9864 |
if (HasGlue) |
0 |
| 9865 |
Ops.push_back(*(Call->op_end() - 1)); |
0 |
9865 |
Ops.push_back(*(Call->op_end() - 1)); |
0 |
| 9866 |
|
--- |
9866 |
|
--- |
| 9867 |
// Push the register mask info. |
--- |
9867 |
// Push the register mask info. |
--- |
| 9868 |
if (HasGlue) |
0 |
9868 |
if (HasGlue) |
0 |
| 9869 |
Ops.push_back(*(Call->op_end() - 2)); |
0 |
9869 |
Ops.push_back(*(Call->op_end() - 2)); |
0 |
| 9870 |
else |
--- |
9870 |
else |
--- |
| 9871 |
Ops.push_back(*(Call->op_end() - 1)); |
0 |
9871 |
Ops.push_back(*(Call->op_end() - 1)); |
0 |
| 9872 |
|
--- |
9872 |
|
--- |
| 9873 |
// Add the and constants. |
--- |
9873 |
// Add the and constants. |
--- |
| 9874 |
SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos)); |
0 |
9874 |
SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos)); |
0 |
| 9875 |
Ops.push_back(DAG.getTargetConstant( |
0 |
9875 |
Ops.push_back(DAG.getTargetConstant( |
0 |
| 9876 |
cast(IDVal)->getZExtValue(), dl, MVT::i64)); |
--- |
9876 |
cast(IDVal)->getZExtValue(), dl, MVT::i64)); |
--- |
| 9877 |
SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos)); |
0 |
9877 |
SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos)); |
0 |
| 9878 |
Ops.push_back(DAG.getTargetConstant( |
0 |
9878 |
Ops.push_back(DAG.getTargetConstant( |
0 |
| 9879 |
cast(NBytesVal)->getZExtValue(), dl, |
--- |
9879 |
cast(NBytesVal)->getZExtValue(), dl, |
--- |
| 9880 |
MVT::i32)); |
--- |
9880 |
MVT::i32)); |
--- |
| 9881 |
|
--- |
9881 |
|
--- |
| 9882 |
// Add the callee. |
--- |
9882 |
// Add the callee. |
--- |
| 9883 |
Ops.push_back(Callee); |
0 |
9883 |
Ops.push_back(Callee); |
0 |
| 9884 |
|
--- |
9884 |
|
--- |
| 9885 |
// Adjust to account for any arguments that have been passed on the |
--- |
9885 |
// Adjust to account for any arguments that have been passed on the |
--- |
| 9886 |
// stack instead. |
--- |
9886 |
// stack instead. |
--- |
| 9887 |
// Call Node: Chain, Target, {Args}, RegMask, [Glue] |
--- |
9887 |
// Call Node: Chain, Target, {Args}, RegMask, [Glue] |
--- |
| 9888 |
unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3); |
0 |
9888 |
unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3); |
0 |
| 9889 |
NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs; |
0 |
9889 |
NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs; |
0 |
| 9890 |
Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32)); |
0 |
9890 |
Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32)); |
0 |
| 9891 |
|
--- |
9891 |
|
--- |
| 9892 |
// Add the calling convention |
--- |
9892 |
// Add the calling convention |
--- |
| 9893 |
Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32)); |
0 |
9893 |
Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32)); |
0 |
| 9894 |
|
--- |
9894 |
|
--- |
| 9895 |
// Add the arguments we omitted previously. The register allocator should |
--- |
9895 |
// Add the arguments we omitted previously. The register allocator should |
--- |
| 9896 |
// place these in any free register. |
--- |
9896 |
// place these in any free register. |
--- |
| 9897 |
if (IsAnyRegCC) |
0 |
9897 |
if (IsAnyRegCC) |
0 |
| 9898 |
for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) |
0 |
9898 |
for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) |
0 |
| 9899 |
Ops.push_back(getValue(CB.getArgOperand(i))); |
0 |
9899 |
Ops.push_back(getValue(CB.getArgOperand(i))); |
0 |
| 9900 |
|
--- |
9900 |
|
--- |
| 9901 |
// Push the arguments from the call instruction. |
--- |
9901 |
// Push the arguments from the call instruction. |
--- |
| 9902 |
SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1; |
0 |
9902 |
SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1; |
0 |
| 9903 |
Ops.append(Call->op_begin() + 2, e); |
0 |
9903 |
Ops.append(Call->op_begin() + 2, e); |
0 |
| 9904 |
|
--- |
9904 |
|
--- |
| 9905 |
// Push live variables for the stack map. |
--- |
9905 |
// Push live variables for the stack map. |
--- |
| 9906 |
addStackMapLiveVars(CB, NumMetaOpers + NumArgs, dl, Ops, *this); |
0 |
9906 |
addStackMapLiveVars(CB, NumMetaOpers + NumArgs, dl, Ops, *this); |
0 |
| 9907 |
|
--- |
9907 |
|
--- |
| 9908 |
SDVTList NodeTys; |
--- |
9908 |
SDVTList NodeTys; |
--- |
| 9909 |
if (IsAnyRegCC && HasDef) { |
0 |
9909 |
if (IsAnyRegCC && HasDef) { |
0 |
| 9910 |
// Create the return types based on the intrinsic definition |
--- |
9910 |
// Create the return types based on the intrinsic definition |
--- |
| 9911 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
9911 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 9912 |
SmallVector ValueVTs; |
0 |
9912 |
SmallVector ValueVTs; |
0 |
| 9913 |
ComputeValueVTs(TLI, DAG.getDataLayout(), CB.getType(), ValueVTs); |
0 |
9913 |
ComputeValueVTs(TLI, DAG.getDataLayout(), CB.getType(), ValueVTs); |
0 |
| 9914 |
assert(ValueVTs.size() == 1 && "Expected only one return value type."); |
0 |
9914 |
assert(ValueVTs.size() == 1 && "Expected only one return value type."); |
0 |
| 9915 |
|
--- |
9915 |
|
--- |
| 9916 |
// There is always a chain and a glue type at the end |
--- |
9916 |
// There is always a chain and a glue type at the end |
--- |
| 9917 |
ValueVTs.push_back(MVT::Other); |
0 |
9917 |
ValueVTs.push_back(MVT::Other); |
0 |
| 9918 |
ValueVTs.push_back(MVT::Glue); |
0 |
9918 |
ValueVTs.push_back(MVT::Glue); |
0 |
| 9919 |
NodeTys = DAG.getVTList(ValueVTs); |
0 |
9919 |
NodeTys = DAG.getVTList(ValueVTs); |
0 |
| 9920 |
} else |
0 |
9920 |
} else |
0 |
| 9921 |
NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
9921 |
NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
0 |
| 9922 |
|
--- |
9922 |
|
--- |
| 9923 |
// Replace the target specific call node with a PATCHPOINT node. |
--- |
9923 |
// Replace the target specific call node with a PATCHPOINT node. |
--- |
| 9924 |
SDValue PPV = DAG.getNode(ISD::PATCHPOINT, dl, NodeTys, Ops); |
0 |
9924 |
SDValue PPV = DAG.getNode(ISD::PATCHPOINT, dl, NodeTys, Ops); |
0 |
| 9925 |
|
--- |
9925 |
|
--- |
| 9926 |
// Update the NodeMap. |
--- |
9926 |
// Update the NodeMap. |
--- |
| 9927 |
if (HasDef) { |
0 |
9927 |
if (HasDef) { |
0 |
| 9928 |
if (IsAnyRegCC) |
0 |
9928 |
if (IsAnyRegCC) |
0 |
| 9929 |
setValue(&CB, SDValue(PPV.getNode(), 0)); |
0 |
9929 |
setValue(&CB, SDValue(PPV.getNode(), 0)); |
0 |
| 9930 |
else |
--- |
9930 |
else |
--- |
| 9931 |
setValue(&CB, Result.first); |
0 |
9931 |
setValue(&CB, Result.first); |
0 |
| 9932 |
} |
--- |
9932 |
} |
--- |
| 9933 |
|
--- |
9933 |
|
--- |
| 9934 |
// Fixup the consumers of the intrinsic. The chain and glue may be used in the |
--- |
9934 |
// Fixup the consumers of the intrinsic. The chain and glue may be used in the |
--- |
| 9935 |
// call sequence. Furthermore the location of the chain and glue can change |
--- |
9935 |
// call sequence. Furthermore the location of the chain and glue can change |
--- |
| 9936 |
// when the AnyReg calling convention is used and the intrinsic returns a |
--- |
9936 |
// when the AnyReg calling convention is used and the intrinsic returns a |
--- |
| 9937 |
// value. |
--- |
9937 |
// value. |
--- |
| 9938 |
if (IsAnyRegCC && HasDef) { |
0 |
9938 |
if (IsAnyRegCC && HasDef) { |
0 |
| 9939 |
SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)}; |
0 |
9939 |
SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)}; |
0 |
| 9940 |
SDValue To[] = {PPV.getValue(1), PPV.getValue(2)}; |
0 |
9940 |
SDValue To[] = {PPV.getValue(1), PPV.getValue(2)}; |
0 |
| 9941 |
DAG.ReplaceAllUsesOfValuesWith(From, To, 2); |
0 |
9941 |
DAG.ReplaceAllUsesOfValuesWith(From, To, 2); |
0 |
| 9942 |
} else |
0 |
9942 |
} else |
0 |
| 9943 |
DAG.ReplaceAllUsesWith(Call, PPV.getNode()); |
0 |
9943 |
DAG.ReplaceAllUsesWith(Call, PPV.getNode()); |
0 |
| 9944 |
DAG.DeleteNode(Call); |
0 |
9944 |
DAG.DeleteNode(Call); |
0 |
| 9945 |
|
--- |
9945 |
|
--- |
| 9946 |
// Inform the Frame Information that we have a patchpoint in this function. |
--- |
9946 |
// Inform the Frame Information that we have a patchpoint in this function. |
--- |
| 9947 |
FuncInfo.MF->getFrameInfo().setHasPatchPoint(); |
0 |
9947 |
FuncInfo.MF->getFrameInfo().setHasPatchPoint(); |
0 |
| 9948 |
} |
0 |
9948 |
} |
0 |
| 9949 |
|
--- |
9949 |
|
--- |
| 9950 |
void SelectionDAGBuilder::visitVectorReduce(const CallInst &I, |
0 |
9950 |
void SelectionDAGBuilder::visitVectorReduce(const CallInst &I, |
0 |
| 9951 |
unsigned Intrinsic) { |
--- |
9951 |
unsigned Intrinsic) { |
--- |
| 9952 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
9952 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 9953 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
9953 |
SDValue Op1 = getValue(I.getArgOperand(0)); |
0 |
| 9954 |
SDValue Op2; |
0 |
9954 |
SDValue Op2; |
0 |
| 9955 |
if (I.arg_size() > 1) |
0 |
9955 |
if (I.arg_size() > 1) |
0 |
| 9956 |
Op2 = getValue(I.getArgOperand(1)); |
0 |
9956 |
Op2 = getValue(I.getArgOperand(1)); |
0 |
| 9957 |
SDLoc dl = getCurSDLoc(); |
0 |
9957 |
SDLoc dl = getCurSDLoc(); |
0 |
| 9958 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
9958 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 9959 |
SDValue Res; |
0 |
9959 |
SDValue Res; |
0 |
| 9960 |
SDNodeFlags SDFlags; |
0 |
9960 |
SDNodeFlags SDFlags; |
0 |
| 9961 |
if (auto *FPMO = dyn_cast(&I)) |
0 |
9961 |
if (auto *FPMO = dyn_cast(&I)) |
0 |
| 9962 |
SDFlags.copyFMF(*FPMO); |
0 |
9962 |
SDFlags.copyFMF(*FPMO); |
0 |
| 9963 |
|
--- |
9963 |
|
--- |
| 9964 |
switch (Intrinsic) { |
0 |
9964 |
switch (Intrinsic) { |
0 |
| 9965 |
case Intrinsic::vector_reduce_fadd: |
0 |
9965 |
case Intrinsic::vector_reduce_fadd: |
0 |
| 9966 |
if (SDFlags.hasAllowReassociation()) |
0 |
9966 |
if (SDFlags.hasAllowReassociation()) |
0 |
| 9967 |
Res = DAG.getNode(ISD::FADD, dl, VT, Op1, |
0 |
9967 |
Res = DAG.getNode(ISD::FADD, dl, VT, Op1, |
0 |
| 9968 |
DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags), |
0 |
9968 |
DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags), |
0 |
| 9969 |
SDFlags); |
--- |
9969 |
SDFlags); |
--- |
| 9970 |
else |
--- |
9970 |
else |
--- |
| 9971 |
Res = DAG.getNode(ISD::VECREDUCE_SEQ_FADD, dl, VT, Op1, Op2, SDFlags); |
0 |
9971 |
Res = DAG.getNode(ISD::VECREDUCE_SEQ_FADD, dl, VT, Op1, Op2, SDFlags); |
0 |
| 9972 |
break; |
0 |
9972 |
break; |
0 |
| 9973 |
case Intrinsic::vector_reduce_fmul: |
0 |
9973 |
case Intrinsic::vector_reduce_fmul: |
0 |
| 9974 |
if (SDFlags.hasAllowReassociation()) |
0 |
9974 |
if (SDFlags.hasAllowReassociation()) |
0 |
| 9975 |
Res = DAG.getNode(ISD::FMUL, dl, VT, Op1, |
0 |
9975 |
Res = DAG.getNode(ISD::FMUL, dl, VT, Op1, |
0 |
| 9976 |
DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags), |
0 |
9976 |
DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags), |
0 |
| 9977 |
SDFlags); |
--- |
9977 |
SDFlags); |
--- |
| 9978 |
else |
--- |
9978 |
else |
--- |
| 9979 |
Res = DAG.getNode(ISD::VECREDUCE_SEQ_FMUL, dl, VT, Op1, Op2, SDFlags); |
0 |
9979 |
Res = DAG.getNode(ISD::VECREDUCE_SEQ_FMUL, dl, VT, Op1, Op2, SDFlags); |
0 |
| 9980 |
break; |
0 |
9980 |
break; |
0 |
| 9981 |
case Intrinsic::vector_reduce_add: |
0 |
9981 |
case Intrinsic::vector_reduce_add: |
0 |
| 9982 |
Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); |
0 |
9982 |
Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); |
0 |
| 9983 |
break; |
0 |
9983 |
break; |
0 |
| 9984 |
case Intrinsic::vector_reduce_mul: |
0 |
9984 |
case Intrinsic::vector_reduce_mul: |
0 |
| 9985 |
Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1); |
0 |
9985 |
Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1); |
0 |
| 9986 |
break; |
0 |
9986 |
break; |
0 |
| 9987 |
case Intrinsic::vector_reduce_and: |
0 |
9987 |
case Intrinsic::vector_reduce_and: |
0 |
| 9988 |
Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); |
0 |
9988 |
Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); |
0 |
| 9989 |
break; |
0 |
9989 |
break; |
0 |
| 9990 |
case Intrinsic::vector_reduce_or: |
0 |
9990 |
case Intrinsic::vector_reduce_or: |
0 |
| 9991 |
Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); |
0 |
9991 |
Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); |
0 |
| 9992 |
break; |
0 |
9992 |
break; |
0 |
| 9993 |
case Intrinsic::vector_reduce_xor: |
0 |
9993 |
case Intrinsic::vector_reduce_xor: |
0 |
| 9994 |
Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); |
0 |
9994 |
Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); |
0 |
| 9995 |
break; |
0 |
9995 |
break; |
0 |
| 9996 |
case Intrinsic::vector_reduce_smax: |
0 |
9996 |
case Intrinsic::vector_reduce_smax: |
0 |
| 9997 |
Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); |
0 |
9997 |
Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); |
0 |
| 9998 |
break; |
0 |
9998 |
break; |
0 |
| 9999 |
case Intrinsic::vector_reduce_smin: |
0 |
9999 |
case Intrinsic::vector_reduce_smin: |
0 |
| 10000 |
Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); |
0 |
10000 |
Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); |
0 |
| 10001 |
break; |
0 |
10001 |
break; |
0 |
| 10002 |
case Intrinsic::vector_reduce_umax: |
0 |
10002 |
case Intrinsic::vector_reduce_umax: |
0 |
| 10003 |
Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1); |
0 |
10003 |
Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1); |
0 |
| 10004 |
break; |
0 |
10004 |
break; |
0 |
| 10005 |
case Intrinsic::vector_reduce_umin: |
0 |
10005 |
case Intrinsic::vector_reduce_umin: |
0 |
| 10006 |
Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1); |
0 |
10006 |
Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1); |
0 |
| 10007 |
break; |
0 |
10007 |
break; |
0 |
| 10008 |
case Intrinsic::vector_reduce_fmax: |
0 |
10008 |
case Intrinsic::vector_reduce_fmax: |
0 |
| 10009 |
Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); |
0 |
10009 |
Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); |
0 |
| 10010 |
break; |
0 |
10010 |
break; |
0 |
| 10011 |
case Intrinsic::vector_reduce_fmin: |
0 |
10011 |
case Intrinsic::vector_reduce_fmin: |
0 |
| 10012 |
Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags); |
0 |
10012 |
Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags); |
0 |
| 10013 |
break; |
0 |
10013 |
break; |
0 |
| 10014 |
case Intrinsic::vector_reduce_fmaximum: |
0 |
10014 |
case Intrinsic::vector_reduce_fmaximum: |
0 |
| 10015 |
Res = DAG.getNode(ISD::VECREDUCE_FMAXIMUM, dl, VT, Op1, SDFlags); |
0 |
10015 |
Res = DAG.getNode(ISD::VECREDUCE_FMAXIMUM, dl, VT, Op1, SDFlags); |
0 |
| 10016 |
break; |
0 |
10016 |
break; |
0 |
| 10017 |
case Intrinsic::vector_reduce_fminimum: |
0 |
10017 |
case Intrinsic::vector_reduce_fminimum: |
0 |
| 10018 |
Res = DAG.getNode(ISD::VECREDUCE_FMINIMUM, dl, VT, Op1, SDFlags); |
0 |
10018 |
Res = DAG.getNode(ISD::VECREDUCE_FMINIMUM, dl, VT, Op1, SDFlags); |
0 |
| 10019 |
break; |
0 |
10019 |
break; |
0 |
| 10020 |
default: |
0 |
10020 |
default: |
0 |
| 10021 |
llvm_unreachable("Unhandled vector reduce intrinsic"); |
0 |
10021 |
llvm_unreachable("Unhandled vector reduce intrinsic"); |
0 |
| 10022 |
} |
--- |
10022 |
} |
--- |
| 10023 |
setValue(&I, Res); |
0 |
10023 |
setValue(&I, Res); |
0 |
| 10024 |
} |
0 |
10024 |
} |
0 |
| 10025 |
|
--- |
10025 |
|
--- |
| 10026 |
/// Returns an AttributeList representing the attributes applied to the return |
--- |
10026 |
/// Returns an AttributeList representing the attributes applied to the return |
--- |
| 10027 |
/// value of the given call. |
--- |
10027 |
/// value of the given call. |
--- |
| 10028 |
static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) { |
0 |
10028 |
static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) { |
0 |
| 10029 |
SmallVector Attrs; |
0 |
10029 |
SmallVector Attrs; |
0 |
| 10030 |
if (CLI.RetSExt) |
0 |
10030 |
if (CLI.RetSExt) |
0 |
| 10031 |
Attrs.push_back(Attribute::SExt); |
0 |
10031 |
Attrs.push_back(Attribute::SExt); |
0 |
| 10032 |
if (CLI.RetZExt) |
0 |
10032 |
if (CLI.RetZExt) |
0 |
| 10033 |
Attrs.push_back(Attribute::ZExt); |
0 |
10033 |
Attrs.push_back(Attribute::ZExt); |
0 |
| 10034 |
if (CLI.IsInReg) |
0 |
10034 |
if (CLI.IsInReg) |
0 |
| 10035 |
Attrs.push_back(Attribute::InReg); |
0 |
10035 |
Attrs.push_back(Attribute::InReg); |
0 |
| 10036 |
|
--- |
10036 |
|
--- |
| 10037 |
return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex, |
0 |
10037 |
return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex, |
0 |
| 10038 |
Attrs); |
0 |
10038 |
Attrs); |
0 |
| 10039 |
} |
0 |
10039 |
} |
0 |
| 10040 |
|
--- |
10040 |
|
--- |
| 10041 |
/// TargetLowering::LowerCallTo - This is the default LowerCallTo |
--- |
10041 |
/// TargetLowering::LowerCallTo - This is the default LowerCallTo |
--- |
| 10042 |
/// implementation, which just calls LowerCall. |
--- |
10042 |
/// implementation, which just calls LowerCall. |
--- |
| 10043 |
/// FIXME: When all targets are |
--- |
10043 |
/// FIXME: When all targets are |
--- |
| 10044 |
/// migrated to using LowerCall, this hook should be integrated into SDISel. |
--- |
10044 |
/// migrated to using LowerCall, this hook should be integrated into SDISel. |
--- |
| 10045 |
std::pair |
--- |
10045 |
std::pair |
--- |
| 10046 |
TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { |
0 |
10046 |
TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { |
0 |
| 10047 |
// Handle the incoming return values from the call. |
--- |
10047 |
// Handle the incoming return values from the call. |
--- |
| 10048 |
CLI.Ins.clear(); |
0 |
10048 |
CLI.Ins.clear(); |
0 |
| 10049 |
Type *OrigRetTy = CLI.RetTy; |
0 |
10049 |
Type *OrigRetTy = CLI.RetTy; |
0 |
| 10050 |
SmallVector RetTys; |
0 |
10050 |
SmallVector RetTys; |
0 |
| 10051 |
SmallVector Offsets; |
0 |
10051 |
SmallVector Offsets; |
0 |
| 10052 |
auto &DL = CLI.DAG.getDataLayout(); |
0 |
10052 |
auto &DL = CLI.DAG.getDataLayout(); |
0 |
| 10053 |
ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets, 0); |
0 |
10053 |
ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets, 0); |
0 |
| 10054 |
|
--- |
10054 |
|
--- |
| 10055 |
if (CLI.IsPostTypeLegalization) { |
0 |
10055 |
if (CLI.IsPostTypeLegalization) { |
0 |
| 10056 |
// If we are lowering a libcall after legalization, split the return type. |
--- |
10056 |
// If we are lowering a libcall after legalization, split the return type. |
--- |
| 10057 |
SmallVector OldRetTys; |
0 |
10057 |
SmallVector OldRetTys; |
0 |
| 10058 |
SmallVector OldOffsets; |
0 |
10058 |
SmallVector OldOffsets; |
0 |
| 10059 |
RetTys.swap(OldRetTys); |
0 |
10059 |
RetTys.swap(OldRetTys); |
0 |
| 10060 |
Offsets.swap(OldOffsets); |
0 |
10060 |
Offsets.swap(OldOffsets); |
0 |
| 10061 |
|
--- |
10061 |
|
--- |
| 10062 |
for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) { |
0 |
10062 |
for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) { |
0 |
| 10063 |
EVT RetVT = OldRetTys[i]; |
0 |
10063 |
EVT RetVT = OldRetTys[i]; |
0 |
| 10064 |
uint64_t Offset = OldOffsets[i]; |
0 |
10064 |
uint64_t Offset = OldOffsets[i]; |
0 |
| 10065 |
MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); |
0 |
10065 |
MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); |
0 |
| 10066 |
unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT); |
0 |
10066 |
unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT); |
0 |
| 10067 |
unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8; |
0 |
10067 |
unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8; |
0 |
| 10068 |
RetTys.append(NumRegs, RegisterVT); |
0 |
10068 |
RetTys.append(NumRegs, RegisterVT); |
0 |
| 10069 |
for (unsigned j = 0; j != NumRegs; ++j) |
0 |
10069 |
for (unsigned j = 0; j != NumRegs; ++j) |
0 |
| 10070 |
Offsets.push_back(Offset + j * RegisterVTByteSZ); |
0 |
10070 |
Offsets.push_back(Offset + j * RegisterVTByteSZ); |
0 |
| 10071 |
} |
--- |
10071 |
} |
--- |
| 10072 |
} |
0 |
10072 |
} |
0 |
| 10073 |
|
--- |
10073 |
|
--- |
| 10074 |
SmallVector Outs; |
0 |
10074 |
SmallVector Outs; |
0 |
| 10075 |
GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL); |
0 |
10075 |
GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL); |
0 |
| 10076 |
|
--- |
10076 |
|
--- |
| 10077 |
bool CanLowerReturn = |
--- |
10077 |
bool CanLowerReturn = |
--- |
| 10078 |
this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(), |
0 |
10078 |
this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(), |
0 |
| 10079 |
CLI.IsVarArg, Outs, CLI.RetTy->getContext()); |
0 |
10079 |
CLI.IsVarArg, Outs, CLI.RetTy->getContext()); |
0 |
| 10080 |
|
--- |
10080 |
|
--- |
| 10081 |
SDValue DemoteStackSlot; |
0 |
10081 |
SDValue DemoteStackSlot; |
0 |
| 10082 |
int DemoteStackIdx = -100; |
0 |
10082 |
int DemoteStackIdx = -100; |
0 |
| 10083 |
if (!CanLowerReturn) { |
0 |
10083 |
if (!CanLowerReturn) { |
0 |
| 10084 |
// FIXME: equivalent assert? |
--- |
10084 |
// FIXME: equivalent assert? |
--- |
| 10085 |
// assert(!CS.hasInAllocaArgument() && |
--- |
10085 |
// assert(!CS.hasInAllocaArgument() && |
--- |
| 10086 |
// "sret demotion is incompatible with inalloca"); |
--- |
10086 |
// "sret demotion is incompatible with inalloca"); |
--- |
| 10087 |
uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy); |
0 |
10087 |
uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy); |
0 |
| 10088 |
Align Alignment = DL.getPrefTypeAlign(CLI.RetTy); |
0 |
10088 |
Align Alignment = DL.getPrefTypeAlign(CLI.RetTy); |
0 |
| 10089 |
MachineFunction &MF = CLI.DAG.getMachineFunction(); |
0 |
10089 |
MachineFunction &MF = CLI.DAG.getMachineFunction(); |
0 |
| 10090 |
DemoteStackIdx = |
--- |
10090 |
DemoteStackIdx = |
--- |
| 10091 |
MF.getFrameInfo().CreateStackObject(TySize, Alignment, false); |
0 |
10091 |
MF.getFrameInfo().CreateStackObject(TySize, Alignment, false); |
0 |
| 10092 |
Type *StackSlotPtrType = PointerType::get(CLI.RetTy, |
0 |
10092 |
Type *StackSlotPtrType = PointerType::get(CLI.RetTy, |
0 |
| 10093 |
DL.getAllocaAddrSpace()); |
--- |
10093 |
DL.getAllocaAddrSpace()); |
--- |
| 10094 |
|
--- |
10094 |
|
--- |
| 10095 |
DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL)); |
0 |
10095 |
DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL)); |
0 |
| 10096 |
ArgListEntry Entry; |
0 |
10096 |
ArgListEntry Entry; |
0 |
| 10097 |
Entry.Node = DemoteStackSlot; |
0 |
10097 |
Entry.Node = DemoteStackSlot; |
0 |
| 10098 |
Entry.Ty = StackSlotPtrType; |
0 |
10098 |
Entry.Ty = StackSlotPtrType; |
0 |
| 10099 |
Entry.IsSExt = false; |
0 |
10099 |
Entry.IsSExt = false; |
0 |
| 10100 |
Entry.IsZExt = false; |
0 |
10100 |
Entry.IsZExt = false; |
0 |
| 10101 |
Entry.IsInReg = false; |
0 |
10101 |
Entry.IsInReg = false; |
0 |
| 10102 |
Entry.IsSRet = true; |
0 |
10102 |
Entry.IsSRet = true; |
0 |
| 10103 |
Entry.IsNest = false; |
0 |
10103 |
Entry.IsNest = false; |
0 |
| 10104 |
Entry.IsByVal = false; |
0 |
10104 |
Entry.IsByVal = false; |
0 |
| 10105 |
Entry.IsByRef = false; |
0 |
10105 |
Entry.IsByRef = false; |
0 |
| 10106 |
Entry.IsReturned = false; |
0 |
10106 |
Entry.IsReturned = false; |
0 |
| 10107 |
Entry.IsSwiftSelf = false; |
0 |
10107 |
Entry.IsSwiftSelf = false; |
0 |
| 10108 |
Entry.IsSwiftAsync = false; |
0 |
10108 |
Entry.IsSwiftAsync = false; |
0 |
| 10109 |
Entry.IsSwiftError = false; |
0 |
10109 |
Entry.IsSwiftError = false; |
0 |
| 10110 |
Entry.IsCFGuardTarget = false; |
0 |
10110 |
Entry.IsCFGuardTarget = false; |
0 |
| 10111 |
Entry.Alignment = Alignment; |
0 |
10111 |
Entry.Alignment = Alignment; |
0 |
| 10112 |
CLI.getArgs().insert(CLI.getArgs().begin(), Entry); |
0 |
10112 |
CLI.getArgs().insert(CLI.getArgs().begin(), Entry); |
0 |
| 10113 |
CLI.NumFixedArgs += 1; |
0 |
10113 |
CLI.NumFixedArgs += 1; |
0 |
| 10114 |
CLI.getArgs()[0].IndirectType = CLI.RetTy; |
0 |
10114 |
CLI.getArgs()[0].IndirectType = CLI.RetTy; |
0 |
| 10115 |
CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext()); |
0 |
10115 |
CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext()); |
0 |
| 10116 |
|
--- |
10116 |
|
--- |
| 10117 |
// sret demotion isn't compatible with tail-calls, since the sret argument |
--- |
10117 |
// sret demotion isn't compatible with tail-calls, since the sret argument |
--- |
| 10118 |
// points into the callers stack frame. |
--- |
10118 |
// points into the callers stack frame. |
--- |
| 10119 |
CLI.IsTailCall = false; |
0 |
10119 |
CLI.IsTailCall = false; |
0 |
| 10120 |
} else { |
--- |
10120 |
} else { |
--- |
| 10121 |
bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( |
0 |
10121 |
bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( |
0 |
| 10122 |
CLI.RetTy, CLI.CallConv, CLI.IsVarArg, DL); |
0 |
10122 |
CLI.RetTy, CLI.CallConv, CLI.IsVarArg, DL); |
0 |
| 10123 |
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { |
0 |
10123 |
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { |
0 |
| 10124 |
ISD::ArgFlagsTy Flags; |
0 |
10124 |
ISD::ArgFlagsTy Flags; |
0 |
| 10125 |
if (NeedsRegBlock) { |
0 |
10125 |
if (NeedsRegBlock) { |
0 |
| 10126 |
Flags.setInConsecutiveRegs(); |
0 |
10126 |
Flags.setInConsecutiveRegs(); |
0 |
| 10127 |
if (I == RetTys.size() - 1) |
0 |
10127 |
if (I == RetTys.size() - 1) |
0 |
| 10128 |
Flags.setInConsecutiveRegsLast(); |
0 |
10128 |
Flags.setInConsecutiveRegsLast(); |
0 |
| 10129 |
} |
--- |
10129 |
} |
--- |
| 10130 |
EVT VT = RetTys[I]; |
0 |
10130 |
EVT VT = RetTys[I]; |
0 |
| 10131 |
MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), |
0 |
10131 |
MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), |
0 |
| 10132 |
CLI.CallConv, VT); |
--- |
10132 |
CLI.CallConv, VT); |
--- |
| 10133 |
unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), |
0 |
10133 |
unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), |
0 |
| 10134 |
CLI.CallConv, VT); |
--- |
10134 |
CLI.CallConv, VT); |
--- |
| 10135 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
10135 |
for (unsigned i = 0; i != NumRegs; ++i) { |
0 |
| 10136 |
ISD::InputArg MyFlags; |
0 |
10136 |
ISD::InputArg MyFlags; |
0 |
| 10137 |
MyFlags.Flags = Flags; |
0 |
10137 |
MyFlags.Flags = Flags; |
0 |
| 10138 |
MyFlags.VT = RegisterVT; |
0 |
10138 |
MyFlags.VT = RegisterVT; |
0 |
| 10139 |
MyFlags.ArgVT = VT; |
0 |
10139 |
MyFlags.ArgVT = VT; |
0 |
| 10140 |
MyFlags.Used = CLI.IsReturnValueUsed; |
0 |
10140 |
MyFlags.Used = CLI.IsReturnValueUsed; |
0 |
| 10141 |
if (CLI.RetTy->isPointerTy()) { |
0 |
10141 |
if (CLI.RetTy->isPointerTy()) { |
0 |
| 10142 |
MyFlags.Flags.setPointer(); |
0 |
10142 |
MyFlags.Flags.setPointer(); |
0 |
| 10143 |
MyFlags.Flags.setPointerAddrSpace( |
0 |
10143 |
MyFlags.Flags.setPointerAddrSpace( |
0 |
| 10144 |
cast(CLI.RetTy)->getAddressSpace()); |
--- |
10144 |
cast(CLI.RetTy)->getAddressSpace()); |
--- |
| 10145 |
} |
--- |
10145 |
} |
--- |
| 10146 |
if (CLI.RetSExt) |
0 |
10146 |
if (CLI.RetSExt) |
0 |
| 10147 |
MyFlags.Flags.setSExt(); |
0 |
10147 |
MyFlags.Flags.setSExt(); |
0 |
| 10148 |
if (CLI.RetZExt) |
0 |
10148 |
if (CLI.RetZExt) |
0 |
| 10149 |
MyFlags.Flags.setZExt(); |
0 |
10149 |
MyFlags.Flags.setZExt(); |
0 |
| 10150 |
if (CLI.IsInReg) |
0 |
10150 |
if (CLI.IsInReg) |
0 |
| 10151 |
MyFlags.Flags.setInReg(); |
0 |
10151 |
MyFlags.Flags.setInReg(); |
0 |
| 10152 |
CLI.Ins.push_back(MyFlags); |
0 |
10152 |
CLI.Ins.push_back(MyFlags); |
0 |
| 10153 |
} |
--- |
10153 |
} |
--- |
| 10154 |
} |
--- |
10154 |
} |
--- |
| 10155 |
} |
--- |
10155 |
} |
--- |
| 10156 |
|
--- |
10156 |
|
--- |
| 10157 |
// We push in swifterror return as the last element of CLI.Ins. |
--- |
10157 |
// We push in swifterror return as the last element of CLI.Ins. |
--- |
| 10158 |
ArgListTy &Args = CLI.getArgs(); |
0 |
10158 |
ArgListTy &Args = CLI.getArgs(); |
0 |
| 10159 |
if (supportSwiftError()) { |
0 |
10159 |
if (supportSwiftError()) { |
0 |
| 10160 |
for (const ArgListEntry &Arg : Args) { |
0 |
10160 |
for (const ArgListEntry &Arg : Args) { |
0 |
| 10161 |
if (Arg.IsSwiftError) { |
0 |
10161 |
if (Arg.IsSwiftError) { |
0 |
| 10162 |
ISD::InputArg MyFlags; |
0 |
10162 |
ISD::InputArg MyFlags; |
0 |
| 10163 |
MyFlags.VT = getPointerTy(DL); |
0 |
10163 |
MyFlags.VT = getPointerTy(DL); |
0 |
| 10164 |
MyFlags.ArgVT = EVT(getPointerTy(DL)); |
0 |
10164 |
MyFlags.ArgVT = EVT(getPointerTy(DL)); |
0 |
| 10165 |
MyFlags.Flags.setSwiftError(); |
0 |
10165 |
MyFlags.Flags.setSwiftError(); |
0 |
| 10166 |
CLI.Ins.push_back(MyFlags); |
0 |
10166 |
CLI.Ins.push_back(MyFlags); |
0 |
| 10167 |
} |
--- |
10167 |
} |
--- |
| 10168 |
} |
--- |
10168 |
} |
--- |
| 10169 |
} |
--- |
10169 |
} |
--- |
| 10170 |
|
--- |
10170 |
|
--- |
| 10171 |
// Handle all of the outgoing arguments. |
--- |
10171 |
// Handle all of the outgoing arguments. |
--- |
| 10172 |
CLI.Outs.clear(); |
0 |
10172 |
CLI.Outs.clear(); |
0 |
| 10173 |
CLI.OutVals.clear(); |
0 |
10173 |
CLI.OutVals.clear(); |
0 |
| 10174 |
for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
0 |
10174 |
for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
0 |
| 10175 |
SmallVector ValueVTs; |
0 |
10175 |
SmallVector ValueVTs; |
0 |
| 10176 |
ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs); |
0 |
10176 |
ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs); |
0 |
| 10177 |
// FIXME: Split arguments if CLI.IsPostTypeLegalization |
--- |
10177 |
// FIXME: Split arguments if CLI.IsPostTypeLegalization |
--- |
| 10178 |
Type *FinalType = Args[i].Ty; |
0 |
10178 |
Type *FinalType = Args[i].Ty; |
0 |
| 10179 |
if (Args[i].IsByVal) |
0 |
10179 |
if (Args[i].IsByVal) |
0 |
| 10180 |
FinalType = Args[i].IndirectType; |
0 |
10180 |
FinalType = Args[i].IndirectType; |
0 |
| 10181 |
bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( |
0 |
10181 |
bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( |
0 |
| 10182 |
FinalType, CLI.CallConv, CLI.IsVarArg, DL); |
0 |
10182 |
FinalType, CLI.CallConv, CLI.IsVarArg, DL); |
0 |
| 10183 |
for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; |
0 |
10183 |
for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; |
0 |
| 10184 |
++Value) { |
--- |
10184 |
++Value) { |
--- |
| 10185 |
EVT VT = ValueVTs[Value]; |
0 |
10185 |
EVT VT = ValueVTs[Value]; |
0 |
| 10186 |
Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); |
0 |
10186 |
Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); |
0 |
| 10187 |
SDValue Op = SDValue(Args[i].Node.getNode(), |
0 |
10187 |
SDValue Op = SDValue(Args[i].Node.getNode(), |
0 |
| 10188 |
Args[i].Node.getResNo() + Value); |
0 |
10188 |
Args[i].Node.getResNo() + Value); |
0 |
| 10189 |
ISD::ArgFlagsTy Flags; |
0 |
10189 |
ISD::ArgFlagsTy Flags; |
0 |
| 10190 |
|
--- |
10190 |
|
--- |
| 10191 |
// Certain targets (such as MIPS), may have a different ABI alignment |
--- |
10191 |
// Certain targets (such as MIPS), may have a different ABI alignment |
--- |
| 10192 |
// for a type depending on the context. Give the target a chance to |
--- |
10192 |
// for a type depending on the context. Give the target a chance to |
--- |
| 10193 |
// specify the alignment it wants. |
--- |
10193 |
// specify the alignment it wants. |
--- |
| 10194 |
const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL)); |
0 |
10194 |
const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL)); |
0 |
| 10195 |
Flags.setOrigAlign(OriginalAlignment); |
0 |
10195 |
Flags.setOrigAlign(OriginalAlignment); |
0 |
| 10196 |
|
--- |
10196 |
|
--- |
| 10197 |
if (Args[i].Ty->isPointerTy()) { |
0 |
10197 |
if (Args[i].Ty->isPointerTy()) { |
0 |
| 10198 |
Flags.setPointer(); |
0 |
10198 |
Flags.setPointer(); |
0 |
| 10199 |
Flags.setPointerAddrSpace( |
0 |
10199 |
Flags.setPointerAddrSpace( |
0 |
| 10200 |
cast(Args[i].Ty)->getAddressSpace()); |
0 |
10200 |
cast(Args[i].Ty)->getAddressSpace()); |
0 |
| 10201 |
} |
--- |
10201 |
} |
--- |
| 10202 |
if (Args[i].IsZExt) |
0 |
10202 |
if (Args[i].IsZExt) |
0 |
| 10203 |
Flags.setZExt(); |
0 |
10203 |
Flags.setZExt(); |
0 |
| 10204 |
if (Args[i].IsSExt) |
0 |
10204 |
if (Args[i].IsSExt) |
0 |
| 10205 |
Flags.setSExt(); |
0 |
10205 |
Flags.setSExt(); |
0 |
| 10206 |
if (Args[i].IsInReg) { |
0 |
10206 |
if (Args[i].IsInReg) { |
0 |
| 10207 |
// If we are using vectorcall calling convention, a structure that is |
--- |
10207 |
// If we are using vectorcall calling convention, a structure that is |
--- |
| 10208 |
// passed InReg - is surely an HVA |
--- |
10208 |
// passed InReg - is surely an HVA |
--- |
| 10209 |
if (CLI.CallConv == CallingConv::X86_VectorCall && |
0 |
10209 |
if (CLI.CallConv == CallingConv::X86_VectorCall && |
0 |
| 10210 |
isa(FinalType)) { |
0 |
10210 |
isa(FinalType)) { |
0 |
| 10211 |
// The first value of a structure is marked |
--- |
10211 |
// The first value of a structure is marked |
--- |
| 10212 |
if (0 == Value) |
0 |
10212 |
if (0 == Value) |
0 |
| 10213 |
Flags.setHvaStart(); |
0 |
10213 |
Flags.setHvaStart(); |
0 |
| 10214 |
Flags.setHva(); |
0 |
10214 |
Flags.setHva(); |
0 |
| 10215 |
} |
--- |
10215 |
} |
--- |
| 10216 |
// Set InReg Flag |
--- |
10216 |
// Set InReg Flag |
--- |
| 10217 |
Flags.setInReg(); |
0 |
10217 |
Flags.setInReg(); |
0 |
| 10218 |
} |
--- |
10218 |
} |
--- |
| 10219 |
if (Args[i].IsSRet) |
0 |
10219 |
if (Args[i].IsSRet) |
0 |
| 10220 |
Flags.setSRet(); |
0 |
10220 |
Flags.setSRet(); |
0 |
| 10221 |
if (Args[i].IsSwiftSelf) |
0 |
10221 |
if (Args[i].IsSwiftSelf) |
0 |
| 10222 |
Flags.setSwiftSelf(); |
0 |
10222 |
Flags.setSwiftSelf(); |
0 |
| 10223 |
if (Args[i].IsSwiftAsync) |
0 |
10223 |
if (Args[i].IsSwiftAsync) |
0 |
| 10224 |
Flags.setSwiftAsync(); |
0 |
10224 |
Flags.setSwiftAsync(); |
0 |
| 10225 |
if (Args[i].IsSwiftError) |
0 |
10225 |
if (Args[i].IsSwiftError) |
0 |
| 10226 |
Flags.setSwiftError(); |
0 |
10226 |
Flags.setSwiftError(); |
0 |
| 10227 |
if (Args[i].IsCFGuardTarget) |
0 |
10227 |
if (Args[i].IsCFGuardTarget) |
0 |
| 10228 |
Flags.setCFGuardTarget(); |
0 |
10228 |
Flags.setCFGuardTarget(); |
0 |
| 10229 |
if (Args[i].IsByVal) |
0 |
10229 |
if (Args[i].IsByVal) |
0 |
| 10230 |
Flags.setByVal(); |
0 |
10230 |
Flags.setByVal(); |
0 |
| 10231 |
if (Args[i].IsByRef) |
0 |
10231 |
if (Args[i].IsByRef) |
0 |
| 10232 |
Flags.setByRef(); |
0 |
10232 |
Flags.setByRef(); |
0 |
| 10233 |
if (Args[i].IsPreallocated) { |
0 |
10233 |
if (Args[i].IsPreallocated) { |
0 |
| 10234 |
Flags.setPreallocated(); |
0 |
10234 |
Flags.setPreallocated(); |
0 |
| 10235 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
10235 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
| 10236 |
// preallocated. This way we can know how many bytes we should've |
--- |
10236 |
// preallocated. This way we can know how many bytes we should've |
--- |
| 10237 |
// allocated and how many bytes a callee cleanup function will pop. If |
--- |
10237 |
// allocated and how many bytes a callee cleanup function will pop. If |
--- |
| 10238 |
// we port preallocated to more targets, we'll have to add custom |
--- |
10238 |
// we port preallocated to more targets, we'll have to add custom |
--- |
| 10239 |
// preallocated handling in the various CC lowering callbacks. |
--- |
10239 |
// preallocated handling in the various CC lowering callbacks. |
--- |
| 10240 |
Flags.setByVal(); |
0 |
10240 |
Flags.setByVal(); |
0 |
| 10241 |
} |
--- |
10241 |
} |
--- |
| 10242 |
if (Args[i].IsInAlloca) { |
0 |
10242 |
if (Args[i].IsInAlloca) { |
0 |
| 10243 |
Flags.setInAlloca(); |
0 |
10243 |
Flags.setInAlloca(); |
0 |
| 10244 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
10244 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
| 10245 |
// inalloca. This way we can know how many bytes we should've allocated |
--- |
10245 |
// inalloca. This way we can know how many bytes we should've allocated |
--- |
| 10246 |
// and how many bytes a callee cleanup function will pop. If we port |
--- |
10246 |
// and how many bytes a callee cleanup function will pop. If we port |
--- |
| 10247 |
// inalloca to more targets, we'll have to add custom inalloca handling |
--- |
10247 |
// inalloca to more targets, we'll have to add custom inalloca handling |
--- |
| 10248 |
// in the various CC lowering callbacks. |
--- |
10248 |
// in the various CC lowering callbacks. |
--- |
| 10249 |
Flags.setByVal(); |
0 |
10249 |
Flags.setByVal(); |
0 |
| 10250 |
} |
--- |
10250 |
} |
--- |
| 10251 |
Align MemAlign; |
0 |
10251 |
Align MemAlign; |
0 |
| 10252 |
if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) { |
0 |
10252 |
if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) { |
0 |
| 10253 |
unsigned FrameSize = DL.getTypeAllocSize(Args[i].IndirectType); |
0 |
10253 |
unsigned FrameSize = DL.getTypeAllocSize(Args[i].IndirectType); |
0 |
| 10254 |
Flags.setByValSize(FrameSize); |
0 |
10254 |
Flags.setByValSize(FrameSize); |
0 |
| 10255 |
|
--- |
10255 |
|
--- |
| 10256 |
// info is not there but there are cases it cannot get right. |
--- |
10256 |
// info is not there but there are cases it cannot get right. |
--- |
| 10257 |
if (auto MA = Args[i].Alignment) |
0 |
10257 |
if (auto MA = Args[i].Alignment) |
0 |
| 10258 |
MemAlign = *MA; |
0 |
10258 |
MemAlign = *MA; |
0 |
| 10259 |
else |
--- |
10259 |
else |
--- |
| 10260 |
MemAlign = Align(getByValTypeAlignment(Args[i].IndirectType, DL)); |
0 |
10260 |
MemAlign = Align(getByValTypeAlignment(Args[i].IndirectType, DL)); |
0 |
| 10261 |
} else if (auto MA = Args[i].Alignment) { |
0 |
10261 |
} else if (auto MA = Args[i].Alignment) { |
0 |
| 10262 |
MemAlign = *MA; |
0 |
10262 |
MemAlign = *MA; |
0 |
| 10263 |
} else { |
--- |
10263 |
} else { |
--- |
| 10264 |
MemAlign = OriginalAlignment; |
0 |
10264 |
MemAlign = OriginalAlignment; |
0 |
| 10265 |
} |
--- |
10265 |
} |
--- |
| 10266 |
Flags.setMemAlign(MemAlign); |
0 |
10266 |
Flags.setMemAlign(MemAlign); |
0 |
| 10267 |
if (Args[i].IsNest) |
0 |
10267 |
if (Args[i].IsNest) |
0 |
| 10268 |
Flags.setNest(); |
0 |
10268 |
Flags.setNest(); |
0 |
| 10269 |
if (NeedsRegBlock) |
0 |
10269 |
if (NeedsRegBlock) |
0 |
| 10270 |
Flags.setInConsecutiveRegs(); |
0 |
10270 |
Flags.setInConsecutiveRegs(); |
0 |
| 10271 |
|
--- |
10271 |
|
--- |
| 10272 |
MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), |
0 |
10272 |
MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), |
0 |
| 10273 |
CLI.CallConv, VT); |
--- |
10273 |
CLI.CallConv, VT); |
--- |
| 10274 |
unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(), |
0 |
10274 |
unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(), |
0 |
| 10275 |
CLI.CallConv, VT); |
--- |
10275 |
CLI.CallConv, VT); |
--- |
| 10276 |
SmallVector Parts(NumParts); |
0 |
10276 |
SmallVector Parts(NumParts); |
0 |
| 10277 |
ISD::NodeType ExtendKind = ISD::ANY_EXTEND; |
0 |
10277 |
ISD::NodeType ExtendKind = ISD::ANY_EXTEND; |
0 |
| 10278 |
|
--- |
10278 |
|
--- |
| 10279 |
if (Args[i].IsSExt) |
0 |
10279 |
if (Args[i].IsSExt) |
0 |
| 10280 |
ExtendKind = ISD::SIGN_EXTEND; |
0 |
10280 |
ExtendKind = ISD::SIGN_EXTEND; |
0 |
| 10281 |
else if (Args[i].IsZExt) |
0 |
10281 |
else if (Args[i].IsZExt) |
0 |
| 10282 |
ExtendKind = ISD::ZERO_EXTEND; |
0 |
10282 |
ExtendKind = ISD::ZERO_EXTEND; |
0 |
| 10283 |
|
--- |
10283 |
|
--- |
| 10284 |
// Conservatively only handle 'returned' on non-vectors that can be lowered, |
--- |
10284 |
// Conservatively only handle 'returned' on non-vectors that can be lowered, |
--- |
| 10285 |
// for now. |
--- |
10285 |
// for now. |
--- |
| 10286 |
if (Args[i].IsReturned && !Op.getValueType().isVector() && |
0 |
10286 |
if (Args[i].IsReturned && !Op.getValueType().isVector() && |
0 |
| 10287 |
CanLowerReturn) { |
--- |
10287 |
CanLowerReturn) { |
--- |
| 10288 |
assert((CLI.RetTy == Args[i].Ty || |
0 |
10288 |
assert((CLI.RetTy == Args[i].Ty || |
0 |
| 10289 |
(CLI.RetTy->isPointerTy() && Args[i].Ty->isPointerTy() && |
--- |
10289 |
(CLI.RetTy->isPointerTy() && Args[i].Ty->isPointerTy() && |
--- |
| 10290 |
CLI.RetTy->getPointerAddressSpace() == |
--- |
10290 |
CLI.RetTy->getPointerAddressSpace() == |
--- |
| 10291 |
Args[i].Ty->getPointerAddressSpace())) && |
--- |
10291 |
Args[i].Ty->getPointerAddressSpace())) && |
--- |
| 10292 |
RetTys.size() == NumValues && "unexpected use of 'returned'"); |
--- |
10292 |
RetTys.size() == NumValues && "unexpected use of 'returned'"); |
--- |
| 10293 |
// Before passing 'returned' to the target lowering code, ensure that |
--- |
10293 |
// Before passing 'returned' to the target lowering code, ensure that |
--- |
| 10294 |
// either the register MVT and the actual EVT are the same size or that |
--- |
10294 |
// either the register MVT and the actual EVT are the same size or that |
--- |
| 10295 |
// the return value and argument are extended in the same way; in these |
--- |
10295 |
// the return value and argument are extended in the same way; in these |
--- |
| 10296 |
// cases it's safe to pass the argument register value unchanged as the |
--- |
10296 |
// cases it's safe to pass the argument register value unchanged as the |
--- |
| 10297 |
// return register value (although it's at the target's option whether |
--- |
10297 |
// return register value (although it's at the target's option whether |
--- |
| 10298 |
// to do so) |
--- |
10298 |
// to do so) |
--- |
| 10299 |
// TODO: allow code generation to take advantage of partially preserved |
--- |
10299 |
// TODO: allow code generation to take advantage of partially preserved |
--- |
| 10300 |
// registers rather than clobbering the entire register when the |
--- |
10300 |
// registers rather than clobbering the entire register when the |
--- |
| 10301 |
// parameter extension method is not compatible with the return |
--- |
10301 |
// parameter extension method is not compatible with the return |
--- |
| 10302 |
// extension method |
--- |
10302 |
// extension method |
--- |
| 10303 |
if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || |
0 |
10303 |
if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || |
0 |
| 10304 |
(ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt && |
0 |
10304 |
(ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt && |
0 |
| 10305 |
CLI.RetZExt == Args[i].IsZExt)) |
0 |
10305 |
CLI.RetZExt == Args[i].IsZExt)) |
0 |
| 10306 |
Flags.setReturned(); |
0 |
10306 |
Flags.setReturned(); |
0 |
| 10307 |
} |
--- |
10307 |
} |
--- |
| 10308 |
|
--- |
10308 |
|
--- |
| 10309 |
getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, CLI.CB, |
0 |
10309 |
getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, CLI.CB, |
0 |
| 10310 |
CLI.CallConv, ExtendKind); |
0 |
10310 |
CLI.CallConv, ExtendKind); |
0 |
| 10311 |
|
--- |
10311 |
|
--- |
| 10312 |
for (unsigned j = 0; j != NumParts; ++j) { |
0 |
10312 |
for (unsigned j = 0; j != NumParts; ++j) { |
0 |
| 10313 |
// if it isn't first piece, alignment must be 1 |
--- |
10313 |
// if it isn't first piece, alignment must be 1 |
--- |
| 10314 |
// For scalable vectors the scalable part is currently handled |
--- |
10314 |
// For scalable vectors the scalable part is currently handled |
--- |
| 10315 |
// by individual targets, so we just use the known minimum size here. |
--- |
10315 |
// by individual targets, so we just use the known minimum size here. |
--- |
| 10316 |
ISD::OutputArg MyFlags( |
--- |
10316 |
ISD::OutputArg MyFlags( |
--- |
| 10317 |
Flags, Parts[j].getValueType().getSimpleVT(), VT, |
0 |
10317 |
Flags, Parts[j].getValueType().getSimpleVT(), VT, |
0 |
| 10318 |
i < CLI.NumFixedArgs, i, |
0 |
10318 |
i < CLI.NumFixedArgs, i, |
0 |
| 10319 |
j * Parts[j].getValueType().getStoreSize().getKnownMinValue()); |
0 |
10319 |
j * Parts[j].getValueType().getStoreSize().getKnownMinValue()); |
0 |
| 10320 |
if (NumParts > 1 && j == 0) |
0 |
10320 |
if (NumParts > 1 && j == 0) |
0 |
| 10321 |
MyFlags.Flags.setSplit(); |
0 |
10321 |
MyFlags.Flags.setSplit(); |
0 |
| 10322 |
else if (j != 0) { |
0 |
10322 |
else if (j != 0) { |
0 |
| 10323 |
MyFlags.Flags.setOrigAlign(Align(1)); |
0 |
10323 |
MyFlags.Flags.setOrigAlign(Align(1)); |
0 |
| 10324 |
if (j == NumParts - 1) |
0 |
10324 |
if (j == NumParts - 1) |
0 |
| 10325 |
MyFlags.Flags.setSplitEnd(); |
0 |
10325 |
MyFlags.Flags.setSplitEnd(); |
0 |
| 10326 |
} |
--- |
10326 |
} |
--- |
| 10327 |
|
--- |
10327 |
|
--- |
| 10328 |
CLI.Outs.push_back(MyFlags); |
0 |
10328 |
CLI.Outs.push_back(MyFlags); |
0 |
| 10329 |
CLI.OutVals.push_back(Parts[j]); |
0 |
10329 |
CLI.OutVals.push_back(Parts[j]); |
0 |
| 10330 |
} |
--- |
10330 |
} |
--- |
| 10331 |
|
--- |
10331 |
|
--- |
| 10332 |
if (NeedsRegBlock && Value == NumValues - 1) |
0 |
10332 |
if (NeedsRegBlock && Value == NumValues - 1) |
0 |
| 10333 |
CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast(); |
0 |
10333 |
CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast(); |
0 |
| 10334 |
} |
0 |
10334 |
} |
0 |
| 10335 |
} |
0 |
10335 |
} |
0 |
| 10336 |
|
--- |
10336 |
|
--- |
| 10337 |
SmallVector InVals; |
0 |
10337 |
SmallVector InVals; |
0 |
| 10338 |
CLI.Chain = LowerCall(CLI, InVals); |
0 |
10338 |
CLI.Chain = LowerCall(CLI, InVals); |
0 |
| 10339 |
|
--- |
10339 |
|
--- |
| 10340 |
// Update CLI.InVals to use outside of this function. |
--- |
10340 |
// Update CLI.InVals to use outside of this function. |
--- |
| 10341 |
CLI.InVals = InVals; |
0 |
10341 |
CLI.InVals = InVals; |
0 |
| 10342 |
|
--- |
10342 |
|
--- |
| 10343 |
// Verify that the target's LowerCall behaved as expected. |
--- |
10343 |
// Verify that the target's LowerCall behaved as expected. |
--- |
| 10344 |
assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && |
0 |
10344 |
assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && |
0 |
| 10345 |
"LowerCall didn't return a valid chain!"); |
--- |
10345 |
"LowerCall didn't return a valid chain!"); |
--- |
| 10346 |
assert((!CLI.IsTailCall || InVals.empty()) && |
0 |
10346 |
assert((!CLI.IsTailCall || InVals.empty()) && |
0 |
| 10347 |
"LowerCall emitted a return value for a tail call!"); |
--- |
10347 |
"LowerCall emitted a return value for a tail call!"); |
--- |
| 10348 |
assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && |
0 |
10348 |
assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && |
0 |
| 10349 |
"LowerCall didn't emit the correct number of values!"); |
--- |
10349 |
"LowerCall didn't emit the correct number of values!"); |
--- |
| 10350 |
|
--- |
10350 |
|
--- |
| 10351 |
// For a tail call, the return value is merely live-out and there aren't |
--- |
10351 |
// For a tail call, the return value is merely live-out and there aren't |
--- |
| 10352 |
// any nodes in the DAG representing it. Return a special value to |
--- |
10352 |
// any nodes in the DAG representing it. Return a special value to |
--- |
| 10353 |
// indicate that a tail call has been emitted and no more Instructions |
--- |
10353 |
// indicate that a tail call has been emitted and no more Instructions |
--- |
| 10354 |
// should be processed in the current block. |
--- |
10354 |
// should be processed in the current block. |
--- |
| 10355 |
if (CLI.IsTailCall) { |
0 |
10355 |
if (CLI.IsTailCall) { |
0 |
| 10356 |
CLI.DAG.setRoot(CLI.Chain); |
0 |
10356 |
CLI.DAG.setRoot(CLI.Chain); |
0 |
| 10357 |
return std::make_pair(SDValue(), SDValue()); |
0 |
10357 |
return std::make_pair(SDValue(), SDValue()); |
0 |
| 10358 |
} |
--- |
10358 |
} |
--- |
| 10359 |
|
--- |
10359 |
|
--- |
| 10360 |
#ifndef NDEBUG |
--- |
10360 |
#ifndef NDEBUG |
--- |
| 10361 |
for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { |
0 |
10361 |
for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { |
0 |
| 10362 |
assert(InVals[i].getNode() && "LowerCall emitted a null value!"); |
0 |
10362 |
assert(InVals[i].getNode() && "LowerCall emitted a null value!"); |
0 |
| 10363 |
assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && |
0 |
10363 |
assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && |
0 |
| 10364 |
"LowerCall emitted a value with the wrong type!"); |
--- |
10364 |
"LowerCall emitted a value with the wrong type!"); |
--- |
| 10365 |
} |
--- |
10365 |
} |
--- |
| 10366 |
#endif |
--- |
10366 |
#endif |
--- |
| 10367 |
|
--- |
10367 |
|
--- |
| 10368 |
SmallVector ReturnValues; |
0 |
10368 |
SmallVector ReturnValues; |
0 |
| 10369 |
if (!CanLowerReturn) { |
0 |
10369 |
if (!CanLowerReturn) { |
0 |
| 10370 |
// The instruction result is the result of loading from the |
--- |
10370 |
// The instruction result is the result of loading from the |
--- |
| 10371 |
// hidden sret parameter. |
--- |
10371 |
// hidden sret parameter. |
--- |
| 10372 |
SmallVector PVTs; |
0 |
10372 |
SmallVector PVTs; |
0 |
| 10373 |
Type *PtrRetTy = |
--- |
10373 |
Type *PtrRetTy = |
--- |
| 10374 |
PointerType::get(OrigRetTy->getContext(), DL.getAllocaAddrSpace()); |
0 |
10374 |
PointerType::get(OrigRetTy->getContext(), DL.getAllocaAddrSpace()); |
0 |
| 10375 |
|
--- |
10375 |
|
--- |
| 10376 |
ComputeValueVTs(*this, DL, PtrRetTy, PVTs); |
0 |
10376 |
ComputeValueVTs(*this, DL, PtrRetTy, PVTs); |
0 |
| 10377 |
assert(PVTs.size() == 1 && "Pointers should fit in one register"); |
0 |
10377 |
assert(PVTs.size() == 1 && "Pointers should fit in one register"); |
0 |
| 10378 |
EVT PtrVT = PVTs[0]; |
0 |
10378 |
EVT PtrVT = PVTs[0]; |
0 |
| 10379 |
|
--- |
10379 |
|
--- |
| 10380 |
unsigned NumValues = RetTys.size(); |
0 |
10380 |
unsigned NumValues = RetTys.size(); |
0 |
| 10381 |
ReturnValues.resize(NumValues); |
0 |
10381 |
ReturnValues.resize(NumValues); |
0 |
| 10382 |
SmallVector Chains(NumValues); |
0 |
10382 |
SmallVector Chains(NumValues); |
0 |
| 10383 |
|
--- |
10383 |
|
--- |
| 10384 |
// An aggregate return value cannot wrap around the address space, so |
--- |
10384 |
// An aggregate return value cannot wrap around the address space, so |
--- |
| 10385 |
// offsets to its parts don't wrap either. |
--- |
10385 |
// offsets to its parts don't wrap either. |
--- |
| 10386 |
SDNodeFlags Flags; |
0 |
10386 |
SDNodeFlags Flags; |
0 |
| 10387 |
Flags.setNoUnsignedWrap(true); |
0 |
10387 |
Flags.setNoUnsignedWrap(true); |
0 |
| 10388 |
|
--- |
10388 |
|
--- |
| 10389 |
MachineFunction &MF = CLI.DAG.getMachineFunction(); |
0 |
10389 |
MachineFunction &MF = CLI.DAG.getMachineFunction(); |
0 |
| 10390 |
Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx); |
0 |
10390 |
Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx); |
0 |
| 10391 |
for (unsigned i = 0; i < NumValues; ++i) { |
0 |
10391 |
for (unsigned i = 0; i < NumValues; ++i) { |
0 |
| 10392 |
SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot, |
0 |
10392 |
SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot, |
0 |
| 10393 |
CLI.DAG.getConstant(Offsets[i], CLI.DL, |
0 |
10393 |
CLI.DAG.getConstant(Offsets[i], CLI.DL, |
0 |
| 10394 |
PtrVT), Flags); |
--- |
10394 |
PtrVT), Flags); |
--- |
| 10395 |
SDValue L = CLI.DAG.getLoad( |
0 |
10395 |
SDValue L = CLI.DAG.getLoad( |
0 |
| 10396 |
RetTys[i], CLI.DL, CLI.Chain, Add, |
0 |
10396 |
RetTys[i], CLI.DL, CLI.Chain, Add, |
0 |
| 10397 |
MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(), |
0 |
10397 |
MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(), |
0 |
| 10398 |
DemoteStackIdx, Offsets[i]), |
0 |
10398 |
DemoteStackIdx, Offsets[i]), |
0 |
| 10399 |
HiddenSRetAlign); |
--- |
10399 |
HiddenSRetAlign); |
--- |
| 10400 |
ReturnValues[i] = L; |
0 |
10400 |
ReturnValues[i] = L; |
0 |
| 10401 |
Chains[i] = L.getValue(1); |
0 |
10401 |
Chains[i] = L.getValue(1); |
0 |
| 10402 |
} |
--- |
10402 |
} |
--- |
| 10403 |
|
--- |
10403 |
|
--- |
| 10404 |
CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains); |
0 |
10404 |
CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains); |
0 |
| 10405 |
} else { |
0 |
10405 |
} else { |
0 |
| 10406 |
// Collect the legal value parts into potentially illegal values |
--- |
10406 |
// Collect the legal value parts into potentially illegal values |
--- |
| 10407 |
// that correspond to the original function's return values. |
--- |
10407 |
// that correspond to the original function's return values. |
--- |
| 10408 |
std::optional AssertOp; |
0 |
10408 |
std::optional AssertOp; |
0 |
| 10409 |
if (CLI.RetSExt) |
0 |
10409 |
if (CLI.RetSExt) |
0 |
| 10410 |
AssertOp = ISD::AssertSext; |
0 |
10410 |
AssertOp = ISD::AssertSext; |
0 |
| 10411 |
else if (CLI.RetZExt) |
0 |
10411 |
else if (CLI.RetZExt) |
0 |
| 10412 |
AssertOp = ISD::AssertZext; |
0 |
10412 |
AssertOp = ISD::AssertZext; |
0 |
| 10413 |
unsigned CurReg = 0; |
0 |
10413 |
unsigned CurReg = 0; |
0 |
| 10414 |
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { |
0 |
10414 |
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { |
0 |
| 10415 |
EVT VT = RetTys[I]; |
0 |
10415 |
EVT VT = RetTys[I]; |
0 |
| 10416 |
MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), |
0 |
10416 |
MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), |
0 |
| 10417 |
CLI.CallConv, VT); |
--- |
10417 |
CLI.CallConv, VT); |
--- |
| 10418 |
unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), |
0 |
10418 |
unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), |
0 |
| 10419 |
CLI.CallConv, VT); |
--- |
10419 |
CLI.CallConv, VT); |
--- |
| 10420 |
|
--- |
10420 |
|
--- |
| 10421 |
ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], |
0 |
10421 |
ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], |
0 |
| 10422 |
NumRegs, RegisterVT, VT, nullptr, |
--- |
10422 |
NumRegs, RegisterVT, VT, nullptr, |
--- |
| 10423 |
CLI.CallConv, AssertOp)); |
0 |
10423 |
CLI.CallConv, AssertOp)); |
0 |
| 10424 |
CurReg += NumRegs; |
0 |
10424 |
CurReg += NumRegs; |
0 |
| 10425 |
} |
--- |
10425 |
} |
--- |
| 10426 |
|
--- |
10426 |
|
--- |
| 10427 |
// For a function returning void, there is no return value. We can't create |
--- |
10427 |
// For a function returning void, there is no return value. We can't create |
--- |
| 10428 |
// such a node, so we just return a null return value in that case. In |
--- |
10428 |
// such a node, so we just return a null return value in that case. In |
--- |
| 10429 |
// that case, nothing will actually look at the value. |
--- |
10429 |
// that case, nothing will actually look at the value. |
--- |
| 10430 |
if (ReturnValues.empty()) |
0 |
10430 |
if (ReturnValues.empty()) |
0 |
| 10431 |
return std::make_pair(SDValue(), CLI.Chain); |
0 |
10431 |
return std::make_pair(SDValue(), CLI.Chain); |
0 |
| 10432 |
} |
--- |
10432 |
} |
--- |
| 10433 |
|
--- |
10433 |
|
--- |
| 10434 |
SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, |
0 |
10434 |
SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, |
0 |
| 10435 |
CLI.DAG.getVTList(RetTys), ReturnValues); |
0 |
10435 |
CLI.DAG.getVTList(RetTys), ReturnValues); |
0 |
| 10436 |
return std::make_pair(Res, CLI.Chain); |
0 |
10436 |
return std::make_pair(Res, CLI.Chain); |
0 |
| 10437 |
} |
0 |
10437 |
} |
0 |
| 10438 |
|
--- |
10438 |
|
--- |
| 10439 |
/// Places new result values for the node in Results (their number |
--- |
10439 |
/// Places new result values for the node in Results (their number |
--- |
| 10440 |
/// and types must exactly match those of the original return values of |
--- |
10440 |
/// and types must exactly match those of the original return values of |
--- |
| 10441 |
/// the node), or leaves Results empty, which indicates that the node is not |
--- |
10441 |
/// the node), or leaves Results empty, which indicates that the node is not |
--- |
| 10442 |
/// to be custom lowered after all. |
--- |
10442 |
/// to be custom lowered after all. |
--- |
| 10443 |
void TargetLowering::LowerOperationWrapper(SDNode *N, |
0 |
10443 |
void TargetLowering::LowerOperationWrapper(SDNode *N, |
0 |
| 10444 |
SmallVectorImpl &Results, |
--- |
10444 |
SmallVectorImpl &Results, |
--- |
| 10445 |
SelectionDAG &DAG) const { |
--- |
10445 |
SelectionDAG &DAG) const { |
--- |
| 10446 |
SDValue Res = LowerOperation(SDValue(N, 0), DAG); |
0 |
10446 |
SDValue Res = LowerOperation(SDValue(N, 0), DAG); |
0 |
| 10447 |
|
--- |
10447 |
|
--- |
| 10448 |
if (!Res.getNode()) |
0 |
10448 |
if (!Res.getNode()) |
0 |
| 10449 |
return; |
0 |
10449 |
return; |
0 |
| 10450 |
|
--- |
10450 |
|
--- |
| 10451 |
// If the original node has one result, take the return value from |
--- |
10451 |
// If the original node has one result, take the return value from |
--- |
| 10452 |
// LowerOperation as is. It might not be result number 0. |
--- |
10452 |
// LowerOperation as is. It might not be result number 0. |
--- |
| 10453 |
if (N->getNumValues() == 1) { |
0 |
10453 |
if (N->getNumValues() == 1) { |
0 |
| 10454 |
Results.push_back(Res); |
0 |
10454 |
Results.push_back(Res); |
0 |
| 10455 |
return; |
0 |
10455 |
return; |
0 |
| 10456 |
} |
--- |
10456 |
} |
--- |
| 10457 |
|
--- |
10457 |
|
--- |
| 10458 |
// If the original node has multiple results, then the return node should |
--- |
10458 |
// If the original node has multiple results, then the return node should |
--- |
| 10459 |
// have the same number of results. |
--- |
10459 |
// have the same number of results. |
--- |
| 10460 |
assert((N->getNumValues() == Res->getNumValues()) && |
0 |
10460 |
assert((N->getNumValues() == Res->getNumValues()) && |
0 |
| 10461 |
"Lowering returned the wrong number of results!"); |
--- |
10461 |
"Lowering returned the wrong number of results!"); |
--- |
| 10462 |
|
--- |
10462 |
|
--- |
| 10463 |
// Places new result values base on N result number. |
--- |
10463 |
// Places new result values base on N result number. |
--- |
| 10464 |
for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) |
0 |
10464 |
for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) |
0 |
| 10465 |
Results.push_back(Res.getValue(I)); |
0 |
10465 |
Results.push_back(Res.getValue(I)); |
0 |
| 10466 |
} |
--- |
10466 |
} |
--- |
| 10467 |
|
--- |
10467 |
|
--- |
| 10468 |
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { |
0 |
10468 |
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { |
0 |
| 10469 |
llvm_unreachable("LowerOperation not implemented for this target!"); |
0 |
10469 |
llvm_unreachable("LowerOperation not implemented for this target!"); |
0 |
| 10470 |
} |
--- |
10470 |
} |
--- |
| 10471 |
|
--- |
10471 |
|
--- |
| 10472 |
void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, |
0 |
10472 |
void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, |
0 |
| 10473 |
unsigned Reg, |
--- |
10473 |
unsigned Reg, |
--- |
| 10474 |
ISD::NodeType ExtendType) { |
--- |
10474 |
ISD::NodeType ExtendType) { |
--- |
| 10475 |
SDValue Op = getNonRegisterValue(V); |
0 |
10475 |
SDValue Op = getNonRegisterValue(V); |
0 |
| 10476 |
assert((Op.getOpcode() != ISD::CopyFromReg || |
0 |
10476 |
assert((Op.getOpcode() != ISD::CopyFromReg || |
0 |
| 10477 |
cast(Op.getOperand(1))->getReg() != Reg) && |
--- |
10477 |
cast(Op.getOperand(1))->getReg() != Reg) && |
--- |
| 10478 |
"Copy from a reg to the same reg!"); |
--- |
10478 |
"Copy from a reg to the same reg!"); |
--- |
| 10479 |
assert(!Register::isPhysicalRegister(Reg) && "Is a physreg"); |
0 |
10479 |
assert(!Register::isPhysicalRegister(Reg) && "Is a physreg"); |
0 |
| 10480 |
|
--- |
10480 |
|
--- |
| 10481 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
10481 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 10482 |
// If this is an InlineAsm we have to match the registers required, not the |
--- |
10482 |
// If this is an InlineAsm we have to match the registers required, not the |
--- |
| 10483 |
// notional registers required by the type. |
--- |
10483 |
// notional registers required by the type. |
--- |
| 10484 |
|
--- |
10484 |
|
--- |
| 10485 |
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(), |
0 |
10485 |
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(), |
0 |
| 10486 |
std::nullopt); // This is not an ABI copy. |
0 |
10486 |
std::nullopt); // This is not an ABI copy. |
0 |
| 10487 |
SDValue Chain = DAG.getEntryNode(); |
0 |
10487 |
SDValue Chain = DAG.getEntryNode(); |
0 |
| 10488 |
|
--- |
10488 |
|
--- |
| 10489 |
if (ExtendType == ISD::ANY_EXTEND) { |
0 |
10489 |
if (ExtendType == ISD::ANY_EXTEND) { |
0 |
| 10490 |
auto PreferredExtendIt = FuncInfo.PreferredExtendType.find(V); |
0 |
10490 |
auto PreferredExtendIt = FuncInfo.PreferredExtendType.find(V); |
0 |
| 10491 |
if (PreferredExtendIt != FuncInfo.PreferredExtendType.end()) |
0 |
10491 |
if (PreferredExtendIt != FuncInfo.PreferredExtendType.end()) |
0 |
| 10492 |
ExtendType = PreferredExtendIt->second; |
0 |
10492 |
ExtendType = PreferredExtendIt->second; |
0 |
| 10493 |
} |
--- |
10493 |
} |
--- |
| 10494 |
RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType); |
0 |
10494 |
RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType); |
0 |
| 10495 |
PendingExports.push_back(Chain); |
0 |
10495 |
PendingExports.push_back(Chain); |
0 |
| 10496 |
} |
0 |
10496 |
} |
0 |
| 10497 |
|
--- |
10497 |
|
--- |
| 10498 |
#include "llvm/CodeGen/SelectionDAGISel.h" |
--- |
10498 |
#include "llvm/CodeGen/SelectionDAGISel.h" |
--- |
| 10499 |
|
--- |
10499 |
|
--- |
| 10500 |
/// isOnlyUsedInEntryBlock - If the specified argument is only used in the |
--- |
10500 |
/// isOnlyUsedInEntryBlock - If the specified argument is only used in the |
--- |
| 10501 |
/// entry block, return true. This includes arguments used by switches, since |
--- |
10501 |
/// entry block, return true. This includes arguments used by switches, since |
--- |
| 10502 |
/// the switch may expand into multiple basic blocks. |
--- |
10502 |
/// the switch may expand into multiple basic blocks. |
--- |
| 10503 |
static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { |
0 |
10503 |
static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { |
0 |
| 10504 |
// With FastISel active, we may be splitting blocks, so force creation |
--- |
10504 |
// With FastISel active, we may be splitting blocks, so force creation |
--- |
| 10505 |
// of virtual registers for all non-dead arguments. |
--- |
10505 |
// of virtual registers for all non-dead arguments. |
--- |
| 10506 |
if (FastISel) |
0 |
10506 |
if (FastISel) |
0 |
| 10507 |
return A->use_empty(); |
0 |
10507 |
return A->use_empty(); |
0 |
| 10508 |
|
--- |
10508 |
|
--- |
| 10509 |
const BasicBlock &Entry = A->getParent()->front(); |
0 |
10509 |
const BasicBlock &Entry = A->getParent()->front(); |
0 |
| 10510 |
for (const User *U : A->users()) |
0 |
10510 |
for (const User *U : A->users()) |
0 |
| 10511 |
if (cast(U)->getParent() != &Entry || isa(U)) |
0 |
10511 |
if (cast(U)->getParent() != &Entry || isa(U)) |
0 |
| 10512 |
return false; // Use not in entry block. |
0 |
10512 |
return false; // Use not in entry block. |
0 |
| 10513 |
|
--- |
10513 |
|
--- |
| 10514 |
return true; |
0 |
10514 |
return true; |
0 |
| 10515 |
} |
--- |
10515 |
} |
--- |
| 10516 |
|
--- |
10516 |
|
--- |
| 10517 |
using ArgCopyElisionMapTy = |
--- |
10517 |
using ArgCopyElisionMapTy = |
--- |
| 10518 |
DenseMap
| --- |
10518 |
DenseMap
| --- |
| |
| 10519 |
std::pair>; |
--- |
10519 |
std::pair>; |
--- |
| 10520 |
|
--- |
10520 |
|
--- |
| 10521 |
/// Scan the entry block of the function in FuncInfo for arguments that look |
--- |
10521 |
/// Scan the entry block of the function in FuncInfo for arguments that look |
--- |
| 10522 |
/// like copies into a local alloca. Record any copied arguments in |
--- |
10522 |
/// like copies into a local alloca. Record any copied arguments in |
--- |
| 10523 |
/// ArgCopyElisionCandidates. |
--- |
10523 |
/// ArgCopyElisionCandidates. |
--- |
| 10524 |
static void |
--- |
10524 |
static void |
--- |
| 10525 |
findArgumentCopyElisionCandidates(const DataLayout &DL, |
1 |
10525 |
findArgumentCopyElisionCandidates(const DataLayout &DL, |
1 |
| 10526 |
FunctionLoweringInfo *FuncInfo, |
--- |
10526 |
FunctionLoweringInfo *FuncInfo, |
--- |
| 10527 |
ArgCopyElisionMapTy &ArgCopyElisionCandidates) { |
--- |
10527 |
ArgCopyElisionMapTy &ArgCopyElisionCandidates) { |
--- |
| 10528 |
// Record the state of every static alloca used in the entry block. Argument |
--- |
10528 |
// Record the state of every static alloca used in the entry block. Argument |
--- |
| 10529 |
// allocas are all used in the entry block, so we need approximately as many |
--- |
10529 |
// allocas are all used in the entry block, so we need approximately as many |
--- |
| 10530 |
// entries as we have arguments. |
--- |
10530 |
// entries as we have arguments. |
--- |
| 10531 |
enum StaticAllocaInfo { Unknown, Clobbered, Elidable }; |
--- |
10531 |
enum StaticAllocaInfo { Unknown, Clobbered, Elidable }; |
--- |
| 10532 |
SmallDenseMap StaticAllocas; |
1 |
10532 |
SmallDenseMap StaticAllocas; |
1 |
| 10533 |
unsigned NumArgs = FuncInfo->Fn->arg_size(); |
1 |
10533 |
unsigned NumArgs = FuncInfo->Fn->arg_size(); |
1 |
| 10534 |
StaticAllocas.reserve(NumArgs * 2); |
1 |
10534 |
StaticAllocas.reserve(NumArgs * 2); |
1 |
| 10535 |
|
--- |
10535 |
|
--- |
| 10536 |
auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * { |
7 |
10536 |
auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * { |
7 |
| 10537 |
if (!V) |
7 |
10537 |
if (!V) |
7 |
| 10538 |
return nullptr; |
0 |
10538 |
return nullptr; |
0 |
| 10539 |
V = V->stripPointerCasts(); |
7 |
10539 |
V = V->stripPointerCasts(); |
7 |
| 10540 |
const auto *AI = dyn_cast(V); |
7 |
10540 |
const auto *AI = dyn_cast(V); |
7 |
| 10541 |
if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI)) |
7 |
10541 |
if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI)) |
7 |
| 10542 |
return nullptr; |
5 |
10542 |
return nullptr; |
5 |
| 10543 |
auto Iter = StaticAllocas.insert({AI, Unknown}); |
2 |
10543 |
auto Iter = StaticAllocas.insert({AI, Unknown}); |
2 |
| 10544 |
return &Iter.first->second; |
2 |
10544 |
return &Iter.first->second; |
2 |
| 10545 |
}; |
1 |
10545 |
}; |
1 |
| 10546 |
|
--- |
10546 |
|
--- |
| 10547 |
// Look for stores of arguments to static allocas. Look through bitcasts and |
--- |
10547 |
// Look for stores of arguments to static allocas. Look through bitcasts and |
--- |
| 10548 |
// GEPs to handle type coercions, as long as the alloca is fully initialized |
--- |
10548 |
// GEPs to handle type coercions, as long as the alloca is fully initialized |
--- |
| 10549 |
// by the store. Any non-store use of an alloca escapes it and any subsequent |
--- |
10549 |
// by the store. Any non-store use of an alloca escapes it and any subsequent |
--- |
| 10550 |
// unanalyzed store might write it. |
--- |
10550 |
// unanalyzed store might write it. |
--- |
| 10551 |
// FIXME: Handle structs initialized with multiple stores. |
--- |
10551 |
// FIXME: Handle structs initialized with multiple stores. |
--- |
| 10552 |
for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) { |
6 |
10552 |
for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) { |
5 |
| 10553 |
// Look for stores, and handle non-store uses conservatively. |
--- |
10553 |
// Look for stores, and handle non-store uses conservatively. |
--- |
| 10554 |
const auto *SI = dyn_cast(&I); |
6 |
10554 |
const auto *SI = dyn_cast(&I); |
5 |
| 10555 |
if (!SI) { |
6 |
10555 |
if (!SI) { |
5 |
| 10556 |
// We will look through cast uses, so ignore them completely. |
--- |
10556 |
// We will look through cast uses, so ignore them completely. |
--- |
| 10557 |
if (I.isCast()) |
4 |
10557 |
if (I.isCast()) |
3 |
| 10558 |
continue; |
4 |
10558 |
continue; |
3 |
| 10559 |
// Ignore debug info and pseudo op intrinsics, they don't escape or store |
--- |
10559 |
// Ignore debug info and pseudo op intrinsics, they don't escape or store |
--- |
| 10560 |
// to allocas. |
--- |
10560 |
// to allocas. |
--- |
| 10561 |
if (I.isDebugOrPseudoInst()) |
4 |
10561 |
if (I.isDebugOrPseudoInst()) |
3 |
| 10562 |
continue; |
1 |
10562 |
continue; |
0 |
| 10563 |
// This is an unknown instruction. Assume it escapes or writes to all |
--- |
10563 |
// This is an unknown instruction. Assume it escapes or writes to all |
--- |
| 10564 |
// static alloca operands. |
--- |
10564 |
// static alloca operands. |
--- |
| 10565 |
for (const Use &U : I.operands()) { |
6 |
10565 |
for (const Use &U : I.operands()) { |
6 |
| 10566 |
if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U)) |
3 |
10566 |
if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U)) |
3 |
| 10567 |
*Info = StaticAllocaInfo::Clobbered; |
0 |
10567 |
*Info = StaticAllocaInfo::Clobbered; |
0 |
| 10568 |
} |
--- |
10568 |
} |
--- |
| 10569 |
continue; |
3 |
10569 |
continue; |
3 |
| 10570 |
} |
3 |
10570 |
} |
3 |
| 10571 |
|
--- |
10571 |
|
--- |
| 10572 |
// If the stored value is a static alloca, mark it as escaped. |
--- |
10572 |
// If the stored value is a static alloca, mark it as escaped. |
--- |
| 10573 |
if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand())) |
2 |
10573 |
if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand())) |
2 |
| 10574 |
*Info = StaticAllocaInfo::Clobbered; |
0 |
10574 |
*Info = StaticAllocaInfo::Clobbered; |
0 |
| 10575 |
|
--- |
10575 |
|
--- |
| 10576 |
// Check if the destination is a static alloca. |
--- |
10576 |
// Check if the destination is a static alloca. |
--- |
| 10577 |
const Value *Dst = SI->getPointerOperand()->stripPointerCasts(); |
2 |
10577 |
const Value *Dst = SI->getPointerOperand()->stripPointerCasts(); |
2 |
| 10578 |
StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst); |
2 |
10578 |
StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst); |
2 |
| 10579 |
if (!Info) |
2 |
10579 |
if (!Info) |
2 |
| 10580 |
continue; |
0 |
10580 |
continue; |
0 |
| 10581 |
const AllocaInst *AI = cast(Dst); |
2 |
10581 |
const AllocaInst *AI = cast(Dst); |
2 |
| 10582 |
|
--- |
10582 |
|
--- |
| 10583 |
// Skip allocas that have been initialized or clobbered. |
--- |
10583 |
// Skip allocas that have been initialized or clobbered. |
--- |
| 10584 |
if (*Info != StaticAllocaInfo::Unknown) |
2 |
10584 |
if (*Info != StaticAllocaInfo::Unknown) |
2 |
| 10585 |
continue; |
0 |
10585 |
continue; |
0 |
| 10586 |
|
--- |
10586 |
|
--- |
| 10587 |
// Check if the stored value is an argument, and that this store fully |
--- |
10587 |
// Check if the stored value is an argument, and that this store fully |
--- |
| 10588 |
// initializes the alloca. |
--- |
10588 |
// initializes the alloca. |
--- |
| 10589 |
// If the argument type has padding bits we can't directly forward a pointer |
--- |
10589 |
// If the argument type has padding bits we can't directly forward a pointer |
--- |
| 10590 |
// as the upper bits may contain garbage. |
--- |
10590 |
// as the upper bits may contain garbage. |
--- |
| 10591 |
// Don't elide copies from the same argument twice. |
--- |
10591 |
// Don't elide copies from the same argument twice. |
--- |
| 10592 |
const Value *Val = SI->getValueOperand()->stripPointerCasts(); |
2 |
10592 |
const Value *Val = SI->getValueOperand()->stripPointerCasts(); |
2 |
| 10593 |
const auto *Arg = dyn_cast(Val); |
2 |
10593 |
const auto *Arg = dyn_cast(Val); |
2 |
| 10594 |
if (!Arg || Arg->hasPassPointeeByValueCopyAttr() || |
4 |
10594 |
if (!Arg || Arg->hasPassPointeeByValueCopyAttr() || |
4 |
| 10595 |
Arg->getType()->isEmptyTy() || |
4 |
10595 |
Arg->getType()->isEmptyTy() || |
4 |
| 10596 |
DL.getTypeStoreSize(Arg->getType()) != |
2 |
10596 |
DL.getTypeStoreSize(Arg->getType()) != |
2 |
| 10597 |
DL.getTypeAllocSize(AI->getAllocatedType()) || |
2 |
10597 |
DL.getTypeAllocSize(AI->getAllocatedType()) || |
2 |
| 10598 |
!DL.typeSizeEqualsStoreSize(Arg->getType()) || |
6 |
10598 |
!DL.typeSizeEqualsStoreSize(Arg->getType()) || |
6 |
| 10599 |
ArgCopyElisionCandidates.count(Arg)) { |
2 |
10599 |
ArgCopyElisionCandidates.count(Arg)) { |
2 |
| 10600 |
*Info = StaticAllocaInfo::Clobbered; |
0 |
10600 |
*Info = StaticAllocaInfo::Clobbered; |
0 |
| 10601 |
continue; |
0 |
10601 |
continue; |
0 |
| 10602 |
} |
--- |
10602 |
} |
--- |
| 10603 |
|
--- |
10603 |
|
--- |
| 10604 |
LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI |
2 |
10604 |
LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI |
2 |
| 10605 |
<< '\n'); |
--- |
10605 |
<< '\n'); |
--- |
| 10606 |
|
--- |
10606 |
|
--- |
| 10607 |
// Mark this alloca and store for argument copy elision. |
--- |
10607 |
// Mark this alloca and store for argument copy elision. |
--- |
| 10608 |
*Info = StaticAllocaInfo::Elidable; |
2 |
10608 |
*Info = StaticAllocaInfo::Elidable; |
2 |
| 10609 |
ArgCopyElisionCandidates.insert({Arg, {AI, SI}}); |
2 |
10609 |
ArgCopyElisionCandidates.insert({Arg, {AI, SI}}); |
2 |
| 10610 |
|
--- |
10610 |
|
--- |
| 10611 |
// Stop scanning if we've seen all arguments. This will happen early in -O0 |
--- |
10611 |
// Stop scanning if we've seen all arguments. This will happen early in -O0 |
--- |
| 10612 |
// builds, which is useful, because -O0 builds have large entry blocks and |
--- |
10612 |
// builds, which is useful, because -O0 builds have large entry blocks and |
--- |
| 10613 |
// many allocas. |
--- |
10613 |
// many allocas. |
--- |
| 10614 |
if (ArgCopyElisionCandidates.size() == NumArgs) |
2 |
10614 |
if (ArgCopyElisionCandidates.size() == NumArgs) |
2 |
| 10615 |
break; |
1 |
10615 |
break; |
1 |
| 10616 |
} |
--- |
10616 |
} |
--- |
| 10617 |
} |
1 |
10617 |
} |
1 |
| 10618 |
|
--- |
10618 |
|
--- |
| 10619 |
/// Try to elide argument copies from memory into a local alloca. Succeeds if |
--- |
10619 |
/// Try to elide argument copies from memory into a local alloca. Succeeds if |
--- |
| 10620 |
/// ArgVal is a load from a suitable fixed stack object. |
--- |
10620 |
/// ArgVal is a load from a suitable fixed stack object. |
--- |
| 10621 |
static void tryToElideArgumentCopy( |
2 |
10621 |
static void tryToElideArgumentCopy( |
2 |
| 10622 |
FunctionLoweringInfo &FuncInfo, SmallVectorImpl &Chains, |
--- |
10622 |
FunctionLoweringInfo &FuncInfo, SmallVectorImpl &Chains, |
--- |
| 10623 |
DenseMap &ArgCopyElisionFrameIndexMap, |
--- |
10623 |
DenseMap &ArgCopyElisionFrameIndexMap, |
--- |
| 10624 |
SmallPtrSetImpl &ElidedArgCopyInstrs, |
--- |
10624 |
SmallPtrSetImpl &ElidedArgCopyInstrs, |
--- |
| 10625 |
ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, |
--- |
10625 |
ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, |
--- |
| 10626 |
ArrayRef ArgVals, bool &ArgHasUses) { |
--- |
10626 |
ArrayRef ArgVals, bool &ArgHasUses) { |
--- |
| 10627 |
// Check if this is a load from a fixed stack object. |
--- |
10627 |
// Check if this is a load from a fixed stack object. |
--- |
| 10628 |
auto *LNode = dyn_cast(ArgVals[0]); |
2 |
10628 |
auto *LNode = dyn_cast(ArgVals[0]); |
2 |
| 10629 |
if (!LNode) |
2 |
10629 |
if (!LNode) |
2 |
| 10630 |
return; |
2 |
10630 |
return; |
2 |
| 10631 |
auto *FINode = dyn_cast(LNode->getBasePtr().getNode()); |
0 |
10631 |
auto *FINode = dyn_cast(LNode->getBasePtr().getNode()); |
0 |
| 10632 |
if (!FINode) |
0 |
10632 |
if (!FINode) |
0 |
| 10633 |
return; |
0 |
10633 |
return; |
0 |
| 10634 |
|
--- |
10634 |
|
--- |
| 10635 |
// Check that the fixed stack object is the right size and alignment. |
--- |
10635 |
// Check that the fixed stack object is the right size and alignment. |
--- |
| 10636 |
// Look at the alignment that the user wrote on the alloca instead of looking |
--- |
10636 |
// Look at the alignment that the user wrote on the alloca instead of looking |
--- |
| 10637 |
// at the stack object. |
--- |
10637 |
// at the stack object. |
--- |
| 10638 |
auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg); |
0 |
10638 |
auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg); |
0 |
| 10639 |
assert(ArgCopyIter != ArgCopyElisionCandidates.end()); |
0 |
10639 |
assert(ArgCopyIter != ArgCopyElisionCandidates.end()); |
0 |
| 10640 |
const AllocaInst *AI = ArgCopyIter->second.first; |
0 |
10640 |
const AllocaInst *AI = ArgCopyIter->second.first; |
0 |
| 10641 |
int FixedIndex = FINode->getIndex(); |
0 |
10641 |
int FixedIndex = FINode->getIndex(); |
0 |
| 10642 |
int &AllocaIndex = FuncInfo.StaticAllocaMap[AI]; |
0 |
10642 |
int &AllocaIndex = FuncInfo.StaticAllocaMap[AI]; |
0 |
| 10643 |
int OldIndex = AllocaIndex; |
0 |
10643 |
int OldIndex = AllocaIndex; |
0 |
| 10644 |
MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo(); |
0 |
10644 |
MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo(); |
0 |
| 10645 |
if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) { |
0 |
10645 |
if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) { |
0 |
| 10646 |
LLVM_DEBUG( |
0 |
10646 |
LLVM_DEBUG( |
0 |
| 10647 |
dbgs() << " argument copy elision failed due to bad fixed stack " |
--- |
10647 |
dbgs() << " argument copy elision failed due to bad fixed stack " |
--- |
| 10648 |
"object size\n"); |
--- |
10648 |
"object size\n"); |
--- |
| 10649 |
return; |
0 |
10649 |
return; |
0 |
| 10650 |
} |
--- |
10650 |
} |
--- |
| 10651 |
Align RequiredAlignment = AI->getAlign(); |
0 |
10651 |
Align RequiredAlignment = AI->getAlign(); |
0 |
| 10652 |
if (MFI.getObjectAlign(FixedIndex) < RequiredAlignment) { |
0 |
10652 |
if (MFI.getObjectAlign(FixedIndex) < RequiredAlignment) { |
0 |
| 10653 |
LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca " |
0 |
10653 |
LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca " |
0 |
| 10654 |
"greater than stack argument alignment (" |
--- |
10654 |
"greater than stack argument alignment (" |
--- |
| 10655 |
<< DebugStr(RequiredAlignment) << " vs " |
--- |
10655 |
<< DebugStr(RequiredAlignment) << " vs " |
--- |
| 10656 |
<< DebugStr(MFI.getObjectAlign(FixedIndex)) << ")\n"); |
--- |
10656 |
<< DebugStr(MFI.getObjectAlign(FixedIndex)) << ")\n"); |
--- |
| 10657 |
return; |
0 |
10657 |
return; |
0 |
| 10658 |
} |
--- |
10658 |
} |
--- |
| 10659 |
|
--- |
10659 |
|
--- |
| 10660 |
// Perform the elision. Delete the old stack object and replace its only use |
--- |
10660 |
// Perform the elision. Delete the old stack object and replace its only use |
--- |
| 10661 |
// in the variable info map. Mark the stack object as mutable. |
--- |
10661 |
// in the variable info map. Mark the stack object as mutable. |
--- |
| 10662 |
LLVM_DEBUG({ |
0 |
10662 |
LLVM_DEBUG({ |
0 |
| 10663 |
dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' |
--- |
10663 |
dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' |
--- |
| 10664 |
<< " Replacing frame index " << OldIndex << " with " << FixedIndex |
--- |
10664 |
<< " Replacing frame index " << OldIndex << " with " << FixedIndex |
--- |
| 10665 |
<< '\n'; |
--- |
10665 |
<< '\n'; |
--- |
| 10666 |
}); |
--- |
10666 |
}); |
--- |
| 10667 |
MFI.RemoveStackObject(OldIndex); |
0 |
10667 |
MFI.RemoveStackObject(OldIndex); |
0 |
| 10668 |
MFI.setIsImmutableObjectIndex(FixedIndex, false); |
0 |
10668 |
MFI.setIsImmutableObjectIndex(FixedIndex, false); |
0 |
| 10669 |
AllocaIndex = FixedIndex; |
0 |
10669 |
AllocaIndex = FixedIndex; |
0 |
| 10670 |
ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex}); |
0 |
10670 |
ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex}); |
0 |
| 10671 |
for (SDValue ArgVal : ArgVals) |
0 |
10671 |
for (SDValue ArgVal : ArgVals) |
0 |
| 10672 |
Chains.push_back(ArgVal.getValue(1)); |
0 |
10672 |
Chains.push_back(ArgVal.getValue(1)); |
0 |
| 10673 |
|
--- |
10673 |
|
--- |
| 10674 |
// Avoid emitting code for the store implementing the copy. |
--- |
10674 |
// Avoid emitting code for the store implementing the copy. |
--- |
| 10675 |
const StoreInst *SI = ArgCopyIter->second.second; |
0 |
10675 |
const StoreInst *SI = ArgCopyIter->second.second; |
0 |
| 10676 |
ElidedArgCopyInstrs.insert(SI); |
0 |
10676 |
ElidedArgCopyInstrs.insert(SI); |
0 |
| 10677 |
|
--- |
10677 |
|
--- |
| 10678 |
// Check for uses of the argument again so that we can avoid exporting ArgVal |
--- |
10678 |
// Check for uses of the argument again so that we can avoid exporting ArgVal |
--- |
| 10679 |
// if it is't used by anything other than the store. |
--- |
10679 |
// if it is't used by anything other than the store. |
--- |
| 10680 |
for (const Value *U : Arg.users()) { |
0 |
10680 |
for (const Value *U : Arg.users()) { |
0 |
| 10681 |
if (U != SI) { |
0 |
10681 |
if (U != SI) { |
0 |
| 10682 |
ArgHasUses = true; |
0 |
10682 |
ArgHasUses = true; |
0 |
| 10683 |
break; |
0 |
10683 |
break; |
0 |
| 10684 |
} |
--- |
10684 |
} |
--- |
| 10685 |
} |
--- |
10685 |
} |
--- |
| 10686 |
} |
--- |
10686 |
} |
--- |
| 10687 |
|
--- |
10687 |
|
--- |
| 10688 |
void SelectionDAGISel::LowerArguments(const Function &F) { |
1 |
10688 |
void SelectionDAGISel::LowerArguments(const Function &F) { |
1 |
| 10689 |
SelectionDAG &DAG = SDB->DAG; |
1 |
10689 |
SelectionDAG &DAG = SDB->DAG; |
1 |
| 10690 |
SDLoc dl = SDB->getCurSDLoc(); |
1 |
10690 |
SDLoc dl = SDB->getCurSDLoc(); |
1 |
| 10691 |
const DataLayout &DL = DAG.getDataLayout(); |
1 |
10691 |
const DataLayout &DL = DAG.getDataLayout(); |
1 |
| 10692 |
SmallVector Ins; |
1 |
10692 |
SmallVector Ins; |
1 |
| 10693 |
|
--- |
10693 |
|
--- |
| 10694 |
// In Naked functions we aren't going to save any registers. |
--- |
10694 |
// In Naked functions we aren't going to save any registers. |
--- |
| 10695 |
if (F.hasFnAttribute(Attribute::Naked)) |
1 |
10695 |
if (F.hasFnAttribute(Attribute::Naked)) |
1 |
| 10696 |
return; |
0 |
10696 |
return; |
0 |
| 10697 |
|
--- |
10697 |
|
--- |
| 10698 |
if (!FuncInfo->CanLowerReturn) { |
1 |
10698 |
if (!FuncInfo->CanLowerReturn) { |
1 |
| 10699 |
// Put in an sret pointer parameter before all the other parameters. |
--- |
10699 |
// Put in an sret pointer parameter before all the other parameters. |
--- |
| 10700 |
SmallVector ValueVTs; |
0 |
10700 |
SmallVector ValueVTs; |
0 |
| 10701 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), |
0 |
10701 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), |
0 |
| 10702 |
PointerType::get(F.getContext(), |
0 |
10702 |
PointerType::get(F.getContext(), |
0 |
| 10703 |
DAG.getDataLayout().getAllocaAddrSpace()), |
0 |
10703 |
DAG.getDataLayout().getAllocaAddrSpace()), |
0 |
| 10704 |
ValueVTs); |
--- |
10704 |
ValueVTs); |
--- |
| 10705 |
|
--- |
10705 |
|
--- |
| 10706 |
// NOTE: Assuming that a pointer will never break down to more than one VT |
--- |
10706 |
// NOTE: Assuming that a pointer will never break down to more than one VT |
--- |
| 10707 |
// or one register. |
--- |
10707 |
// or one register. |
--- |
| 10708 |
ISD::ArgFlagsTy Flags; |
0 |
10708 |
ISD::ArgFlagsTy Flags; |
0 |
| 10709 |
Flags.setSRet(); |
0 |
10709 |
Flags.setSRet(); |
0 |
| 10710 |
MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); |
0 |
10710 |
MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); |
0 |
| 10711 |
ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, |
0 |
10711 |
ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, |
0 |
| 10712 |
ISD::InputArg::NoArgIndex, 0); |
0 |
10712 |
ISD::InputArg::NoArgIndex, 0); |
0 |
| 10713 |
Ins.push_back(RetArg); |
0 |
10713 |
Ins.push_back(RetArg); |
0 |
| 10714 |
} |
0 |
10714 |
} |
0 |
| 10715 |
|
--- |
10715 |
|
--- |
| 10716 |
// Look for stores of arguments to static allocas. Mark such arguments with a |
--- |
10716 |
// Look for stores of arguments to static allocas. Mark such arguments with a |
--- |
| 10717 |
// flag to ask the target to give us the memory location of that argument if |
--- |
10717 |
// flag to ask the target to give us the memory location of that argument if |
--- |
| 10718 |
// available. |
--- |
10718 |
// available. |
--- |
| 10719 |
ArgCopyElisionMapTy ArgCopyElisionCandidates; |
1 |
10719 |
ArgCopyElisionMapTy ArgCopyElisionCandidates; |
1 |
| 10720 |
findArgumentCopyElisionCandidates(DL, FuncInfo.get(), |
1 |
10720 |
findArgumentCopyElisionCandidates(DL, FuncInfo.get(), |
1 |
| 10721 |
ArgCopyElisionCandidates); |
--- |
10721 |
ArgCopyElisionCandidates); |
--- |
| 10722 |
|
--- |
10722 |
|
--- |
| 10723 |
// Set up the incoming argument description vector. |
--- |
10723 |
// Set up the incoming argument description vector. |
--- |
| 10724 |
for (const Argument &Arg : F.args()) { |
3 |
10724 |
for (const Argument &Arg : F.args()) { |
3 |
| 10725 |
unsigned ArgNo = Arg.getArgNo(); |
2 |
10725 |
unsigned ArgNo = Arg.getArgNo(); |
2 |
| 10726 |
SmallVector ValueVTs; |
2 |
10726 |
SmallVector ValueVTs; |
2 |
| 10727 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); |
2 |
10727 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); |
2 |
| 10728 |
bool isArgValueUsed = !Arg.use_empty(); |
2 |
10728 |
bool isArgValueUsed = !Arg.use_empty(); |
2 |
| 10729 |
unsigned PartBase = 0; |
2 |
10729 |
unsigned PartBase = 0; |
2 |
| 10730 |
Type *FinalType = Arg.getType(); |
2 |
10730 |
Type *FinalType = Arg.getType(); |
2 |
| 10731 |
if (Arg.hasAttribute(Attribute::ByVal)) |
2 |
10731 |
if (Arg.hasAttribute(Attribute::ByVal)) |
2 |
| 10732 |
FinalType = Arg.getParamByValType(); |
0 |
10732 |
FinalType = Arg.getParamByValType(); |
0 |
| 10733 |
bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( |
2 |
10733 |
bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( |
2 |
| 10734 |
FinalType, F.getCallingConv(), F.isVarArg(), DL); |
2 |
10734 |
FinalType, F.getCallingConv(), F.isVarArg(), DL); |
2 |
| 10735 |
for (unsigned Value = 0, NumValues = ValueVTs.size(); |
2 |
10735 |
for (unsigned Value = 0, NumValues = ValueVTs.size(); |
2 |
| 10736 |
Value != NumValues; ++Value) { |
4 |
10736 |
Value != NumValues; ++Value) { |
4 |
| 10737 |
EVT VT = ValueVTs[Value]; |
2 |
10737 |
EVT VT = ValueVTs[Value]; |
2 |
| 10738 |
Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); |
2 |
10738 |
Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); |
2 |
| 10739 |
ISD::ArgFlagsTy Flags; |
2 |
10739 |
ISD::ArgFlagsTy Flags; |
2 |
| 10740 |
|
--- |
10740 |
|
--- |
| 10741 |
|
--- |
10741 |
|
--- |
| 10742 |
if (Arg.getType()->isPointerTy()) { |
2 |
10742 |
if (Arg.getType()->isPointerTy()) { |
2 |
| 10743 |
Flags.setPointer(); |
0 |
10743 |
Flags.setPointer(); |
0 |
| 10744 |
Flags.setPointerAddrSpace( |
0 |
10744 |
Flags.setPointerAddrSpace( |
0 |
| 10745 |
cast(Arg.getType())->getAddressSpace()); |
--- |
10745 |
cast(Arg.getType())->getAddressSpace()); |
--- |
| 10746 |
} |
--- |
10746 |
} |
--- |
| 10747 |
if (Arg.hasAttribute(Attribute::ZExt)) |
2 |
10747 |
if (Arg.hasAttribute(Attribute::ZExt)) |
2 |
| 10748 |
Flags.setZExt(); |
0 |
10748 |
Flags.setZExt(); |
0 |
| 10749 |
if (Arg.hasAttribute(Attribute::SExt)) |
2 |
10749 |
if (Arg.hasAttribute(Attribute::SExt)) |
2 |
| 10750 |
Flags.setSExt(); |
2 |
10750 |
Flags.setSExt(); |
2 |
| 10751 |
if (Arg.hasAttribute(Attribute::InReg)) { |
2 |
10751 |
if (Arg.hasAttribute(Attribute::InReg)) { |
2 |
| 10752 |
// If we are using vectorcall calling convention, a structure that is |
--- |
10752 |
// If we are using vectorcall calling convention, a structure that is |
--- |
| 10753 |
// passed InReg - is surely an HVA |
--- |
10753 |
// passed InReg - is surely an HVA |
--- |
| 10754 |
if (F.getCallingConv() == CallingConv::X86_VectorCall && |
0 |
10754 |
if (F.getCallingConv() == CallingConv::X86_VectorCall && |
0 |
| 10755 |
isa(Arg.getType())) { |
0 |
10755 |
isa(Arg.getType())) { |
0 |
| 10756 |
// The first value of a structure is marked |
--- |
10756 |
// The first value of a structure is marked |
--- |
| 10757 |
if (0 == Value) |
0 |
10757 |
if (0 == Value) |
0 |
| 10758 |
Flags.setHvaStart(); |
0 |
10758 |
Flags.setHvaStart(); |
0 |
| 10759 |
Flags.setHva(); |
0 |
10759 |
Flags.setHva(); |
0 |
| 10760 |
} |
--- |
10760 |
} |
--- |
| 10761 |
// Set InReg Flag |
--- |
10761 |
// Set InReg Flag |
--- |
| 10762 |
Flags.setInReg(); |
0 |
10762 |
Flags.setInReg(); |
0 |
| 10763 |
} |
--- |
10763 |
} |
--- |
| 10764 |
if (Arg.hasAttribute(Attribute::StructRet)) |
2 |
10764 |
if (Arg.hasAttribute(Attribute::StructRet)) |
2 |
| 10765 |
Flags.setSRet(); |
0 |
10765 |
Flags.setSRet(); |
0 |
| 10766 |
if (Arg.hasAttribute(Attribute::SwiftSelf)) |
2 |
10766 |
if (Arg.hasAttribute(Attribute::SwiftSelf)) |
2 |
| 10767 |
Flags.setSwiftSelf(); |
0 |
10767 |
Flags.setSwiftSelf(); |
0 |
| 10768 |
if (Arg.hasAttribute(Attribute::SwiftAsync)) |
2 |
10768 |
if (Arg.hasAttribute(Attribute::SwiftAsync)) |
2 |
| 10769 |
Flags.setSwiftAsync(); |
0 |
10769 |
Flags.setSwiftAsync(); |
0 |
| 10770 |
if (Arg.hasAttribute(Attribute::SwiftError)) |
2 |
10770 |
if (Arg.hasAttribute(Attribute::SwiftError)) |
2 |
| 10771 |
Flags.setSwiftError(); |
0 |
10771 |
Flags.setSwiftError(); |
0 |
| 10772 |
if (Arg.hasAttribute(Attribute::ByVal)) |
2 |
10772 |
if (Arg.hasAttribute(Attribute::ByVal)) |
2 |
| 10773 |
Flags.setByVal(); |
0 |
10773 |
Flags.setByVal(); |
0 |
| 10774 |
if (Arg.hasAttribute(Attribute::ByRef)) |
2 |
10774 |
if (Arg.hasAttribute(Attribute::ByRef)) |
2 |
| 10775 |
Flags.setByRef(); |
0 |
10775 |
Flags.setByRef(); |
0 |
| 10776 |
if (Arg.hasAttribute(Attribute::InAlloca)) { |
2 |
10776 |
if (Arg.hasAttribute(Attribute::InAlloca)) { |
2 |
| 10777 |
Flags.setInAlloca(); |
0 |
10777 |
Flags.setInAlloca(); |
0 |
| 10778 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
10778 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
| 10779 |
// inalloca. This way we can know how many bytes we should've allocated |
--- |
10779 |
// inalloca. This way we can know how many bytes we should've allocated |
--- |
| 10780 |
// and how many bytes a callee cleanup function will pop. If we port |
--- |
10780 |
// and how many bytes a callee cleanup function will pop. If we port |
--- |
| 10781 |
// inalloca to more targets, we'll have to add custom inalloca handling |
--- |
10781 |
// inalloca to more targets, we'll have to add custom inalloca handling |
--- |
| 10782 |
// in the various CC lowering callbacks. |
--- |
10782 |
// in the various CC lowering callbacks. |
--- |
| 10783 |
Flags.setByVal(); |
0 |
10783 |
Flags.setByVal(); |
0 |
| 10784 |
} |
--- |
10784 |
} |
--- |
| 10785 |
if (Arg.hasAttribute(Attribute::Preallocated)) { |
2 |
10785 |
if (Arg.hasAttribute(Attribute::Preallocated)) { |
2 |
| 10786 |
Flags.setPreallocated(); |
0 |
10786 |
Flags.setPreallocated(); |
0 |
| 10787 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
10787 |
// Set the byval flag for CCAssignFn callbacks that don't know about |
--- |
| 10788 |
// preallocated. This way we can know how many bytes we should've |
--- |
10788 |
// preallocated. This way we can know how many bytes we should've |
--- |
| 10789 |
// allocated and how many bytes a callee cleanup function will pop. If |
--- |
10789 |
// allocated and how many bytes a callee cleanup function will pop. If |
--- |
| 10790 |
// we port preallocated to more targets, we'll have to add custom |
--- |
10790 |
// we port preallocated to more targets, we'll have to add custom |
--- |
| 10791 |
// preallocated handling in the various CC lowering callbacks. |
--- |
10791 |
// preallocated handling in the various CC lowering callbacks. |
--- |
| 10792 |
Flags.setByVal(); |
0 |
10792 |
Flags.setByVal(); |
0 |
| 10793 |
} |
--- |
10793 |
} |
--- |
| 10794 |
|
--- |
10794 |
|
--- |
| 10795 |
// Certain targets (such as MIPS), may have a different ABI alignment |
--- |
10795 |
// Certain targets (such as MIPS), may have a different ABI alignment |
--- |
| 10796 |
// for a type depending on the context. Give the target a chance to |
--- |
10796 |
// for a type depending on the context. Give the target a chance to |
--- |
| 10797 |
// specify the alignment it wants. |
--- |
10797 |
// specify the alignment it wants. |
--- |
| 10798 |
const Align OriginalAlignment( |
--- |
10798 |
const Align OriginalAlignment( |
--- |
| 10799 |
TLI->getABIAlignmentForCallingConv(ArgTy, DL)); |
2 |
10799 |
TLI->getABIAlignmentForCallingConv(ArgTy, DL)); |
2 |
| 10800 |
Flags.setOrigAlign(OriginalAlignment); |
2 |
10800 |
Flags.setOrigAlign(OriginalAlignment); |
2 |
| 10801 |
|
--- |
10801 |
|
--- |
| 10802 |
Align MemAlign; |
2 |
10802 |
Align MemAlign; |
2 |
| 10803 |
Type *ArgMemTy = nullptr; |
2 |
10803 |
Type *ArgMemTy = nullptr; |
2 |
| 10804 |
if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() || |
4 |
10804 |
if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() || |
4 |
| 10805 |
Flags.isByRef()) { |
2 |
10805 |
Flags.isByRef()) { |
2 |
| 10806 |
if (!ArgMemTy) |
0 |
10806 |
if (!ArgMemTy) |
0 |
| 10807 |
ArgMemTy = Arg.getPointeeInMemoryValueType(); |
0 |
10807 |
ArgMemTy = Arg.getPointeeInMemoryValueType(); |
0 |
| 10808 |
|
--- |
10808 |
|
--- |
| 10809 |
uint64_t MemSize = DL.getTypeAllocSize(ArgMemTy); |
0 |
10809 |
uint64_t MemSize = DL.getTypeAllocSize(ArgMemTy); |
0 |
| 10810 |
|
--- |
10810 |
|
--- |
| 10811 |
// For in-memory arguments, size and alignment should be passed from FE. |
--- |
10811 |
// For in-memory arguments, size and alignment should be passed from FE. |
--- |
| 10812 |
// BE will guess if this info is not there but there are cases it cannot |
--- |
10812 |
// BE will guess if this info is not there but there are cases it cannot |
--- |
| 10813 |
// get right. |
--- |
10813 |
// get right. |
--- |
| 10814 |
if (auto ParamAlign = Arg.getParamStackAlign()) |
0 |
10814 |
if (auto ParamAlign = Arg.getParamStackAlign()) |
0 |
| 10815 |
MemAlign = *ParamAlign; |
0 |
10815 |
MemAlign = *ParamAlign; |
0 |
| 10816 |
else if ((ParamAlign = Arg.getParamAlign())) |
0 |
10816 |
else if ((ParamAlign = Arg.getParamAlign())) |
0 |
| 10817 |
MemAlign = *ParamAlign; |
0 |
10817 |
MemAlign = *ParamAlign; |
0 |
| 10818 |
else |
--- |
10818 |
else |
--- |
| 10819 |
MemAlign = Align(TLI->getByValTypeAlignment(ArgMemTy, DL)); |
0 |
10819 |
MemAlign = Align(TLI->getByValTypeAlignment(ArgMemTy, DL)); |
0 |
| 10820 |
if (Flags.isByRef()) |
0 |
10820 |
if (Flags.isByRef()) |
0 |
| 10821 |
Flags.setByRefSize(MemSize); |
0 |
10821 |
Flags.setByRefSize(MemSize); |
0 |
| 10822 |
else |
--- |
10822 |
else |
--- |
| 10823 |
Flags.setByValSize(MemSize); |
0 |
10823 |
Flags.setByValSize(MemSize); |
0 |
| 10824 |
} else if (auto ParamAlign = Arg.getParamStackAlign()) { |
2 |
10824 |
} else if (auto ParamAlign = Arg.getParamStackAlign()) { |
2 |
| 10825 |
MemAlign = *ParamAlign; |
0 |
10825 |
MemAlign = *ParamAlign; |
0 |
| 10826 |
} else { |
--- |
10826 |
} else { |
--- |
| 10827 |
MemAlign = OriginalAlignment; |
2 |
10827 |
MemAlign = OriginalAlignment; |
2 |
| 10828 |
} |
--- |
10828 |
} |
--- |
| 10829 |
Flags.setMemAlign(MemAlign); |
2 |
10829 |
Flags.setMemAlign(MemAlign); |
2 |
| 10830 |
|
--- |
10830 |
|
--- |
| 10831 |
if (Arg.hasAttribute(Attribute::Nest)) |
2 |
10831 |
if (Arg.hasAttribute(Attribute::Nest)) |
2 |
| 10832 |
Flags.setNest(); |
0 |
10832 |
Flags.setNest(); |
0 |
| 10833 |
if (NeedsRegBlock) |
2 |
10833 |
if (NeedsRegBlock) |
2 |
| 10834 |
Flags.setInConsecutiveRegs(); |
0 |
10834 |
Flags.setInConsecutiveRegs(); |
0 |
| 10835 |
if (ArgCopyElisionCandidates.count(&Arg)) |
2 |
10835 |
if (ArgCopyElisionCandidates.count(&Arg)) |
2 |
| 10836 |
Flags.setCopyElisionCandidate(); |
2 |
10836 |
Flags.setCopyElisionCandidate(); |
2 |
| 10837 |
if (Arg.hasAttribute(Attribute::Returned)) |
2 |
10837 |
if (Arg.hasAttribute(Attribute::Returned)) |
2 |
| 10838 |
Flags.setReturned(); |
0 |
10838 |
Flags.setReturned(); |
0 |
| 10839 |
|
--- |
10839 |
|
--- |
| 10840 |
MVT RegisterVT = TLI->getRegisterTypeForCallingConv( |
4 |
10840 |
MVT RegisterVT = TLI->getRegisterTypeForCallingConv( |
4 |
| 10841 |
*CurDAG->getContext(), F.getCallingConv(), VT); |
2 |
10841 |
*CurDAG->getContext(), F.getCallingConv(), VT); |
2 |
| 10842 |
unsigned NumRegs = TLI->getNumRegistersForCallingConv( |
4 |
10842 |
unsigned NumRegs = TLI->getNumRegistersForCallingConv( |
4 |
| 10843 |
*CurDAG->getContext(), F.getCallingConv(), VT); |
2 |
10843 |
*CurDAG->getContext(), F.getCallingConv(), VT); |
2 |
| 10844 |
for (unsigned i = 0; i != NumRegs; ++i) { |
4 |
10844 |
for (unsigned i = 0; i != NumRegs; ++i) { |
4 |
| 10845 |
// For scalable vectors, use the minimum size; individual targets |
--- |
10845 |
// For scalable vectors, use the minimum size; individual targets |
--- |
| 10846 |
// are responsible for handling scalable vector arguments and |
--- |
10846 |
// are responsible for handling scalable vector arguments and |
--- |
| 10847 |
// return values. |
--- |
10847 |
// return values. |
--- |
| 10848 |
ISD::InputArg MyFlags( |
--- |
10848 |
ISD::InputArg MyFlags( |
--- |
| 10849 |
Flags, RegisterVT, VT, isArgValueUsed, ArgNo, |
--- |
10849 |
Flags, RegisterVT, VT, isArgValueUsed, ArgNo, |
--- |
| 10850 |
PartBase + i * RegisterVT.getStoreSize().getKnownMinValue()); |
2 |
10850 |
PartBase + i * RegisterVT.getStoreSize().getKnownMinValue()); |
2 |
| 10851 |
if (NumRegs > 1 && i == 0) |
2 |
10851 |
if (NumRegs > 1 && i == 0) |
2 |
| 10852 |
MyFlags.Flags.setSplit(); |
0 |
10852 |
MyFlags.Flags.setSplit(); |
0 |
| 10853 |
// if it isn't first piece, alignment must be 1 |
--- |
10853 |
// if it isn't first piece, alignment must be 1 |
--- |
| 10854 |
else if (i > 0) { |
2 |
10854 |
else if (i > 0) { |
2 |
| 10855 |
MyFlags.Flags.setOrigAlign(Align(1)); |
0 |
10855 |
MyFlags.Flags.setOrigAlign(Align(1)); |
0 |
| 10856 |
if (i == NumRegs - 1) |
0 |
10856 |
if (i == NumRegs - 1) |
0 |
| 10857 |
MyFlags.Flags.setSplitEnd(); |
0 |
10857 |
MyFlags.Flags.setSplitEnd(); |
0 |
| 10858 |
} |
--- |
10858 |
} |
--- |
| 10859 |
Ins.push_back(MyFlags); |
2 |
10859 |
Ins.push_back(MyFlags); |
2 |
| 10860 |
} |
--- |
10860 |
} |
--- |
| 10861 |
if (NeedsRegBlock && Value == NumValues - 1) |
2 |
10861 |
if (NeedsRegBlock && Value == NumValues - 1) |
2 |
| 10862 |
Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); |
0 |
10862 |
Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); |
0 |
| 10863 |
PartBase += VT.getStoreSize().getKnownMinValue(); |
2 |
10863 |
PartBase += VT.getStoreSize().getKnownMinValue(); |
2 |
| 10864 |
} |
--- |
10864 |
} |
--- |
| 10865 |
} |
2 |
10865 |
} |
2 |
| 10866 |
|
--- |
10866 |
|
--- |
| 10867 |
// Call the target to set up the argument values. |
--- |
10867 |
// Call the target to set up the argument values. |
--- |
| 10868 |
SmallVector InVals; |
1 |
10868 |
SmallVector InVals; |
1 |
| 10869 |
SDValue NewRoot = TLI->LowerFormalArguments( |
2 |
10869 |
SDValue NewRoot = TLI->LowerFormalArguments( |
2 |
| 10870 |
DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals); |
2 |
10870 |
DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals); |
2 |
| 10871 |
|
--- |
10871 |
|
--- |
| 10872 |
// Verify that the target's LowerFormalArguments behaved as expected. |
--- |
10872 |
// Verify that the target's LowerFormalArguments behaved as expected. |
--- |
| 10873 |
assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && |
1 |
10873 |
assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && |
1 |
| 10874 |
"LowerFormalArguments didn't return a valid chain!"); |
--- |
10874 |
"LowerFormalArguments didn't return a valid chain!"); |
--- |
| 10875 |
assert(InVals.size() == Ins.size() && |
1 |
10875 |
assert(InVals.size() == Ins.size() && |
1 |
| 10876 |
"LowerFormalArguments didn't emit the correct number of values!"); |
--- |
10876 |
"LowerFormalArguments didn't emit the correct number of values!"); |
--- |
| 10877 |
LLVM_DEBUG({ |
1 |
10877 |
LLVM_DEBUG({ |
1 |
| 10878 |
for (unsigned i = 0, e = Ins.size(); i != e; ++i) { |
--- |
10878 |
for (unsigned i = 0, e = Ins.size(); i != e; ++i) { |
--- |
| 10879 |
assert(InVals[i].getNode() && |
--- |
10879 |
assert(InVals[i].getNode() && |
--- |
| 10880 |
"LowerFormalArguments emitted a null value!"); |
--- |
10880 |
"LowerFormalArguments emitted a null value!"); |
--- |
| 10881 |
assert(EVT(Ins[i].VT) == InVals[i].getValueType() && |
--- |
10881 |
assert(EVT(Ins[i].VT) == InVals[i].getValueType() && |
--- |
| 10882 |
"LowerFormalArguments emitted a value with the wrong type!"); |
--- |
10882 |
"LowerFormalArguments emitted a value with the wrong type!"); |
--- |
| 10883 |
} |
--- |
10883 |
} |
--- |
| 10884 |
}); |
--- |
10884 |
}); |
--- |
| 10885 |
|
--- |
10885 |
|
--- |
| 10886 |
// Update the DAG with the new chain value resulting from argument lowering. |
--- |
10886 |
// Update the DAG with the new chain value resulting from argument lowering. |
--- |
| 10887 |
DAG.setRoot(NewRoot); |
1 |
10887 |
DAG.setRoot(NewRoot); |
1 |
| 10888 |
|
--- |
10888 |
|
--- |
| 10889 |
// Set up the argument values. |
--- |
10889 |
// Set up the argument values. |
--- |
| 10890 |
unsigned i = 0; |
1 |
10890 |
unsigned i = 0; |
1 |
| 10891 |
if (!FuncInfo->CanLowerReturn) { |
1 |
10891 |
if (!FuncInfo->CanLowerReturn) { |
1 |
| 10892 |
// Create a virtual register for the sret pointer, and put in a copy |
--- |
10892 |
// Create a virtual register for the sret pointer, and put in a copy |
--- |
| 10893 |
// from the sret argument into it. |
--- |
10893 |
// from the sret argument into it. |
--- |
| 10894 |
SmallVector ValueVTs; |
0 |
10894 |
SmallVector ValueVTs; |
0 |
| 10895 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), |
0 |
10895 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), |
0 |
| 10896 |
PointerType::get(F.getContext(), |
0 |
10896 |
PointerType::get(F.getContext(), |
0 |
| 10897 |
DAG.getDataLayout().getAllocaAddrSpace()), |
0 |
10897 |
DAG.getDataLayout().getAllocaAddrSpace()), |
0 |
| 10898 |
ValueVTs); |
--- |
10898 |
ValueVTs); |
--- |
| 10899 |
MVT VT = ValueVTs[0].getSimpleVT(); |
0 |
10899 |
MVT VT = ValueVTs[0].getSimpleVT(); |
0 |
| 10900 |
MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); |
0 |
10900 |
MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); |
0 |
| 10901 |
std::optional AssertOp; |
0 |
10901 |
std::optional AssertOp; |
0 |
| 10902 |
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, |
0 |
10902 |
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, |
0 |
| 10903 |
nullptr, F.getCallingConv(), AssertOp); |
0 |
10903 |
nullptr, F.getCallingConv(), AssertOp); |
0 |
| 10904 |
|
--- |
10904 |
|
--- |
| 10905 |
MachineFunction& MF = SDB->DAG.getMachineFunction(); |
0 |
10905 |
MachineFunction& MF = SDB->DAG.getMachineFunction(); |
0 |
| 10906 |
MachineRegisterInfo& RegInfo = MF.getRegInfo(); |
0 |
10906 |
MachineRegisterInfo& RegInfo = MF.getRegInfo(); |
0 |
| 10907 |
Register SRetReg = |
--- |
10907 |
Register SRetReg = |
--- |
| 10908 |
RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); |
0 |
10908 |
RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); |
0 |
| 10909 |
FuncInfo->DemoteRegister = SRetReg; |
0 |
10909 |
FuncInfo->DemoteRegister = SRetReg; |
0 |
| 10910 |
NewRoot = |
0 |
10910 |
NewRoot = |
0 |
| 10911 |
SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue); |
0 |
10911 |
SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue); |
0 |
| 10912 |
DAG.setRoot(NewRoot); |
0 |
10912 |
DAG.setRoot(NewRoot); |
0 |
| 10913 |
|
--- |
10913 |
|
--- |
| 10914 |
// i indexes lowered arguments. Bump it past the hidden sret argument. |
--- |
10914 |
// i indexes lowered arguments. Bump it past the hidden sret argument. |
--- |
| 10915 |
++i; |
0 |
10915 |
++i; |
0 |
| 10916 |
} |
0 |
10916 |
} |
0 |
| 10917 |
|
--- |
10917 |
|
--- |
| 10918 |
SmallVector Chains; |
1 |
10918 |
SmallVector Chains; |
1 |
| 10919 |
DenseMap ArgCopyElisionFrameIndexMap; |
1 |
10919 |
DenseMap ArgCopyElisionFrameIndexMap; |
1 |
| 10920 |
for (const Argument &Arg : F.args()) { |
3 |
10920 |
for (const Argument &Arg : F.args()) { |
3 |
| 10921 |
SmallVector ArgValues; |
2 |
10921 |
SmallVector ArgValues; |
2 |
| 10922 |
SmallVector ValueVTs; |
2 |
10922 |
SmallVector ValueVTs; |
2 |
| 10923 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); |
2 |
10923 |
ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); |
2 |
| 10924 |
unsigned NumValues = ValueVTs.size(); |
2 |
10924 |
unsigned NumValues = ValueVTs.size(); |
2 |
| 10925 |
if (NumValues == 0) |
2 |
10925 |
if (NumValues == 0) |
2 |
| 10926 |
continue; |
0 |
10926 |
continue; |
0 |
| 10927 |
|
--- |
10927 |
|
--- |
| 10928 |
bool ArgHasUses = !Arg.use_empty(); |
2 |
10928 |
bool ArgHasUses = !Arg.use_empty(); |
2 |
| 10929 |
|
--- |
10929 |
|
--- |
| 10930 |
// Elide the copying store if the target loaded this argument from a |
--- |
10930 |
// Elide the copying store if the target loaded this argument from a |
--- |
| 10931 |
// suitable fixed stack object. |
--- |
10931 |
// suitable fixed stack object. |
--- |
| 10932 |
if (Ins[i].Flags.isCopyElisionCandidate()) { |
2 |
10932 |
if (Ins[i].Flags.isCopyElisionCandidate()) { |
2 |
| 10933 |
unsigned NumParts = 0; |
2 |
10933 |
unsigned NumParts = 0; |
2 |
| 10934 |
for (EVT VT : ValueVTs) |
4 |
10934 |
for (EVT VT : ValueVTs) |
4 |
| 10935 |
NumParts += TLI->getNumRegistersForCallingConv(*CurDAG->getContext(), |
2 |
10935 |
NumParts += TLI->getNumRegistersForCallingConv(*CurDAG->getContext(), |
2 |
| 10936 |
F.getCallingConv(), VT); |
--- |
10936 |
F.getCallingConv(), VT); |
--- |
| 10937 |
|
--- |
10937 |
|
--- |
| 10938 |
tryToElideArgumentCopy(*FuncInfo, Chains, ArgCopyElisionFrameIndexMap, |
2 |
10938 |
tryToElideArgumentCopy(*FuncInfo, Chains, ArgCopyElisionFrameIndexMap, |
2 |
| 10939 |
ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg, |
--- |
10939 |
ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg, |
--- |
| 10940 |
ArrayRef(&InVals[i], NumParts), ArgHasUses); |
2 |
10940 |
ArrayRef(&InVals[i], NumParts), ArgHasUses); |
2 |
| 10941 |
} |
--- |
10941 |
} |
--- |
| 10942 |
|
--- |
10942 |
|
--- |
| 10943 |
// If this argument is unused then remember its value. It is used to generate |
--- |
10943 |
// If this argument is unused then remember its value. It is used to generate |
--- |
| 10944 |
// debugging information. |
--- |
10944 |
// debugging information. |
--- |
| 10945 |
bool isSwiftErrorArg = |
--- |
10945 |
bool isSwiftErrorArg = |
--- |
| 10946 |
TLI->supportSwiftError() && |
2 |
10946 |
TLI->supportSwiftError() && |
2 |
| 10947 |
Arg.hasAttribute(Attribute::SwiftError); |
0 |
10947 |
Arg.hasAttribute(Attribute::SwiftError); |
0 |
| 10948 |
if (!ArgHasUses && !isSwiftErrorArg) { |
2 |
10948 |
if (!ArgHasUses && !isSwiftErrorArg) { |
2 |
| 10949 |
SDB->setUnusedArgValue(&Arg, InVals[i]); |
0 |
10949 |
SDB->setUnusedArgValue(&Arg, InVals[i]); |
0 |
| 10950 |
|
--- |
10950 |
|
--- |
| 10951 |
// Also remember any frame index for use in FastISel. |
--- |
10951 |
// Also remember any frame index for use in FastISel. |
--- |
| 10952 |
if (FrameIndexSDNode *FI = |
0 |
10952 |
if (FrameIndexSDNode *FI = |
0 |
| 10953 |
dyn_cast(InVals[i].getNode())) |
0 |
10953 |
dyn_cast(InVals[i].getNode())) |
0 |
| 10954 |
FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); |
0 |
10954 |
FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); |
0 |
| 10955 |
} |
--- |
10955 |
} |
--- |
| 10956 |
|
--- |
10956 |
|
--- |
| 10957 |
for (unsigned Val = 0; Val != NumValues; ++Val) { |
4 |
10957 |
for (unsigned Val = 0; Val != NumValues; ++Val) { |
4 |
| 10958 |
EVT VT = ValueVTs[Val]; |
2 |
10958 |
EVT VT = ValueVTs[Val]; |
2 |
| 10959 |
MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), |
2 |
10959 |
MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), |
2 |
| 10960 |
F.getCallingConv(), VT); |
--- |
10960 |
F.getCallingConv(), VT); |
--- |
| 10961 |
unsigned NumParts = TLI->getNumRegistersForCallingConv( |
4 |
10961 |
unsigned NumParts = TLI->getNumRegistersForCallingConv( |
4 |
| 10962 |
*CurDAG->getContext(), F.getCallingConv(), VT); |
2 |
10962 |
*CurDAG->getContext(), F.getCallingConv(), VT); |
2 |
| 10963 |
|
--- |
10963 |
|
--- |
| 10964 |
// Even an apparent 'unused' swifterror argument needs to be returned. So |
--- |
10964 |
// Even an apparent 'unused' swifterror argument needs to be returned. So |
--- |
| 10965 |
// we do generate a copy for it that can be used on return from the |
--- |
10965 |
// we do generate a copy for it that can be used on return from the |
--- |
| 10966 |
// function. |
--- |
10966 |
// function. |
--- |
| 10967 |
if (ArgHasUses || isSwiftErrorArg) { |
2 |
10967 |
if (ArgHasUses || isSwiftErrorArg) { |
2 |
| 10968 |
std::optional AssertOp; |
2 |
10968 |
std::optional AssertOp; |
2 |
| 10969 |
if (Arg.hasAttribute(Attribute::SExt)) |
2 |
10969 |
if (Arg.hasAttribute(Attribute::SExt)) |
2 |
| 10970 |
AssertOp = ISD::AssertSext; |
2 |
10970 |
AssertOp = ISD::AssertSext; |
2 |
| 10971 |
else if (Arg.hasAttribute(Attribute::ZExt)) |
0 |
10971 |
else if (Arg.hasAttribute(Attribute::ZExt)) |
0 |
| 10972 |
AssertOp = ISD::AssertZext; |
0 |
10972 |
AssertOp = ISD::AssertZext; |
0 |
| 10973 |
|
--- |
10973 |
|
--- |
| 10974 |
ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts, |
2 |
10974 |
ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts, |
2 |
| 10975 |
PartVT, VT, nullptr, |
--- |
10975 |
PartVT, VT, nullptr, |
--- |
| 10976 |
F.getCallingConv(), AssertOp)); |
4 |
10976 |
F.getCallingConv(), AssertOp)); |
4 |
| 10977 |
} |
--- |
10977 |
} |
--- |
| 10978 |
|
--- |
10978 |
|
--- |
| 10979 |
i += NumParts; |
2 |
10979 |
i += NumParts; |
2 |
| 10980 |
} |
--- |
10980 |
} |
--- |
| 10981 |
|
--- |
10981 |
|
--- |
| 10982 |
// We don't need to do anything else for unused arguments. |
--- |
10982 |
// We don't need to do anything else for unused arguments. |
--- |
| 10983 |
if (ArgValues.empty()) |
2 |
10983 |
if (ArgValues.empty()) |
2 |
| 10984 |
continue; |
0 |
10984 |
continue; |
0 |
| 10985 |
|
--- |
10985 |
|
--- |
| 10986 |
// Note down frame index. |
--- |
10986 |
// Note down frame index. |
--- |
| 10987 |
if (FrameIndexSDNode *FI = |
2 |
10987 |
if (FrameIndexSDNode *FI = |
2 |
| 10988 |
dyn_cast(ArgValues[0].getNode())) |
2 |
10988 |
dyn_cast(ArgValues[0].getNode())) |
2 |
| 10989 |
FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); |
0 |
10989 |
FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); |
0 |
| 10990 |
|
--- |
10990 |
|
--- |
| 10991 |
SDValue Res = DAG.getMergeValues(ArrayRef(ArgValues.data(), NumValues), |
2 |
10991 |
SDValue Res = DAG.getMergeValues(ArrayRef(ArgValues.data(), NumValues), |
2 |
| 10992 |
SDB->getCurSDLoc()); |
4 |
10992 |
SDB->getCurSDLoc()); |
4 |
| 10993 |
|
--- |
10993 |
|
--- |
| 10994 |
SDB->setValue(&Arg, Res); |
2 |
10994 |
SDB->setValue(&Arg, Res); |
2 |
| 10995 |
if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { |
2 |
10995 |
if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { |
2 |
| 10996 |
// We want to associate the argument with the frame index, among |
--- |
10996 |
// We want to associate the argument with the frame index, among |
--- |
| 10997 |
// involved operands, that correspond to the lowest address. The |
--- |
10997 |
// involved operands, that correspond to the lowest address. The |
--- |
| 10998 |
// getCopyFromParts function, called earlier, is swapping the order of |
--- |
10998 |
// getCopyFromParts function, called earlier, is swapping the order of |
--- |
| 10999 |
// the operands to BUILD_PAIR depending on endianness. The result of |
--- |
10999 |
// the operands to BUILD_PAIR depending on endianness. The result of |
--- |
| 11000 |
// that swapping is that the least significant bits of the argument will |
--- |
11000 |
// that swapping is that the least significant bits of the argument will |
--- |
| 11001 |
// be in the first operand of the BUILD_PAIR node, and the most |
--- |
11001 |
// be in the first operand of the BUILD_PAIR node, and the most |
--- |
| 11002 |
// significant bits will be in the second operand. |
--- |
11002 |
// significant bits will be in the second operand. |
--- |
| 11003 |
unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0; |
0 |
11003 |
unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0; |
0 |
| 11004 |
if (LoadSDNode *LNode = |
0 |
11004 |
if (LoadSDNode *LNode = |
0 |
| 11005 |
dyn_cast(Res.getOperand(LowAddressOp).getNode())) |
0 |
11005 |
dyn_cast(Res.getOperand(LowAddressOp).getNode())) |
0 |
| 11006 |
if (FrameIndexSDNode *FI = |
0 |
11006 |
if (FrameIndexSDNode *FI = |
0 |
| 11007 |
dyn_cast(LNode->getBasePtr().getNode())) |
0 |
11007 |
dyn_cast(LNode->getBasePtr().getNode())) |
0 |
| 11008 |
FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); |
0 |
11008 |
FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); |
0 |
| 11009 |
} |
--- |
11009 |
} |
--- |
| 11010 |
|
--- |
11010 |
|
--- |
| 11011 |
// Analyses past this point are naive and don't expect an assertion. |
--- |
11011 |
// Analyses past this point are naive and don't expect an assertion. |
--- |
| 11012 |
if (Res.getOpcode() == ISD::AssertZext) |
2 |
11012 |
if (Res.getOpcode() == ISD::AssertZext) |
2 |
| 11013 |
Res = Res.getOperand(0); |
0 |
11013 |
Res = Res.getOperand(0); |
0 |
| 11014 |
|
--- |
11014 |
|
--- |
| 11015 |
// Update the SwiftErrorVRegDefMap. |
--- |
11015 |
// Update the SwiftErrorVRegDefMap. |
--- |
| 11016 |
if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { |
2 |
11016 |
if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { |
2 |
| 11017 |
unsigned Reg = cast(Res.getOperand(1))->getReg(); |
0 |
11017 |
unsigned Reg = cast(Res.getOperand(1))->getReg(); |
0 |
| 11018 |
if (Register::isVirtualRegister(Reg)) |
0 |
11018 |
if (Register::isVirtualRegister(Reg)) |
0 |
| 11019 |
SwiftError->setCurrentVReg(FuncInfo->MBB, SwiftError->getFunctionArg(), |
0 |
11019 |
SwiftError->setCurrentVReg(FuncInfo->MBB, SwiftError->getFunctionArg(), |
0 |
| 11020 |
Reg); |
--- |
11020 |
Reg); |
--- |
| 11021 |
} |
--- |
11021 |
} |
--- |
| 11022 |
|
--- |
11022 |
|
--- |
| 11023 |
// If this argument is live outside of the entry block, insert a copy from |
--- |
11023 |
// If this argument is live outside of the entry block, insert a copy from |
--- |
| 11024 |
// wherever we got it to the vreg that other BB's will reference it as. |
--- |
11024 |
// wherever we got it to the vreg that other BB's will reference it as. |
--- |
| 11025 |
if (Res.getOpcode() == ISD::CopyFromReg) { |
2 |
11025 |
if (Res.getOpcode() == ISD::CopyFromReg) { |
2 |
| 11026 |
// If we can, though, try to skip creating an unnecessary vreg. |
--- |
11026 |
// If we can, though, try to skip creating an unnecessary vreg. |
--- |
| 11027 |
// FIXME: This isn't very clean... it would be nice to make this more |
--- |
11027 |
// FIXME: This isn't very clean... it would be nice to make this more |
--- |
| 11028 |
// general. |
--- |
11028 |
// general. |
--- |
| 11029 |
unsigned Reg = cast(Res.getOperand(1))->getReg(); |
2 |
11029 |
unsigned Reg = cast(Res.getOperand(1))->getReg(); |
2 |
| 11030 |
if (Register::isVirtualRegister(Reg)) { |
2 |
11030 |
if (Register::isVirtualRegister(Reg)) { |
2 |
| 11031 |
FuncInfo->ValueMap[&Arg] = Reg; |
2 |
11031 |
FuncInfo->ValueMap[&Arg] = Reg; |
2 |
| 11032 |
continue; |
2 |
11032 |
continue; |
2 |
| 11033 |
} |
--- |
11033 |
} |
--- |
| 11034 |
} |
--- |
11034 |
} |
--- |
| 11035 |
if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) { |
0 |
11035 |
if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) { |
0 |
| 11036 |
FuncInfo->InitializeRegForValue(&Arg); |
0 |
11036 |
FuncInfo->InitializeRegForValue(&Arg); |
0 |
| 11037 |
SDB->CopyToExportRegsIfNeeded(&Arg); |
0 |
11037 |
SDB->CopyToExportRegsIfNeeded(&Arg); |
0 |
| 11038 |
} |
--- |
11038 |
} |
--- |
| 11039 |
} |
4 |
11039 |
} |
4 |
| 11040 |
|
--- |
11040 |
|
--- |
| 11041 |
if (!Chains.empty()) { |
1 |
11041 |
if (!Chains.empty()) { |
1 |
| 11042 |
Chains.push_back(NewRoot); |
0 |
11042 |
Chains.push_back(NewRoot); |
0 |
| 11043 |
NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); |
0 |
11043 |
NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); |
0 |
| 11044 |
} |
--- |
11044 |
} |
--- |
| 11045 |
|
--- |
11045 |
|
--- |
| 11046 |
DAG.setRoot(NewRoot); |
1 |
11046 |
DAG.setRoot(NewRoot); |
1 |
| 11047 |
|
--- |
11047 |
|
--- |
| 11048 |
assert(i == InVals.size() && "Argument register count mismatch!"); |
1 |
11048 |
assert(i == InVals.size() && "Argument register count mismatch!"); |
1 |
| 11049 |
|
--- |
11049 |
|
--- |
| 11050 |
// If any argument copy elisions occurred and we have debug info, update the |
--- |
11050 |
// If any argument copy elisions occurred and we have debug info, update the |
--- |
| 11051 |
// stale frame indices used in the dbg.declare variable info table. |
--- |
11051 |
// stale frame indices used in the dbg.declare variable info table. |
--- |
| 11052 |
if (!ArgCopyElisionFrameIndexMap.empty()) { |
1 |
11052 |
if (!ArgCopyElisionFrameIndexMap.empty()) { |
1 |
| 11053 |
for (MachineFunction::VariableDbgInfo &VI : |
0 |
11053 |
for (MachineFunction::VariableDbgInfo &VI : |
0 |
| 11054 |
MF->getInStackSlotVariableDbgInfo()) { |
0 |
11054 |
MF->getInStackSlotVariableDbgInfo()) { |
0 |
| 11055 |
auto I = ArgCopyElisionFrameIndexMap.find(VI.getStackSlot()); |
0 |
11055 |
auto I = ArgCopyElisionFrameIndexMap.find(VI.getStackSlot()); |
0 |
| 11056 |
if (I != ArgCopyElisionFrameIndexMap.end()) |
0 |
11056 |
if (I != ArgCopyElisionFrameIndexMap.end()) |
0 |
| 11057 |
VI.updateStackSlot(I->second); |
0 |
11057 |
VI.updateStackSlot(I->second); |
0 |
| 11058 |
} |
--- |
11058 |
} |
--- |
| 11059 |
} |
--- |
11059 |
} |
--- |
| 11060 |
|
--- |
11060 |
|
--- |
| 11061 |
// Finally, if the target has anything special to do, allow it to do so. |
--- |
11061 |
// Finally, if the target has anything special to do, allow it to do so. |
--- |
| 11062 |
emitFunctionEntryCode(); |
1 |
11062 |
emitFunctionEntryCode(); |
1 |
| 11063 |
} |
1 |
11063 |
} |
1 |
| 11064 |
|
--- |
11064 |
|
--- |
| 11065 |
/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to |
--- |
11065 |
/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to |
--- |
| 11066 |
/// ensure constants are generated when needed. Remember the virtual registers |
--- |
11066 |
/// ensure constants are generated when needed. Remember the virtual registers |
--- |
| 11067 |
/// that need to be added to the Machine PHI nodes as input. We cannot just |
--- |
11067 |
/// that need to be added to the Machine PHI nodes as input. We cannot just |
--- |
| 11068 |
/// directly add them, because expansion might result in multiple MBB's for one |
--- |
11068 |
/// directly add them, because expansion might result in multiple MBB's for one |
--- |
| 11069 |
/// BB. As such, the start of the BB might correspond to a different MBB than |
--- |
11069 |
/// BB. As such, the start of the BB might correspond to a different MBB than |
--- |
| 11070 |
/// the end. |
--- |
11070 |
/// the end. |
--- |
| 11071 |
void |
--- |
11071 |
void |
--- |
| 11072 |
SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { |
4 |
11072 |
SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { |
4 |
| 11073 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
4 |
11073 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
4 |
| 11074 |
|
--- |
11074 |
|
--- |
| 11075 |
SmallPtrSet SuccsHandled; |
4 |
11075 |
SmallPtrSet SuccsHandled; |
4 |
| 11076 |
|
--- |
11076 |
|
--- |
| 11077 |
// Check PHI nodes in successors that expect a value to be available from this |
--- |
11077 |
// Check PHI nodes in successors that expect a value to be available from this |
--- |
| 11078 |
// block. |
--- |
11078 |
// block. |
--- |
| 11079 |
for (const BasicBlock *SuccBB : successors(LLVMBB->getTerminator())) { |
8 |
11079 |
for (const BasicBlock *SuccBB : successors(LLVMBB->getTerminator())) { |
8 |
| 11080 |
if (!isa(SuccBB->begin())) continue; |
4 |
11080 |
if (!isa(SuccBB->begin())) continue; |
4 |
| 11081 |
MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; |
0 |
11081 |
MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; |
0 |
| 11082 |
|
--- |
11082 |
|
--- |
| 11083 |
// If this terminator has multiple identical successors (common for |
--- |
11083 |
// If this terminator has multiple identical successors (common for |
--- |
| 11084 |
// switches), only handle each succ once. |
--- |
11084 |
// switches), only handle each succ once. |
--- |
| 11085 |
if (!SuccsHandled.insert(SuccMBB).second) |
0 |
11085 |
if (!SuccsHandled.insert(SuccMBB).second) |
0 |
| 11086 |
continue; |
0 |
11086 |
continue; |
0 |
| 11087 |
|
--- |
11087 |
|
--- |
| 11088 |
MachineBasicBlock::iterator MBBI = SuccMBB->begin(); |
0 |
11088 |
MachineBasicBlock::iterator MBBI = SuccMBB->begin(); |
0 |
| 11089 |
|
--- |
11089 |
|
--- |
| 11090 |
// At this point we know that there is a 1-1 correspondence between LLVM PHI |
--- |
11090 |
// At this point we know that there is a 1-1 correspondence between LLVM PHI |
--- |
| 11091 |
// nodes and Machine PHI nodes, but the incoming operands have not been |
--- |
11091 |
// nodes and Machine PHI nodes, but the incoming operands have not been |
--- |
| 11092 |
// emitted yet. |
--- |
11092 |
// emitted yet. |
--- |
| 11093 |
for (const PHINode &PN : SuccBB->phis()) { |
0 |
11093 |
for (const PHINode &PN : SuccBB->phis()) { |
0 |
| 11094 |
// Ignore dead phi's. |
--- |
11094 |
// Ignore dead phi's. |
--- |
| 11095 |
if (PN.use_empty()) |
0 |
11095 |
if (PN.use_empty()) |
0 |
| 11096 |
continue; |
0 |
11096 |
continue; |
0 |
| 11097 |
|
--- |
11097 |
|
--- |
| 11098 |
// Skip empty types |
--- |
11098 |
// Skip empty types |
--- |
| 11099 |
if (PN.getType()->isEmptyTy()) |
0 |
11099 |
if (PN.getType()->isEmptyTy()) |
0 |
| 11100 |
continue; |
0 |
11100 |
continue; |
0 |
| 11101 |
|
--- |
11101 |
|
--- |
| 11102 |
unsigned Reg; |
--- |
11102 |
unsigned Reg; |
--- |
| 11103 |
const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB); |
0 |
11103 |
const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB); |
0 |
| 11104 |
|
--- |
11104 |
|
--- |
| 11105 |
if (const auto *C = dyn_cast(PHIOp)) { |
0 |
11105 |
if (const auto *C = dyn_cast(PHIOp)) { |
0 |
| 11106 |
unsigned &RegOut = ConstantsOut[C]; |
0 |
11106 |
unsigned &RegOut = ConstantsOut[C]; |
0 |
| 11107 |
if (RegOut == 0) { |
0 |
11107 |
if (RegOut == 0) { |
0 |
| 11108 |
RegOut = FuncInfo.CreateRegs(C); |
0 |
11108 |
RegOut = FuncInfo.CreateRegs(C); |
0 |
| 11109 |
// We need to zero/sign extend ConstantInt phi operands to match |
--- |
11109 |
// We need to zero/sign extend ConstantInt phi operands to match |
--- |
| 11110 |
// assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo. |
--- |
11110 |
// assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo. |
--- |
| 11111 |
ISD::NodeType ExtendType = ISD::ANY_EXTEND; |
0 |
11111 |
ISD::NodeType ExtendType = ISD::ANY_EXTEND; |
0 |
| 11112 |
if (auto *CI = dyn_cast(C)) |
0 |
11112 |
if (auto *CI = dyn_cast(C)) |
0 |
| 11113 |
ExtendType = TLI.signExtendConstant(CI) ? ISD::SIGN_EXTEND |
0 |
11113 |
ExtendType = TLI.signExtendConstant(CI) ? ISD::SIGN_EXTEND |
0 |
| 11114 |
: ISD::ZERO_EXTEND; |
--- |
11114 |
: ISD::ZERO_EXTEND; |
--- |
| 11115 |
CopyValueToVirtualRegister(C, RegOut, ExtendType); |
0 |
11115 |
CopyValueToVirtualRegister(C, RegOut, ExtendType); |
0 |
| 11116 |
} |
--- |
11116 |
} |
--- |
| 11117 |
Reg = RegOut; |
0 |
11117 |
Reg = RegOut; |
0 |
| 11118 |
} else { |
--- |
11118 |
} else { |
--- |
| 11119 |
DenseMap::iterator I = |
--- |
11119 |
DenseMap::iterator I = |
--- |
| 11120 |
FuncInfo.ValueMap.find(PHIOp); |
0 |
11120 |
FuncInfo.ValueMap.find(PHIOp); |
0 |
| 11121 |
if (I != FuncInfo.ValueMap.end()) |
0 |
11121 |
if (I != FuncInfo.ValueMap.end()) |
0 |
| 11122 |
Reg = I->second; |
0 |
11122 |
Reg = I->second; |
0 |
| 11123 |
else { |
--- |
11123 |
else { |
--- |
| 11124 |
assert(isa(PHIOp) && |
0 |
11124 |
assert(isa(PHIOp) && |
0 |
| 11125 |
FuncInfo.StaticAllocaMap.count(cast(PHIOp)) && |
--- |
11125 |
FuncInfo.StaticAllocaMap.count(cast(PHIOp)) && |
--- |
| 11126 |
"Didn't codegen value into a register!??"); |
--- |
11126 |
"Didn't codegen value into a register!??"); |
--- |
| 11127 |
Reg = FuncInfo.CreateRegs(PHIOp); |
0 |
11127 |
Reg = FuncInfo.CreateRegs(PHIOp); |
0 |
| 11128 |
CopyValueToVirtualRegister(PHIOp, Reg); |
0 |
11128 |
CopyValueToVirtualRegister(PHIOp, Reg); |
0 |
| 11129 |
} |
--- |
11129 |
} |
--- |
| 11130 |
} |
--- |
11130 |
} |
--- |
| 11131 |
|
--- |
11131 |
|
--- |
| 11132 |
// Remember that this register needs to added to the machine PHI node as |
--- |
11132 |
// Remember that this register needs to added to the machine PHI node as |
--- |
| 11133 |
// the input for this MBB. |
--- |
11133 |
// the input for this MBB. |
--- |
| 11134 |
SmallVector ValueVTs; |
0 |
11134 |
SmallVector ValueVTs; |
0 |
| 11135 |
ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs); |
0 |
11135 |
ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs); |
0 |
| 11136 |
for (EVT VT : ValueVTs) { |
0 |
11136 |
for (EVT VT : ValueVTs) { |
0 |
| 11137 |
const unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); |
0 |
11137 |
const unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); |
0 |
| 11138 |
for (unsigned i = 0; i != NumRegisters; ++i) |
0 |
11138 |
for (unsigned i = 0; i != NumRegisters; ++i) |
0 |
| 11139 |
FuncInfo.PHINodesToUpdate.push_back( |
0 |
11139 |
FuncInfo.PHINodesToUpdate.push_back( |
0 |
| 11140 |
std::make_pair(&*MBBI++, Reg + i)); |
0 |
11140 |
std::make_pair(&*MBBI++, Reg + i)); |
0 |
| 11141 |
Reg += NumRegisters; |
0 |
11141 |
Reg += NumRegisters; |
0 |
| 11142 |
} |
--- |
11142 |
} |
--- |
| 11143 |
} |
0 |
11143 |
} |
0 |
| 11144 |
} |
--- |
11144 |
} |
--- |
| 11145 |
|
--- |
11145 |
|
--- |
| 11146 |
ConstantsOut.clear(); |
4 |
11146 |
ConstantsOut.clear(); |
4 |
| 11147 |
} |
4 |
11147 |
} |
4 |
| 11148 |
|
--- |
11148 |
|
--- |
| 11149 |
MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) { |
3 |
11149 |
MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) { |
3 |
| 11150 |
MachineFunction::iterator I(MBB); |
3 |
11150 |
MachineFunction::iterator I(MBB); |
3 |
| 11151 |
if (++I == FuncInfo.MF->end()) |
3 |
11151 |
if (++I == FuncInfo.MF->end()) |
3 |
| 11152 |
return nullptr; |
0 |
11152 |
return nullptr; |
0 |
| 11153 |
return &*I; |
3 |
11153 |
return &*I; |
3 |
| 11154 |
} |
--- |
11154 |
} |
--- |
| 11155 |
|
--- |
11155 |
|
--- |
| 11156 |
/// During lowering new call nodes can be created (such as memset, etc.). |
--- |
11156 |
/// During lowering new call nodes can be created (such as memset, etc.). |
--- |
| 11157 |
/// Those will become new roots of the current DAG, but complications arise |
--- |
11157 |
/// Those will become new roots of the current DAG, but complications arise |
--- |
| 11158 |
/// when they are tail calls. In such cases, the call lowering will update |
--- |
11158 |
/// when they are tail calls. In such cases, the call lowering will update |
--- |
| 11159 |
/// the root, but the builder still needs to know that a tail call has been |
--- |
11159 |
/// the root, but the builder still needs to know that a tail call has been |
--- |
| 11160 |
/// lowered in order to avoid generating an additional return. |
--- |
11160 |
/// lowered in order to avoid generating an additional return. |
--- |
| 11161 |
void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) { |
0 |
11161 |
void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) { |
0 |
| 11162 |
// If the node is null, we do have a tail call. |
--- |
11162 |
// If the node is null, we do have a tail call. |
--- |
| 11163 |
if (MaybeTC.getNode() != nullptr) |
0 |
11163 |
if (MaybeTC.getNode() != nullptr) |
0 |
| 11164 |
DAG.setRoot(MaybeTC); |
0 |
11164 |
DAG.setRoot(MaybeTC); |
0 |
| 11165 |
else |
--- |
11165 |
else |
--- |
| 11166 |
HasTailCall = true; |
0 |
11166 |
HasTailCall = true; |
0 |
| 11167 |
} |
0 |
11167 |
} |
0 |
| 11168 |
|
--- |
11168 |
|
--- |
| 11169 |
void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, |
0 |
11169 |
void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, |
0 |
| 11170 |
MachineBasicBlock *SwitchMBB, |
--- |
11170 |
MachineBasicBlock *SwitchMBB, |
--- |
| 11171 |
MachineBasicBlock *DefaultMBB) { |
--- |
11171 |
MachineBasicBlock *DefaultMBB) { |
--- |
| 11172 |
MachineFunction *CurMF = FuncInfo.MF; |
0 |
11172 |
MachineFunction *CurMF = FuncInfo.MF; |
0 |
| 11173 |
MachineBasicBlock *NextMBB = nullptr; |
0 |
11173 |
MachineBasicBlock *NextMBB = nullptr; |
0 |
| 11174 |
MachineFunction::iterator BBI(W.MBB); |
0 |
11174 |
MachineFunction::iterator BBI(W.MBB); |
0 |
| 11175 |
if (++BBI != FuncInfo.MF->end()) |
0 |
11175 |
if (++BBI != FuncInfo.MF->end()) |
0 |
| 11176 |
NextMBB = &*BBI; |
0 |
11176 |
NextMBB = &*BBI; |
0 |
| 11177 |
|
--- |
11177 |
|
--- |
| 11178 |
unsigned Size = W.LastCluster - W.FirstCluster + 1; |
0 |
11178 |
unsigned Size = W.LastCluster - W.FirstCluster + 1; |
0 |
| 11179 |
|
--- |
11179 |
|
--- |
| 11180 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
11180 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
| 11181 |
|
--- |
11181 |
|
--- |
| 11182 |
if (Size == 2 && W.MBB == SwitchMBB) { |
0 |
11182 |
if (Size == 2 && W.MBB == SwitchMBB) { |
0 |
| 11183 |
// If any two of the cases has the same destination, and if one value |
--- |
11183 |
// If any two of the cases has the same destination, and if one value |
--- |
| 11184 |
// is the same as the other, but has one bit unset that the other has set, |
--- |
11184 |
// is the same as the other, but has one bit unset that the other has set, |
--- |
| 11185 |
// use bit manipulation to do two compares at once. For example: |
--- |
11185 |
// use bit manipulation to do two compares at once. For example: |
--- |
| 11186 |
// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" |
--- |
11186 |
// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" |
--- |
| 11187 |
// TODO: This could be extended to merge any 2 cases in switches with 3 |
--- |
11187 |
// TODO: This could be extended to merge any 2 cases in switches with 3 |
--- |
| 11188 |
// cases. |
--- |
11188 |
// cases. |
--- |
| 11189 |
// TODO: Handle cases where W.CaseBB != SwitchBB. |
--- |
11189 |
// TODO: Handle cases where W.CaseBB != SwitchBB. |
--- |
| 11190 |
CaseCluster &Small = *W.FirstCluster; |
0 |
11190 |
CaseCluster &Small = *W.FirstCluster; |
0 |
| 11191 |
CaseCluster &Big = *W.LastCluster; |
0 |
11191 |
CaseCluster &Big = *W.LastCluster; |
0 |
| 11192 |
|
--- |
11192 |
|
--- |
| 11193 |
if (Small.Low == Small.High && Big.Low == Big.High && |
0 |
11193 |
if (Small.Low == Small.High && Big.Low == Big.High && |
0 |
| 11194 |
Small.MBB == Big.MBB) { |
0 |
11194 |
Small.MBB == Big.MBB) { |
0 |
| 11195 |
const APInt &SmallValue = Small.Low->getValue(); |
0 |
11195 |
const APInt &SmallValue = Small.Low->getValue(); |
0 |
| 11196 |
const APInt &BigValue = Big.Low->getValue(); |
0 |
11196 |
const APInt &BigValue = Big.Low->getValue(); |
0 |
| 11197 |
|
--- |
11197 |
|
--- |
| 11198 |
// Check that there is only one bit different. |
--- |
11198 |
// Check that there is only one bit different. |
--- |
| 11199 |
APInt CommonBit = BigValue ^ SmallValue; |
0 |
11199 |
APInt CommonBit = BigValue ^ SmallValue; |
0 |
| 11200 |
if (CommonBit.isPowerOf2()) { |
0 |
11200 |
if (CommonBit.isPowerOf2()) { |
0 |
| 11201 |
SDValue CondLHS = getValue(Cond); |
0 |
11201 |
SDValue CondLHS = getValue(Cond); |
0 |
| 11202 |
EVT VT = CondLHS.getValueType(); |
0 |
11202 |
EVT VT = CondLHS.getValueType(); |
0 |
| 11203 |
SDLoc DL = getCurSDLoc(); |
0 |
11203 |
SDLoc DL = getCurSDLoc(); |
0 |
| 11204 |
|
--- |
11204 |
|
--- |
| 11205 |
SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, |
0 |
11205 |
SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, |
0 |
| 11206 |
DAG.getConstant(CommonBit, DL, VT)); |
0 |
11206 |
DAG.getConstant(CommonBit, DL, VT)); |
0 |
| 11207 |
SDValue Cond = DAG.getSetCC( |
0 |
11207 |
SDValue Cond = DAG.getSetCC( |
0 |
| 11208 |
DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT), |
0 |
11208 |
DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT), |
0 |
| 11209 |
ISD::SETEQ); |
--- |
11209 |
ISD::SETEQ); |
--- |
| 11210 |
|
--- |
11210 |
|
--- |
| 11211 |
// Update successor info. |
--- |
11211 |
// Update successor info. |
--- |
| 11212 |
// Both Small and Big will jump to Small.BB, so we sum up the |
--- |
11212 |
// Both Small and Big will jump to Small.BB, so we sum up the |
--- |
| 11213 |
// probabilities. |
--- |
11213 |
// probabilities. |
--- |
| 11214 |
addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob); |
0 |
11214 |
addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob); |
0 |
| 11215 |
if (BPI) |
0 |
11215 |
if (BPI) |
0 |
| 11216 |
addSuccessorWithProb( |
0 |
11216 |
addSuccessorWithProb( |
0 |
| 11217 |
SwitchMBB, DefaultMBB, |
--- |
11217 |
SwitchMBB, DefaultMBB, |
--- |
| 11218 |
// The default destination is the first successor in IR. |
--- |
11218 |
// The default destination is the first successor in IR. |
--- |
| 11219 |
BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0)); |
--- |
11219 |
BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0)); |
--- |
| 11220 |
else |
--- |
11220 |
else |
--- |
| 11221 |
addSuccessorWithProb(SwitchMBB, DefaultMBB); |
0 |
11221 |
addSuccessorWithProb(SwitchMBB, DefaultMBB); |
0 |
| 11222 |
|
--- |
11222 |
|
--- |
| 11223 |
// Insert the true branch. |
--- |
11223 |
// Insert the true branch. |
--- |
| 11224 |
SDValue BrCond = |
--- |
11224 |
SDValue BrCond = |
--- |
| 11225 |
DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond, |
0 |
11225 |
DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond, |
0 |
| 11226 |
DAG.getBasicBlock(Small.MBB)); |
0 |
11226 |
DAG.getBasicBlock(Small.MBB)); |
0 |
| 11227 |
// Insert the false branch. |
--- |
11227 |
// Insert the false branch. |
--- |
| 11228 |
BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, |
0 |
11228 |
BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, |
0 |
| 11229 |
DAG.getBasicBlock(DefaultMBB)); |
0 |
11229 |
DAG.getBasicBlock(DefaultMBB)); |
0 |
| 11230 |
|
--- |
11230 |
|
--- |
| 11231 |
DAG.setRoot(BrCond); |
0 |
11231 |
DAG.setRoot(BrCond); |
0 |
| 11232 |
return; |
0 |
11232 |
return; |
0 |
| 11233 |
} |
0 |
11233 |
} |
0 |
| 11234 |
} |
0 |
11234 |
} |
0 |
| 11235 |
} |
--- |
11235 |
} |
--- |
| 11236 |
|
--- |
11236 |
|
--- |
| 11237 |
if (TM.getOptLevel() != CodeGenOpt::None) { |
0 |
11237 |
if (TM.getOptLevel() != CodeGenOpt::None) { |
0 |
| 11238 |
// Here, we order cases by probability so the most likely case will be |
--- |
11238 |
// Here, we order cases by probability so the most likely case will be |
--- |
| 11239 |
// checked first. However, two clusters can have the same probability in |
--- |
11239 |
// checked first. However, two clusters can have the same probability in |
--- |
| 11240 |
// which case their relative ordering is non-deterministic. So we use Low |
--- |
11240 |
// which case their relative ordering is non-deterministic. So we use Low |
--- |
| 11241 |
// as a tie-breaker as clusters are guaranteed to never overlap. |
--- |
11241 |
// as a tie-breaker as clusters are guaranteed to never overlap. |
--- |
| 11242 |
llvm::sort(W.FirstCluster, W.LastCluster + 1, |
0 |
11242 |
llvm::sort(W.FirstCluster, W.LastCluster + 1, |
0 |
| 11243 |
[](const CaseCluster &a, const CaseCluster &b) { |
0 |
11243 |
[](const CaseCluster &a, const CaseCluster &b) { |
0 |
| 11244 |
return a.Prob != b.Prob ? |
0 |
11244 |
return a.Prob != b.Prob ? |
0 |
| 11245 |
a.Prob > b.Prob : |
0 |
11245 |
a.Prob > b.Prob : |
0 |
| 11246 |
a.Low->getValue().slt(b.Low->getValue()); |
0 |
11246 |
a.Low->getValue().slt(b.Low->getValue()); |
0 |
| 11247 |
}); |
--- |
11247 |
}); |
--- |
| 11248 |
|
--- |
11248 |
|
--- |
| 11249 |
// Rearrange the case blocks so that the last one falls through if possible |
--- |
11249 |
// Rearrange the case blocks so that the last one falls through if possible |
--- |
| 11250 |
// without changing the order of probabilities. |
--- |
11250 |
// without changing the order of probabilities. |
--- |
| 11251 |
for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) { |
0 |
11251 |
for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) { |
0 |
| 11252 |
--I; |
0 |
11252 |
--I; |
0 |
| 11253 |
if (I->Prob > W.LastCluster->Prob) |
0 |
11253 |
if (I->Prob > W.LastCluster->Prob) |
0 |
| 11254 |
break; |
0 |
11254 |
break; |
0 |
| 11255 |
if (I->Kind == CC_Range && I->MBB == NextMBB) { |
0 |
11255 |
if (I->Kind == CC_Range && I->MBB == NextMBB) { |
0 |
| 11256 |
std::swap(*I, *W.LastCluster); |
0 |
11256 |
std::swap(*I, *W.LastCluster); |
0 |
| 11257 |
break; |
0 |
11257 |
break; |
0 |
| 11258 |
} |
--- |
11258 |
} |
--- |
| 11259 |
} |
--- |
11259 |
} |
--- |
| 11260 |
} |
--- |
11260 |
} |
--- |
| 11261 |
|
--- |
11261 |
|
--- |
| 11262 |
// Compute total probability. |
--- |
11262 |
// Compute total probability. |
--- |
| 11263 |
BranchProbability DefaultProb = W.DefaultProb; |
0 |
11263 |
BranchProbability DefaultProb = W.DefaultProb; |
0 |
| 11264 |
BranchProbability UnhandledProbs = DefaultProb; |
0 |
11264 |
BranchProbability UnhandledProbs = DefaultProb; |
0 |
| 11265 |
for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) |
0 |
11265 |
for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) |
0 |
| 11266 |
UnhandledProbs += I->Prob; |
0 |
11266 |
UnhandledProbs += I->Prob; |
0 |
| 11267 |
|
--- |
11267 |
|
--- |
| 11268 |
MachineBasicBlock *CurMBB = W.MBB; |
0 |
11268 |
MachineBasicBlock *CurMBB = W.MBB; |
0 |
| 11269 |
for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) { |
0 |
11269 |
for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) { |
0 |
| 11270 |
bool FallthroughUnreachable = false; |
0 |
11270 |
bool FallthroughUnreachable = false; |
0 |
| 11271 |
MachineBasicBlock *Fallthrough; |
--- |
11271 |
MachineBasicBlock *Fallthrough; |
--- |
| 11272 |
if (I == W.LastCluster) { |
0 |
11272 |
if (I == W.LastCluster) { |
0 |
| 11273 |
// For the last cluster, fall through to the default destination. |
--- |
11273 |
// For the last cluster, fall through to the default destination. |
--- |
| 11274 |
Fallthrough = DefaultMBB; |
0 |
11274 |
Fallthrough = DefaultMBB; |
0 |
| 11275 |
FallthroughUnreachable = isa( |
0 |
11275 |
FallthroughUnreachable = isa( |
0 |
| 11276 |
DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg()); |
0 |
11276 |
DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg()); |
0 |
| 11277 |
} else { |
--- |
11277 |
} else { |
--- |
| 11278 |
Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock()); |
0 |
11278 |
Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock()); |
0 |
| 11279 |
CurMF->insert(BBI, Fallthrough); |
0 |
11279 |
CurMF->insert(BBI, Fallthrough); |
0 |
| 11280 |
// Put Cond in a virtual register to make it available from the new blocks. |
--- |
11280 |
// Put Cond in a virtual register to make it available from the new blocks. |
--- |
| 11281 |
ExportFromCurrentBlock(Cond); |
0 |
11281 |
ExportFromCurrentBlock(Cond); |
0 |
| 11282 |
} |
--- |
11282 |
} |
--- |
| 11283 |
UnhandledProbs -= I->Prob; |
0 |
11283 |
UnhandledProbs -= I->Prob; |
0 |
| 11284 |
|
--- |
11284 |
|
--- |
| 11285 |
switch (I->Kind) { |
0 |
11285 |
switch (I->Kind) { |
0 |
| 11286 |
case CC_JumpTable: { |
0 |
11286 |
case CC_JumpTable: { |
0 |
| 11287 |
// FIXME: Optimize away range check based on pivot comparisons. |
--- |
11287 |
// FIXME: Optimize away range check based on pivot comparisons. |
--- |
| 11288 |
JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first; |
0 |
11288 |
JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first; |
0 |
| 11289 |
SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second; |
0 |
11289 |
SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second; |
0 |
| 11290 |
|
--- |
11290 |
|
--- |
| 11291 |
// The jump block hasn't been inserted yet; insert it here. |
--- |
11291 |
// The jump block hasn't been inserted yet; insert it here. |
--- |
| 11292 |
MachineBasicBlock *JumpMBB = JT->MBB; |
0 |
11292 |
MachineBasicBlock *JumpMBB = JT->MBB; |
0 |
| 11293 |
CurMF->insert(BBI, JumpMBB); |
0 |
11293 |
CurMF->insert(BBI, JumpMBB); |
0 |
| 11294 |
|
--- |
11294 |
|
--- |
| 11295 |
auto JumpProb = I->Prob; |
0 |
11295 |
auto JumpProb = I->Prob; |
0 |
| 11296 |
auto FallthroughProb = UnhandledProbs; |
0 |
11296 |
auto FallthroughProb = UnhandledProbs; |
0 |
| 11297 |
|
--- |
11297 |
|
--- |
| 11298 |
// If the default statement is a target of the jump table, we evenly |
--- |
11298 |
// If the default statement is a target of the jump table, we evenly |
--- |
| 11299 |
// distribute the default probability to successors of CurMBB. Also |
--- |
11299 |
// distribute the default probability to successors of CurMBB. Also |
--- |
| 11300 |
// update the probability on the edge from JumpMBB to Fallthrough. |
--- |
11300 |
// update the probability on the edge from JumpMBB to Fallthrough. |
--- |
| 11301 |
for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(), |
0 |
11301 |
for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(), |
0 |
| 11302 |
SE = JumpMBB->succ_end(); |
0 |
11302 |
SE = JumpMBB->succ_end(); |
0 |
| 11303 |
SI != SE; ++SI) { |
0 |
11303 |
SI != SE; ++SI) { |
0 |
| 11304 |
if (*SI == DefaultMBB) { |
0 |
11304 |
if (*SI == DefaultMBB) { |
0 |
| 11305 |
JumpProb += DefaultProb / 2; |
0 |
11305 |
JumpProb += DefaultProb / 2; |
0 |
| 11306 |
FallthroughProb -= DefaultProb / 2; |
0 |
11306 |
FallthroughProb -= DefaultProb / 2; |
0 |
| 11307 |
JumpMBB->setSuccProbability(SI, DefaultProb / 2); |
0 |
11307 |
JumpMBB->setSuccProbability(SI, DefaultProb / 2); |
0 |
| 11308 |
JumpMBB->normalizeSuccProbs(); |
0 |
11308 |
JumpMBB->normalizeSuccProbs(); |
0 |
| 11309 |
break; |
0 |
11309 |
break; |
0 |
| 11310 |
} |
--- |
11310 |
} |
--- |
| 11311 |
} |
--- |
11311 |
} |
--- |
| 11312 |
|
--- |
11312 |
|
--- |
| 11313 |
if (FallthroughUnreachable) |
0 |
11313 |
if (FallthroughUnreachable) |
0 |
| 11314 |
JTH->FallthroughUnreachable = true; |
0 |
11314 |
JTH->FallthroughUnreachable = true; |
0 |
| 11315 |
|
--- |
11315 |
|
--- |
| 11316 |
if (!JTH->FallthroughUnreachable) |
0 |
11316 |
if (!JTH->FallthroughUnreachable) |
0 |
| 11317 |
addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb); |
0 |
11317 |
addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb); |
0 |
| 11318 |
addSuccessorWithProb(CurMBB, JumpMBB, JumpProb); |
0 |
11318 |
addSuccessorWithProb(CurMBB, JumpMBB, JumpProb); |
0 |
| 11319 |
CurMBB->normalizeSuccProbs(); |
0 |
11319 |
CurMBB->normalizeSuccProbs(); |
0 |
| 11320 |
|
--- |
11320 |
|
--- |
| 11321 |
// The jump table header will be inserted in our current block, do the |
--- |
11321 |
// The jump table header will be inserted in our current block, do the |
--- |
| 11322 |
// range check, and fall through to our fallthrough block. |
--- |
11322 |
// range check, and fall through to our fallthrough block. |
--- |
| 11323 |
JTH->HeaderBB = CurMBB; |
0 |
11323 |
JTH->HeaderBB = CurMBB; |
0 |
| 11324 |
JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader. |
0 |
11324 |
JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader. |
0 |
| 11325 |
|
--- |
11325 |
|
--- |
| 11326 |
// If we're in the right place, emit the jump table header right now. |
--- |
11326 |
// If we're in the right place, emit the jump table header right now. |
--- |
| 11327 |
if (CurMBB == SwitchMBB) { |
0 |
11327 |
if (CurMBB == SwitchMBB) { |
0 |
| 11328 |
visitJumpTableHeader(*JT, *JTH, SwitchMBB); |
0 |
11328 |
visitJumpTableHeader(*JT, *JTH, SwitchMBB); |
0 |
| 11329 |
JTH->Emitted = true; |
0 |
11329 |
JTH->Emitted = true; |
0 |
| 11330 |
} |
--- |
11330 |
} |
--- |
| 11331 |
break; |
0 |
11331 |
break; |
0 |
| 11332 |
} |
--- |
11332 |
} |
--- |
| 11333 |
case CC_BitTests: { |
0 |
11333 |
case CC_BitTests: { |
0 |
| 11334 |
// FIXME: Optimize away range check based on pivot comparisons. |
--- |
11334 |
// FIXME: Optimize away range check based on pivot comparisons. |
--- |
| 11335 |
BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex]; |
0 |
11335 |
BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex]; |
0 |
| 11336 |
|
--- |
11336 |
|
--- |
| 11337 |
// The bit test blocks haven't been inserted yet; insert them here. |
--- |
11337 |
// The bit test blocks haven't been inserted yet; insert them here. |
--- |
| 11338 |
for (BitTestCase &BTC : BTB->Cases) |
0 |
11338 |
for (BitTestCase &BTC : BTB->Cases) |
0 |
| 11339 |
CurMF->insert(BBI, BTC.ThisBB); |
0 |
11339 |
CurMF->insert(BBI, BTC.ThisBB); |
0 |
| 11340 |
|
--- |
11340 |
|
--- |
| 11341 |
// Fill in fields of the BitTestBlock. |
--- |
11341 |
// Fill in fields of the BitTestBlock. |
--- |
| 11342 |
BTB->Parent = CurMBB; |
0 |
11342 |
BTB->Parent = CurMBB; |
0 |
| 11343 |
BTB->Default = Fallthrough; |
0 |
11343 |
BTB->Default = Fallthrough; |
0 |
| 11344 |
|
--- |
11344 |
|
--- |
| 11345 |
BTB->DefaultProb = UnhandledProbs; |
0 |
11345 |
BTB->DefaultProb = UnhandledProbs; |
0 |
| 11346 |
// If the cases in bit test don't form a contiguous range, we evenly |
--- |
11346 |
// If the cases in bit test don't form a contiguous range, we evenly |
--- |
| 11347 |
// distribute the probability on the edge to Fallthrough to two |
--- |
11347 |
// distribute the probability on the edge to Fallthrough to two |
--- |
| 11348 |
// successors of CurMBB. |
--- |
11348 |
// successors of CurMBB. |
--- |
| 11349 |
if (!BTB->ContiguousRange) { |
0 |
11349 |
if (!BTB->ContiguousRange) { |
0 |
| 11350 |
BTB->Prob += DefaultProb / 2; |
0 |
11350 |
BTB->Prob += DefaultProb / 2; |
0 |
| 11351 |
BTB->DefaultProb -= DefaultProb / 2; |
0 |
11351 |
BTB->DefaultProb -= DefaultProb / 2; |
0 |
| 11352 |
} |
--- |
11352 |
} |
--- |
| 11353 |
|
--- |
11353 |
|
--- |
| 11354 |
if (FallthroughUnreachable) |
0 |
11354 |
if (FallthroughUnreachable) |
0 |
| 11355 |
BTB->FallthroughUnreachable = true; |
0 |
11355 |
BTB->FallthroughUnreachable = true; |
0 |
| 11356 |
|
--- |
11356 |
|
--- |
| 11357 |
// If we're in the right place, emit the bit test header right now. |
--- |
11357 |
// If we're in the right place, emit the bit test header right now. |
--- |
| 11358 |
if (CurMBB == SwitchMBB) { |
0 |
11358 |
if (CurMBB == SwitchMBB) { |
0 |
| 11359 |
visitBitTestHeader(*BTB, SwitchMBB); |
0 |
11359 |
visitBitTestHeader(*BTB, SwitchMBB); |
0 |
| 11360 |
BTB->Emitted = true; |
0 |
11360 |
BTB->Emitted = true; |
0 |
| 11361 |
} |
--- |
11361 |
} |
--- |
| 11362 |
break; |
0 |
11362 |
break; |
0 |
| 11363 |
} |
--- |
11363 |
} |
--- |
| 11364 |
case CC_Range: { |
0 |
11364 |
case CC_Range: { |
0 |
| 11365 |
const Value *RHS, *LHS, *MHS; |
--- |
11365 |
const Value *RHS, *LHS, *MHS; |
--- |
| 11366 |
ISD::CondCode CC; |
--- |
11366 |
ISD::CondCode CC; |
--- |
| 11367 |
if (I->Low == I->High) { |
0 |
11367 |
if (I->Low == I->High) { |
0 |
| 11368 |
// Check Cond == I->Low. |
--- |
11368 |
// Check Cond == I->Low. |
--- |
| 11369 |
CC = ISD::SETEQ; |
0 |
11369 |
CC = ISD::SETEQ; |
0 |
| 11370 |
LHS = Cond; |
0 |
11370 |
LHS = Cond; |
0 |
| 11371 |
RHS=I->Low; |
0 |
11371 |
RHS=I->Low; |
0 |
| 11372 |
MHS = nullptr; |
0 |
11372 |
MHS = nullptr; |
0 |
| 11373 |
} else { |
--- |
11373 |
} else { |
--- |
| 11374 |
// Check I->Low <= Cond <= I->High. |
--- |
11374 |
// Check I->Low <= Cond <= I->High. |
--- |
| 11375 |
CC = ISD::SETLE; |
0 |
11375 |
CC = ISD::SETLE; |
0 |
| 11376 |
LHS = I->Low; |
0 |
11376 |
LHS = I->Low; |
0 |
| 11377 |
MHS = Cond; |
0 |
11377 |
MHS = Cond; |
0 |
| 11378 |
RHS = I->High; |
0 |
11378 |
RHS = I->High; |
0 |
| 11379 |
} |
--- |
11379 |
} |
--- |
| 11380 |
|
--- |
11380 |
|
--- |
| 11381 |
// If Fallthrough is unreachable, fold away the comparison. |
--- |
11381 |
// If Fallthrough is unreachable, fold away the comparison. |
--- |
| 11382 |
if (FallthroughUnreachable) |
0 |
11382 |
if (FallthroughUnreachable) |
0 |
| 11383 |
CC = ISD::SETTRUE; |
0 |
11383 |
CC = ISD::SETTRUE; |
0 |
| 11384 |
|
--- |
11384 |
|
--- |
| 11385 |
// The false probability is the sum of all unhandled cases. |
--- |
11385 |
// The false probability is the sum of all unhandled cases. |
--- |
| 11386 |
CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, |
0 |
11386 |
CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, |
0 |
| 11387 |
getCurSDLoc(), I->Prob, UnhandledProbs); |
0 |
11387 |
getCurSDLoc(), I->Prob, UnhandledProbs); |
0 |
| 11388 |
|
--- |
11388 |
|
--- |
| 11389 |
if (CurMBB == SwitchMBB) |
0 |
11389 |
if (CurMBB == SwitchMBB) |
0 |
| 11390 |
visitSwitchCase(CB, SwitchMBB); |
0 |
11390 |
visitSwitchCase(CB, SwitchMBB); |
0 |
| 11391 |
else |
--- |
11391 |
else |
--- |
| 11392 |
SL->SwitchCases.push_back(CB); |
0 |
11392 |
SL->SwitchCases.push_back(CB); |
0 |
| 11393 |
|
--- |
11393 |
|
--- |
| 11394 |
break; |
0 |
11394 |
break; |
0 |
| 11395 |
} |
0 |
11395 |
} |
0 |
| 11396 |
} |
--- |
11396 |
} |
--- |
| 11397 |
CurMBB = Fallthrough; |
0 |
11397 |
CurMBB = Fallthrough; |
0 |
| 11398 |
} |
--- |
11398 |
} |
--- |
| 11399 |
} |
--- |
11399 |
} |
--- |
| 11400 |
|
--- |
11400 |
|
--- |
| 11401 |
unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC, |
0 |
11401 |
unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC, |
0 |
| 11402 |
CaseClusterIt First, |
--- |
11402 |
CaseClusterIt First, |
--- |
| 11403 |
CaseClusterIt Last) { |
--- |
11403 |
CaseClusterIt Last) { |
--- |
| 11404 |
return std::count_if(First, Last + 1, [&](const CaseCluster &X) { |
0 |
11404 |
return std::count_if(First, Last + 1, [&](const CaseCluster &X) { |
0 |
| 11405 |
if (X.Prob != CC.Prob) |
0 |
11405 |
if (X.Prob != CC.Prob) |
0 |
| 11406 |
return X.Prob > CC.Prob; |
0 |
11406 |
return X.Prob > CC.Prob; |
0 |
| 11407 |
|
--- |
11407 |
|
--- |
| 11408 |
// Ties are broken by comparing the case value. |
--- |
11408 |
// Ties are broken by comparing the case value. |
--- |
| 11409 |
return X.Low->getValue().slt(CC.Low->getValue()); |
0 |
11409 |
return X.Low->getValue().slt(CC.Low->getValue()); |
0 |
| 11410 |
}); |
0 |
11410 |
}); |
0 |
| 11411 |
} |
--- |
11411 |
} |
--- |
| 11412 |
|
--- |
11412 |
|
--- |
| 11413 |
void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList, |
0 |
11413 |
void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList, |
0 |
| 11414 |
const SwitchWorkListItem &W, |
--- |
11414 |
const SwitchWorkListItem &W, |
--- |
| 11415 |
Value *Cond, |
--- |
11415 |
Value *Cond, |
--- |
| 11416 |
MachineBasicBlock *SwitchMBB) { |
--- |
11416 |
MachineBasicBlock *SwitchMBB) { |
--- |
| 11417 |
assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && |
0 |
11417 |
assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && |
0 |
| 11418 |
"Clusters not sorted?"); |
--- |
11418 |
"Clusters not sorted?"); |
--- |
| 11419 |
|
--- |
11419 |
|
--- |
| 11420 |
assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!"); |
0 |
11420 |
assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!"); |
0 |
| 11421 |
|
--- |
11421 |
|
--- |
| 11422 |
// Balance the tree based on branch probabilities to create a near-optimal (in |
--- |
11422 |
// Balance the tree based on branch probabilities to create a near-optimal (in |
--- |
| 11423 |
// terms of search time given key frequency) binary search tree. See e.g. Kurt |
--- |
11423 |
// terms of search time given key frequency) binary search tree. See e.g. Kurt |
--- |
| 11424 |
// Mehlhorn "Nearly Optimal Binary Search Trees" (1975). |
--- |
11424 |
// Mehlhorn "Nearly Optimal Binary Search Trees" (1975). |
--- |
| 11425 |
CaseClusterIt LastLeft = W.FirstCluster; |
0 |
11425 |
CaseClusterIt LastLeft = W.FirstCluster; |
0 |
| 11426 |
CaseClusterIt FirstRight = W.LastCluster; |
0 |
11426 |
CaseClusterIt FirstRight = W.LastCluster; |
0 |
| 11427 |
auto LeftProb = LastLeft->Prob + W.DefaultProb / 2; |
0 |
11427 |
auto LeftProb = LastLeft->Prob + W.DefaultProb / 2; |
0 |
| 11428 |
auto RightProb = FirstRight->Prob + W.DefaultProb / 2; |
0 |
11428 |
auto RightProb = FirstRight->Prob + W.DefaultProb / 2; |
0 |
| 11429 |
|
--- |
11429 |
|
--- |
| 11430 |
// Move LastLeft and FirstRight towards each other from opposite directions to |
--- |
11430 |
// Move LastLeft and FirstRight towards each other from opposite directions to |
--- |
| 11431 |
// find a partitioning of the clusters which balances the probability on both |
--- |
11431 |
// find a partitioning of the clusters which balances the probability on both |
--- |
| 11432 |
// sides. If LeftProb and RightProb are equal, alternate which side is |
--- |
11432 |
// sides. If LeftProb and RightProb are equal, alternate which side is |
--- |
| 11433 |
// taken to ensure 0-probability nodes are distributed evenly. |
--- |
11433 |
// taken to ensure 0-probability nodes are distributed evenly. |
--- |
| 11434 |
unsigned I = 0; |
0 |
11434 |
unsigned I = 0; |
0 |
| 11435 |
while (LastLeft + 1 < FirstRight) { |
0 |
11435 |
while (LastLeft + 1 < FirstRight) { |
0 |
| 11436 |
if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1))) |
0 |
11436 |
if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1))) |
0 |
| 11437 |
LeftProb += (++LastLeft)->Prob; |
0 |
11437 |
LeftProb += (++LastLeft)->Prob; |
0 |
| 11438 |
else |
--- |
11438 |
else |
--- |
| 11439 |
RightProb += (--FirstRight)->Prob; |
0 |
11439 |
RightProb += (--FirstRight)->Prob; |
0 |
| 11440 |
I++; |
0 |
11440 |
I++; |
0 |
| 11441 |
} |
--- |
11441 |
} |
--- |
| 11442 |
|
--- |
11442 |
|
--- |
| 11443 |
while (true) { |
--- |
11443 |
while (true) { |
--- |
| 11444 |
// Our binary search tree differs from a typical BST in that ours can have up |
--- |
11444 |
// Our binary search tree differs from a typical BST in that ours can have up |
--- |
| 11445 |
// to three values in each leaf. The pivot selection above doesn't take that |
--- |
11445 |
// to three values in each leaf. The pivot selection above doesn't take that |
--- |
| 11446 |
// into account, which means the tree might require more nodes and be less |
--- |
11446 |
// into account, which means the tree might require more nodes and be less |
--- |
| 11447 |
// efficient. We compensate for this here. |
--- |
11447 |
// efficient. We compensate for this here. |
--- |
| 11448 |
|
--- |
11448 |
|
--- |
| 11449 |
unsigned NumLeft = LastLeft - W.FirstCluster + 1; |
0 |
11449 |
unsigned NumLeft = LastLeft - W.FirstCluster + 1; |
0 |
| 11450 |
unsigned NumRight = W.LastCluster - FirstRight + 1; |
0 |
11450 |
unsigned NumRight = W.LastCluster - FirstRight + 1; |
0 |
| 11451 |
|
--- |
11451 |
|
--- |
| 11452 |
if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) { |
0 |
11452 |
if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) { |
0 |
| 11453 |
// If one side has less than 3 clusters, and the other has more than 3, |
--- |
11453 |
// If one side has less than 3 clusters, and the other has more than 3, |
--- |
| 11454 |
// consider taking a cluster from the other side. |
--- |
11454 |
// consider taking a cluster from the other side. |
--- |
| 11455 |
|
--- |
11455 |
|
--- |
| 11456 |
if (NumLeft < NumRight) { |
0 |
11456 |
if (NumLeft < NumRight) { |
0 |
| 11457 |
// Consider moving the first cluster on the right to the left side. |
--- |
11457 |
// Consider moving the first cluster on the right to the left side. |
--- |
| 11458 |
CaseCluster &CC = *FirstRight; |
0 |
11458 |
CaseCluster &CC = *FirstRight; |
0 |
| 11459 |
unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); |
0 |
11459 |
unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); |
0 |
| 11460 |
unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); |
0 |
11460 |
unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); |
0 |
| 11461 |
if (LeftSideRank <= RightSideRank) { |
0 |
11461 |
if (LeftSideRank <= RightSideRank) { |
0 |
| 11462 |
// Moving the cluster to the left does not demote it. |
--- |
11462 |
// Moving the cluster to the left does not demote it. |
--- |
| 11463 |
++LastLeft; |
0 |
11463 |
++LastLeft; |
0 |
| 11464 |
++FirstRight; |
0 |
11464 |
++FirstRight; |
0 |
| 11465 |
continue; |
0 |
11465 |
continue; |
0 |
| 11466 |
} |
--- |
11466 |
} |
--- |
| 11467 |
} else { |
--- |
11467 |
} else { |
--- |
| 11468 |
assert(NumRight < NumLeft); |
0 |
11468 |
assert(NumRight < NumLeft); |
0 |
| 11469 |
// Consider moving the last element on the left to the right side. |
--- |
11469 |
// Consider moving the last element on the left to the right side. |
--- |
| 11470 |
CaseCluster &CC = *LastLeft; |
0 |
11470 |
CaseCluster &CC = *LastLeft; |
0 |
| 11471 |
unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); |
0 |
11471 |
unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); |
0 |
| 11472 |
unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); |
0 |
11472 |
unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); |
0 |
| 11473 |
if (RightSideRank <= LeftSideRank) { |
0 |
11473 |
if (RightSideRank <= LeftSideRank) { |
0 |
| 11474 |
// Moving the cluster to the right does not demot it. |
--- |
11474 |
// Moving the cluster to the right does not demot it. |
--- |
| 11475 |
--LastLeft; |
0 |
11475 |
--LastLeft; |
0 |
| 11476 |
--FirstRight; |
0 |
11476 |
--FirstRight; |
0 |
| 11477 |
continue; |
0 |
11477 |
continue; |
0 |
| 11478 |
} |
--- |
11478 |
} |
--- |
| 11479 |
} |
--- |
11479 |
} |
--- |
| 11480 |
} |
--- |
11480 |
} |
--- |
| 11481 |
break; |
0 |
11481 |
break; |
0 |
| 11482 |
} |
0 |
11482 |
} |
0 |
| 11483 |
|
--- |
11483 |
|
--- |
| 11484 |
assert(LastLeft + 1 == FirstRight); |
0 |
11484 |
assert(LastLeft + 1 == FirstRight); |
0 |
| 11485 |
assert(LastLeft >= W.FirstCluster); |
0 |
11485 |
assert(LastLeft >= W.FirstCluster); |
0 |
| 11486 |
assert(FirstRight <= W.LastCluster); |
0 |
11486 |
assert(FirstRight <= W.LastCluster); |
0 |
| 11487 |
|
--- |
11487 |
|
--- |
| 11488 |
// Use the first element on the right as pivot since we will make less-than |
--- |
11488 |
// Use the first element on the right as pivot since we will make less-than |
--- |
| 11489 |
// comparisons against it. |
--- |
11489 |
// comparisons against it. |
--- |
| 11490 |
CaseClusterIt PivotCluster = FirstRight; |
0 |
11490 |
CaseClusterIt PivotCluster = FirstRight; |
0 |
| 11491 |
assert(PivotCluster > W.FirstCluster); |
0 |
11491 |
assert(PivotCluster > W.FirstCluster); |
0 |
| 11492 |
assert(PivotCluster <= W.LastCluster); |
0 |
11492 |
assert(PivotCluster <= W.LastCluster); |
0 |
| 11493 |
|
--- |
11493 |
|
--- |
| 11494 |
CaseClusterIt FirstLeft = W.FirstCluster; |
0 |
11494 |
CaseClusterIt FirstLeft = W.FirstCluster; |
0 |
| 11495 |
CaseClusterIt LastRight = W.LastCluster; |
0 |
11495 |
CaseClusterIt LastRight = W.LastCluster; |
0 |
| 11496 |
|
--- |
11496 |
|
--- |
| 11497 |
const ConstantInt *Pivot = PivotCluster->Low; |
0 |
11497 |
const ConstantInt *Pivot = PivotCluster->Low; |
0 |
| 11498 |
|
--- |
11498 |
|
--- |
| 11499 |
// New blocks will be inserted immediately after the current one. |
--- |
11499 |
// New blocks will be inserted immediately after the current one. |
--- |
| 11500 |
MachineFunction::iterator BBI(W.MBB); |
0 |
11500 |
MachineFunction::iterator BBI(W.MBB); |
0 |
| 11501 |
++BBI; |
0 |
11501 |
++BBI; |
0 |
| 11502 |
|
--- |
11502 |
|
--- |
| 11503 |
// We will branch to the LHS if Value < Pivot. If LHS is a single cluster, |
--- |
11503 |
// We will branch to the LHS if Value < Pivot. If LHS is a single cluster, |
--- |
| 11504 |
// we can branch to its destination directly if it's squeezed exactly in |
--- |
11504 |
// we can branch to its destination directly if it's squeezed exactly in |
--- |
| 11505 |
// between the known lower bound and Pivot - 1. |
--- |
11505 |
// between the known lower bound and Pivot - 1. |
--- |
| 11506 |
MachineBasicBlock *LeftMBB; |
--- |
11506 |
MachineBasicBlock *LeftMBB; |
--- |
| 11507 |
if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range && |
0 |
11507 |
if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range && |
0 |
| 11508 |
FirstLeft->Low == W.GE && |
0 |
11508 |
FirstLeft->Low == W.GE && |
0 |
| 11509 |
(FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) { |
0 |
11509 |
(FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) { |
0 |
| 11510 |
LeftMBB = FirstLeft->MBB; |
0 |
11510 |
LeftMBB = FirstLeft->MBB; |
0 |
| 11511 |
} else { |
--- |
11511 |
} else { |
--- |
| 11512 |
LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); |
0 |
11512 |
LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); |
0 |
| 11513 |
FuncInfo.MF->insert(BBI, LeftMBB); |
0 |
11513 |
FuncInfo.MF->insert(BBI, LeftMBB); |
0 |
| 11514 |
WorkList.push_back( |
0 |
11514 |
WorkList.push_back( |
0 |
| 11515 |
{LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2}); |
0 |
11515 |
{LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2}); |
0 |
| 11516 |
// Put Cond in a virtual register to make it available from the new blocks. |
--- |
11516 |
// Put Cond in a virtual register to make it available from the new blocks. |
--- |
| 11517 |
ExportFromCurrentBlock(Cond); |
0 |
11517 |
ExportFromCurrentBlock(Cond); |
0 |
| 11518 |
} |
--- |
11518 |
} |
--- |
| 11519 |
|
--- |
11519 |
|
--- |
| 11520 |
// Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a |
--- |
11520 |
// Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a |
--- |
| 11521 |
// single cluster, RHS.Low == Pivot, and we can branch to its destination |
--- |
11521 |
// single cluster, RHS.Low == Pivot, and we can branch to its destination |
--- |
| 11522 |
// directly if RHS.High equals the current upper bound. |
--- |
11522 |
// directly if RHS.High equals the current upper bound. |
--- |
| 11523 |
MachineBasicBlock *RightMBB; |
--- |
11523 |
MachineBasicBlock *RightMBB; |
--- |
| 11524 |
if (FirstRight == LastRight && FirstRight->Kind == CC_Range && |
0 |
11524 |
if (FirstRight == LastRight && FirstRight->Kind == CC_Range && |
0 |
| 11525 |
W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) { |
0 |
11525 |
W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) { |
0 |
| 11526 |
RightMBB = FirstRight->MBB; |
0 |
11526 |
RightMBB = FirstRight->MBB; |
0 |
| 11527 |
} else { |
--- |
11527 |
} else { |
--- |
| 11528 |
RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); |
0 |
11528 |
RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); |
0 |
| 11529 |
FuncInfo.MF->insert(BBI, RightMBB); |
0 |
11529 |
FuncInfo.MF->insert(BBI, RightMBB); |
0 |
| 11530 |
WorkList.push_back( |
0 |
11530 |
WorkList.push_back( |
0 |
| 11531 |
{RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2}); |
0 |
11531 |
{RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2}); |
0 |
| 11532 |
// Put Cond in a virtual register to make it available from the new blocks. |
--- |
11532 |
// Put Cond in a virtual register to make it available from the new blocks. |
--- |
| 11533 |
ExportFromCurrentBlock(Cond); |
0 |
11533 |
ExportFromCurrentBlock(Cond); |
0 |
| 11534 |
} |
--- |
11534 |
} |
--- |
| 11535 |
|
--- |
11535 |
|
--- |
| 11536 |
// Create the CaseBlock record that will be used to lower the branch. |
--- |
11536 |
// Create the CaseBlock record that will be used to lower the branch. |
--- |
| 11537 |
CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB, |
0 |
11537 |
CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB, |
0 |
| 11538 |
getCurSDLoc(), LeftProb, RightProb); |
0 |
11538 |
getCurSDLoc(), LeftProb, RightProb); |
0 |
| 11539 |
|
--- |
11539 |
|
--- |
| 11540 |
if (W.MBB == SwitchMBB) |
0 |
11540 |
if (W.MBB == SwitchMBB) |
0 |
| 11541 |
visitSwitchCase(CB, SwitchMBB); |
0 |
11541 |
visitSwitchCase(CB, SwitchMBB); |
0 |
| 11542 |
else |
--- |
11542 |
else |
--- |
| 11543 |
SL->SwitchCases.push_back(CB); |
0 |
11543 |
SL->SwitchCases.push_back(CB); |
0 |
| 11544 |
} |
0 |
11544 |
} |
0 |
| 11545 |
|
--- |
11545 |
|
--- |
| 11546 |
// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb |
--- |
11546 |
// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb |
--- |
| 11547 |
// from the swith statement. |
--- |
11547 |
// from the swith statement. |
--- |
| 11548 |
static BranchProbability scaleCaseProbality(BranchProbability CaseProb, |
0 |
11548 |
static BranchProbability scaleCaseProbality(BranchProbability CaseProb, |
0 |
| 11549 |
BranchProbability PeeledCaseProb) { |
--- |
11549 |
BranchProbability PeeledCaseProb) { |
--- |
| 11550 |
if (PeeledCaseProb == BranchProbability::getOne()) |
0 |
11550 |
if (PeeledCaseProb == BranchProbability::getOne()) |
0 |
| 11551 |
return BranchProbability::getZero(); |
0 |
11551 |
return BranchProbability::getZero(); |
0 |
| 11552 |
BranchProbability SwitchProb = PeeledCaseProb.getCompl(); |
0 |
11552 |
BranchProbability SwitchProb = PeeledCaseProb.getCompl(); |
0 |
| 11553 |
|
--- |
11553 |
|
--- |
| 11554 |
uint32_t Numerator = CaseProb.getNumerator(); |
0 |
11554 |
uint32_t Numerator = CaseProb.getNumerator(); |
0 |
| 11555 |
uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator()); |
0 |
11555 |
uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator()); |
0 |
| 11556 |
return BranchProbability(Numerator, std::max(Numerator, Denominator)); |
0 |
11556 |
return BranchProbability(Numerator, std::max(Numerator, Denominator)); |
0 |
| 11557 |
} |
--- |
11557 |
} |
--- |
| 11558 |
|
--- |
11558 |
|
--- |
| 11559 |
// Try to peel the top probability case if it exceeds the threshold. |
--- |
11559 |
// Try to peel the top probability case if it exceeds the threshold. |
--- |
| 11560 |
// Return current MachineBasicBlock for the switch statement if the peeling |
--- |
11560 |
// Return current MachineBasicBlock for the switch statement if the peeling |
--- |
| 11561 |
// does not occur. |
--- |
11561 |
// does not occur. |
--- |
| 11562 |
// If the peeling is performed, return the newly created MachineBasicBlock |
--- |
11562 |
// If the peeling is performed, return the newly created MachineBasicBlock |
--- |
| 11563 |
// for the peeled switch statement. Also update Clusters to remove the peeled |
--- |
11563 |
// for the peeled switch statement. Also update Clusters to remove the peeled |
--- |
| 11564 |
// case. PeeledCaseProb is the BranchProbability for the peeled case. |
--- |
11564 |
// case. PeeledCaseProb is the BranchProbability for the peeled case. |
--- |
| 11565 |
MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster( |
0 |
11565 |
MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster( |
0 |
| 11566 |
const SwitchInst &SI, CaseClusterVector &Clusters, |
--- |
11566 |
const SwitchInst &SI, CaseClusterVector &Clusters, |
--- |
| 11567 |
BranchProbability &PeeledCaseProb) { |
--- |
11567 |
BranchProbability &PeeledCaseProb) { |
--- |
| 11568 |
MachineBasicBlock *SwitchMBB = FuncInfo.MBB; |
0 |
11568 |
MachineBasicBlock *SwitchMBB = FuncInfo.MBB; |
0 |
| 11569 |
// Don't perform if there is only one cluster or optimizing for size. |
--- |
11569 |
// Don't perform if there is only one cluster or optimizing for size. |
--- |
| 11570 |
if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 || |
0 |
11570 |
if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 || |
0 |
| 11571 |
TM.getOptLevel() == CodeGenOpt::None || |
0 |
11571 |
TM.getOptLevel() == CodeGenOpt::None || |
0 |
| 11572 |
SwitchMBB->getParent()->getFunction().hasMinSize()) |
0 |
11572 |
SwitchMBB->getParent()->getFunction().hasMinSize()) |
0 |
| 11573 |
return SwitchMBB; |
0 |
11573 |
return SwitchMBB; |
0 |
| 11574 |
|
--- |
11574 |
|
--- |
| 11575 |
BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100); |
0 |
11575 |
BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100); |
0 |
| 11576 |
unsigned PeeledCaseIndex = 0; |
0 |
11576 |
unsigned PeeledCaseIndex = 0; |
0 |
| 11577 |
bool SwitchPeeled = false; |
0 |
11577 |
bool SwitchPeeled = false; |
0 |
| 11578 |
for (unsigned Index = 0; Index < Clusters.size(); ++Index) { |
0 |
11578 |
for (unsigned Index = 0; Index < Clusters.size(); ++Index) { |
0 |
| 11579 |
CaseCluster &CC = Clusters[Index]; |
0 |
11579 |
CaseCluster &CC = Clusters[Index]; |
0 |
| 11580 |
if (CC.Prob < TopCaseProb) |
0 |
11580 |
if (CC.Prob < TopCaseProb) |
0 |
| 11581 |
continue; |
0 |
11581 |
continue; |
0 |
| 11582 |
TopCaseProb = CC.Prob; |
0 |
11582 |
TopCaseProb = CC.Prob; |
0 |
| 11583 |
PeeledCaseIndex = Index; |
0 |
11583 |
PeeledCaseIndex = Index; |
0 |
| 11584 |
SwitchPeeled = true; |
0 |
11584 |
SwitchPeeled = true; |
0 |
| 11585 |
} |
--- |
11585 |
} |
--- |
| 11586 |
if (!SwitchPeeled) |
0 |
11586 |
if (!SwitchPeeled) |
0 |
| 11587 |
return SwitchMBB; |
0 |
11587 |
return SwitchMBB; |
0 |
| 11588 |
|
--- |
11588 |
|
--- |
| 11589 |
LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: " |
0 |
11589 |
LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: " |
0 |
| 11590 |
<< TopCaseProb << "\n"); |
--- |
11590 |
<< TopCaseProb << "\n"); |
--- |
| 11591 |
|
--- |
11591 |
|
--- |
| 11592 |
// Record the MBB for the peeled switch statement. |
--- |
11592 |
// Record the MBB for the peeled switch statement. |
--- |
| 11593 |
MachineFunction::iterator BBI(SwitchMBB); |
0 |
11593 |
MachineFunction::iterator BBI(SwitchMBB); |
0 |
| 11594 |
++BBI; |
0 |
11594 |
++BBI; |
0 |
| 11595 |
MachineBasicBlock *PeeledSwitchMBB = |
--- |
11595 |
MachineBasicBlock *PeeledSwitchMBB = |
--- |
| 11596 |
FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock()); |
0 |
11596 |
FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock()); |
0 |
| 11597 |
FuncInfo.MF->insert(BBI, PeeledSwitchMBB); |
0 |
11597 |
FuncInfo.MF->insert(BBI, PeeledSwitchMBB); |
0 |
| 11598 |
|
--- |
11598 |
|
--- |
| 11599 |
ExportFromCurrentBlock(SI.getCondition()); |
0 |
11599 |
ExportFromCurrentBlock(SI.getCondition()); |
0 |
| 11600 |
auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex; |
0 |
11600 |
auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex; |
0 |
| 11601 |
SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt, |
0 |
11601 |
SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt, |
0 |
| 11602 |
nullptr, nullptr, TopCaseProb.getCompl()}; |
0 |
11602 |
nullptr, nullptr, TopCaseProb.getCompl()}; |
0 |
| 11603 |
lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB); |
0 |
11603 |
lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB); |
0 |
| 11604 |
|
--- |
11604 |
|
--- |
| 11605 |
Clusters.erase(PeeledCaseIt); |
0 |
11605 |
Clusters.erase(PeeledCaseIt); |
0 |
| 11606 |
for (CaseCluster &CC : Clusters) { |
0 |
11606 |
for (CaseCluster &CC : Clusters) { |
0 |
| 11607 |
LLVM_DEBUG( |
0 |
11607 |
LLVM_DEBUG( |
0 |
| 11608 |
dbgs() << "Scale the probablity for one cluster, before scaling: " |
--- |
11608 |
dbgs() << "Scale the probablity for one cluster, before scaling: " |
--- |
| 11609 |
<< CC.Prob << "\n"); |
--- |
11609 |
<< CC.Prob << "\n"); |
--- |
| 11610 |
CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb); |
0 |
11610 |
CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb); |
0 |
| 11611 |
LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n"); |
0 |
11611 |
LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n"); |
0 |
| 11612 |
} |
--- |
11612 |
} |
--- |
| 11613 |
PeeledCaseProb = TopCaseProb; |
0 |
11613 |
PeeledCaseProb = TopCaseProb; |
0 |
| 11614 |
return PeeledSwitchMBB; |
0 |
11614 |
return PeeledSwitchMBB; |
0 |
| 11615 |
} |
--- |
11615 |
} |
--- |
| 11616 |
|
--- |
11616 |
|
--- |
| 11617 |
void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { |
0 |
11617 |
void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { |
0 |
| 11618 |
// Extract cases from the switch. |
--- |
11618 |
// Extract cases from the switch. |
--- |
| 11619 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
11619 |
BranchProbabilityInfo *BPI = FuncInfo.BPI; |
0 |
| 11620 |
CaseClusterVector Clusters; |
0 |
11620 |
CaseClusterVector Clusters; |
0 |
| 11621 |
Clusters.reserve(SI.getNumCases()); |
0 |
11621 |
Clusters.reserve(SI.getNumCases()); |
0 |
| 11622 |
for (auto I : SI.cases()) { |
0 |
11622 |
for (auto I : SI.cases()) { |
0 |
| 11623 |
MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()]; |
0 |
11623 |
MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()]; |
0 |
| 11624 |
const ConstantInt *CaseVal = I.getCaseValue(); |
0 |
11624 |
const ConstantInt *CaseVal = I.getCaseValue(); |
0 |
| 11625 |
BranchProbability Prob = |
--- |
11625 |
BranchProbability Prob = |
--- |
| 11626 |
BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex()) |
0 |
11626 |
BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex()) |
0 |
| 11627 |
: BranchProbability(1, SI.getNumCases() + 1); |
0 |
11627 |
: BranchProbability(1, SI.getNumCases() + 1); |
0 |
| 11628 |
Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob)); |
0 |
11628 |
Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob)); |
0 |
| 11629 |
} |
--- |
11629 |
} |
--- |
| 11630 |
|
--- |
11630 |
|
--- |
| 11631 |
MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()]; |
0 |
11631 |
MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()]; |
0 |
| 11632 |
|
--- |
11632 |
|
--- |
| 11633 |
// Cluster adjacent cases with the same destination. We do this at all |
--- |
11633 |
// Cluster adjacent cases with the same destination. We do this at all |
--- |
| 11634 |
// optimization levels because it's cheap to do and will make codegen faster |
--- |
11634 |
// optimization levels because it's cheap to do and will make codegen faster |
--- |
| 11635 |
// if there are many clusters. |
--- |
11635 |
// if there are many clusters. |
--- |
| 11636 |
sortAndRangeify(Clusters); |
0 |
11636 |
sortAndRangeify(Clusters); |
0 |
| 11637 |
|
--- |
11637 |
|
--- |
| 11638 |
// The branch probablity of the peeled case. |
--- |
11638 |
// The branch probablity of the peeled case. |
--- |
| 11639 |
BranchProbability PeeledCaseProb = BranchProbability::getZero(); |
0 |
11639 |
BranchProbability PeeledCaseProb = BranchProbability::getZero(); |
0 |
| 11640 |
MachineBasicBlock *PeeledSwitchMBB = |
--- |
11640 |
MachineBasicBlock *PeeledSwitchMBB = |
--- |
| 11641 |
peelDominantCaseCluster(SI, Clusters, PeeledCaseProb); |
0 |
11641 |
peelDominantCaseCluster(SI, Clusters, PeeledCaseProb); |
0 |
| 11642 |
|
--- |
11642 |
|
--- |
| 11643 |
// If there is only the default destination, jump there directly. |
--- |
11643 |
// If there is only the default destination, jump there directly. |
--- |
| 11644 |
MachineBasicBlock *SwitchMBB = FuncInfo.MBB; |
0 |
11644 |
MachineBasicBlock *SwitchMBB = FuncInfo.MBB; |
0 |
| 11645 |
if (Clusters.empty()) { |
0 |
11645 |
if (Clusters.empty()) { |
0 |
| 11646 |
assert(PeeledSwitchMBB == SwitchMBB); |
0 |
11646 |
assert(PeeledSwitchMBB == SwitchMBB); |
0 |
| 11647 |
SwitchMBB->addSuccessor(DefaultMBB); |
0 |
11647 |
SwitchMBB->addSuccessor(DefaultMBB); |
0 |
| 11648 |
if (DefaultMBB != NextBlock(SwitchMBB)) { |
0 |
11648 |
if (DefaultMBB != NextBlock(SwitchMBB)) { |
0 |
| 11649 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, |
0 |
11649 |
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, |
0 |
| 11650 |
getControlRoot(), DAG.getBasicBlock(DefaultMBB))); |
0 |
11650 |
getControlRoot(), DAG.getBasicBlock(DefaultMBB))); |
0 |
| 11651 |
} |
--- |
11651 |
} |
--- |
| 11652 |
return; |
0 |
11652 |
return; |
0 |
| 11653 |
} |
--- |
11653 |
} |
--- |
| 11654 |
|
--- |
11654 |
|
--- |
| 11655 |
SL->findJumpTables(Clusters, &SI, DefaultMBB, DAG.getPSI(), DAG.getBFI()); |
0 |
11655 |
SL->findJumpTables(Clusters, &SI, DefaultMBB, DAG.getPSI(), DAG.getBFI()); |
0 |
| 11656 |
SL->findBitTestClusters(Clusters, &SI); |
0 |
11656 |
SL->findBitTestClusters(Clusters, &SI); |
0 |
| 11657 |
|
--- |
11657 |
|
--- |
| 11658 |
LLVM_DEBUG({ |
0 |
11658 |
LLVM_DEBUG({ |
0 |
| 11659 |
dbgs() << "Case clusters: "; |
--- |
11659 |
dbgs() << "Case clusters: "; |
--- |
| 11660 |
for (const CaseCluster &C : Clusters) { |
--- |
11660 |
for (const CaseCluster &C : Clusters) { |
--- |
| 11661 |
if (C.Kind == CC_JumpTable) |
--- |
11661 |
if (C.Kind == CC_JumpTable) |
--- |
| 11662 |
dbgs() << "JT:"; |
--- |
11662 |
dbgs() << "JT:"; |
--- |
| 11663 |
if (C.Kind == CC_BitTests) |
--- |
11663 |
if (C.Kind == CC_BitTests) |
--- |
| 11664 |
dbgs() << "BT:"; |
--- |
11664 |
dbgs() << "BT:"; |
--- |
| 11665 |
|
--- |
11665 |
|
--- |
| 11666 |
C.Low->getValue().print(dbgs(), true); |
--- |
11666 |
C.Low->getValue().print(dbgs(), true); |
--- |
| 11667 |
if (C.Low != C.High) { |
--- |
11667 |
if (C.Low != C.High) { |
--- |
| 11668 |
dbgs() << '-'; |
--- |
11668 |
dbgs() << '-'; |
--- |
| 11669 |
C.High->getValue().print(dbgs(), true); |
--- |
11669 |
C.High->getValue().print(dbgs(), true); |
--- |
| 11670 |
} |
--- |
11670 |
} |
--- |
| 11671 |
dbgs() << ' '; |
--- |
11671 |
dbgs() << ' '; |
--- |
| 11672 |
} |
--- |
11672 |
} |
--- |
| 11673 |
dbgs() << '\n'; |
--- |
11673 |
dbgs() << '\n'; |
--- |
| 11674 |
}); |
--- |
11674 |
}); |
--- |
| 11675 |
|
--- |
11675 |
|
--- |
| 11676 |
assert(!Clusters.empty()); |
0 |
11676 |
assert(!Clusters.empty()); |
0 |
| 11677 |
SwitchWorkList WorkList; |
0 |
11677 |
SwitchWorkList WorkList; |
0 |
| 11678 |
CaseClusterIt First = Clusters.begin(); |
0 |
11678 |
CaseClusterIt First = Clusters.begin(); |
0 |
| 11679 |
CaseClusterIt Last = Clusters.end() - 1; |
0 |
11679 |
CaseClusterIt Last = Clusters.end() - 1; |
0 |
| 11680 |
auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB); |
0 |
11680 |
auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB); |
0 |
| 11681 |
// Scale the branchprobability for DefaultMBB if the peel occurs and |
--- |
11681 |
// Scale the branchprobability for DefaultMBB if the peel occurs and |
--- |
| 11682 |
// DefaultMBB is not replaced. |
--- |
11682 |
// DefaultMBB is not replaced. |
--- |
| 11683 |
if (PeeledCaseProb != BranchProbability::getZero() && |
0 |
11683 |
if (PeeledCaseProb != BranchProbability::getZero() && |
0 |
| 11684 |
DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()]) |
0 |
11684 |
DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()]) |
0 |
| 11685 |
DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb); |
0 |
11685 |
DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb); |
0 |
| 11686 |
WorkList.push_back( |
0 |
11686 |
WorkList.push_back( |
0 |
| 11687 |
{PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb}); |
--- |
11687 |
{PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb}); |
--- |
| 11688 |
|
--- |
11688 |
|
--- |
| 11689 |
while (!WorkList.empty()) { |
0 |
11689 |
while (!WorkList.empty()) { |
0 |
| 11690 |
SwitchWorkListItem W = WorkList.pop_back_val(); |
0 |
11690 |
SwitchWorkListItem W = WorkList.pop_back_val(); |
0 |
| 11691 |
unsigned NumClusters = W.LastCluster - W.FirstCluster + 1; |
0 |
11691 |
unsigned NumClusters = W.LastCluster - W.FirstCluster + 1; |
0 |
| 11692 |
|
--- |
11692 |
|
--- |
| 11693 |
if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None && |
0 |
11693 |
if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None && |
0 |
| 11694 |
!DefaultMBB->getParent()->getFunction().hasMinSize()) { |
0 |
11694 |
!DefaultMBB->getParent()->getFunction().hasMinSize()) { |
0 |
| 11695 |
// For optimized builds, lower large range as a balanced binary tree. |
--- |
11695 |
// For optimized builds, lower large range as a balanced binary tree. |
--- |
| 11696 |
splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB); |
0 |
11696 |
splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB); |
0 |
| 11697 |
continue; |
0 |
11697 |
continue; |
0 |
| 11698 |
} |
--- |
11698 |
} |
--- |
| 11699 |
|
--- |
11699 |
|
--- |
| 11700 |
lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB); |
0 |
11700 |
lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB); |
0 |
| 11701 |
} |
--- |
11701 |
} |
--- |
| 11702 |
} |
0 |
11702 |
} |
0 |
| 11703 |
|
--- |
11703 |
|
--- |
| 11704 |
void SelectionDAGBuilder::visitStepVector(const CallInst &I) { |
0 |
11704 |
void SelectionDAGBuilder::visitStepVector(const CallInst &I) { |
0 |
| 11705 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11705 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11706 |
auto DL = getCurSDLoc(); |
0 |
11706 |
auto DL = getCurSDLoc(); |
0 |
| 11707 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
11707 |
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 11708 |
setValue(&I, DAG.getStepVector(DL, ResultVT)); |
0 |
11708 |
setValue(&I, DAG.getStepVector(DL, ResultVT)); |
0 |
| 11709 |
} |
0 |
11709 |
} |
0 |
| 11710 |
|
--- |
11710 |
|
--- |
| 11711 |
void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) { |
0 |
11711 |
void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) { |
0 |
| 11712 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11712 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11713 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
11713 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 11714 |
|
--- |
11714 |
|
--- |
| 11715 |
SDLoc DL = getCurSDLoc(); |
0 |
11715 |
SDLoc DL = getCurSDLoc(); |
0 |
| 11716 |
SDValue V = getValue(I.getOperand(0)); |
0 |
11716 |
SDValue V = getValue(I.getOperand(0)); |
0 |
| 11717 |
assert(VT == V.getValueType() && "Malformed vector.reverse!"); |
0 |
11717 |
assert(VT == V.getValueType() && "Malformed vector.reverse!"); |
0 |
| 11718 |
|
--- |
11718 |
|
--- |
| 11719 |
if (VT.isScalableVector()) { |
0 |
11719 |
if (VT.isScalableVector()) { |
0 |
| 11720 |
setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V)); |
0 |
11720 |
setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V)); |
0 |
| 11721 |
return; |
0 |
11721 |
return; |
0 |
| 11722 |
} |
--- |
11722 |
} |
--- |
| 11723 |
|
--- |
11723 |
|
--- |
| 11724 |
// Use VECTOR_SHUFFLE for the fixed-length vector |
--- |
11724 |
// Use VECTOR_SHUFFLE for the fixed-length vector |
--- |
| 11725 |
// to maintain existing behavior. |
--- |
11725 |
// to maintain existing behavior. |
--- |
| 11726 |
SmallVector Mask; |
0 |
11726 |
SmallVector Mask; |
0 |
| 11727 |
unsigned NumElts = VT.getVectorMinNumElements(); |
0 |
11727 |
unsigned NumElts = VT.getVectorMinNumElements(); |
0 |
| 11728 |
for (unsigned i = 0; i != NumElts; ++i) |
0 |
11728 |
for (unsigned i = 0; i != NumElts; ++i) |
0 |
| 11729 |
Mask.push_back(NumElts - 1 - i); |
0 |
11729 |
Mask.push_back(NumElts - 1 - i); |
0 |
| 11730 |
|
--- |
11730 |
|
--- |
| 11731 |
setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask)); |
0 |
11731 |
setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask)); |
0 |
| 11732 |
} |
0 |
11732 |
} |
0 |
| 11733 |
|
--- |
11733 |
|
--- |
| 11734 |
void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I) { |
0 |
11734 |
void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I) { |
0 |
| 11735 |
auto DL = getCurSDLoc(); |
0 |
11735 |
auto DL = getCurSDLoc(); |
0 |
| 11736 |
SDValue InVec = getValue(I.getOperand(0)); |
0 |
11736 |
SDValue InVec = getValue(I.getOperand(0)); |
0 |
| 11737 |
EVT OutVT = |
--- |
11737 |
EVT OutVT = |
--- |
| 11738 |
InVec.getValueType().getHalfNumVectorElementsVT(*DAG.getContext()); |
0 |
11738 |
InVec.getValueType().getHalfNumVectorElementsVT(*DAG.getContext()); |
0 |
| 11739 |
|
--- |
11739 |
|
--- |
| 11740 |
unsigned OutNumElts = OutVT.getVectorMinNumElements(); |
0 |
11740 |
unsigned OutNumElts = OutVT.getVectorMinNumElements(); |
0 |
| 11741 |
|
--- |
11741 |
|
--- |
| 11742 |
// ISD Node needs the input vectors split into two equal parts |
--- |
11742 |
// ISD Node needs the input vectors split into two equal parts |
--- |
| 11743 |
SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, |
0 |
11743 |
SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, |
0 |
| 11744 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
11744 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
| 11745 |
SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, |
0 |
11745 |
SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, |
0 |
| 11746 |
DAG.getVectorIdxConstant(OutNumElts, DL)); |
0 |
11746 |
DAG.getVectorIdxConstant(OutNumElts, DL)); |
0 |
| 11747 |
|
--- |
11747 |
|
--- |
| 11748 |
// Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing |
--- |
11748 |
// Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing |
--- |
| 11749 |
// legalisation and combines. |
--- |
11749 |
// legalisation and combines. |
--- |
| 11750 |
if (OutVT.isFixedLengthVector()) { |
0 |
11750 |
if (OutVT.isFixedLengthVector()) { |
0 |
| 11751 |
SDValue Even = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, |
0 |
11751 |
SDValue Even = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, |
0 |
| 11752 |
createStrideMask(0, 2, OutNumElts)); |
0 |
11752 |
createStrideMask(0, 2, OutNumElts)); |
0 |
| 11753 |
SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, |
0 |
11753 |
SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, |
0 |
| 11754 |
createStrideMask(1, 2, OutNumElts)); |
0 |
11754 |
createStrideMask(1, 2, OutNumElts)); |
0 |
| 11755 |
SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc()); |
0 |
11755 |
SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc()); |
0 |
| 11756 |
setValue(&I, Res); |
0 |
11756 |
setValue(&I, Res); |
0 |
| 11757 |
return; |
0 |
11757 |
return; |
0 |
| 11758 |
} |
--- |
11758 |
} |
--- |
| 11759 |
|
--- |
11759 |
|
--- |
| 11760 |
SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, |
0 |
11760 |
SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, |
0 |
| 11761 |
DAG.getVTList(OutVT, OutVT), Lo, Hi); |
0 |
11761 |
DAG.getVTList(OutVT, OutVT), Lo, Hi); |
0 |
| 11762 |
setValue(&I, Res); |
0 |
11762 |
setValue(&I, Res); |
0 |
| 11763 |
} |
0 |
11763 |
} |
0 |
| 11764 |
|
--- |
11764 |
|
--- |
| 11765 |
void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I) { |
0 |
11765 |
void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I) { |
0 |
| 11766 |
auto DL = getCurSDLoc(); |
0 |
11766 |
auto DL = getCurSDLoc(); |
0 |
| 11767 |
EVT InVT = getValue(I.getOperand(0)).getValueType(); |
0 |
11767 |
EVT InVT = getValue(I.getOperand(0)).getValueType(); |
0 |
| 11768 |
SDValue InVec0 = getValue(I.getOperand(0)); |
0 |
11768 |
SDValue InVec0 = getValue(I.getOperand(0)); |
0 |
| 11769 |
SDValue InVec1 = getValue(I.getOperand(1)); |
0 |
11769 |
SDValue InVec1 = getValue(I.getOperand(1)); |
0 |
| 11770 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11770 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11771 |
EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
11771 |
EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 11772 |
|
--- |
11772 |
|
--- |
| 11773 |
// Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing |
--- |
11773 |
// Use VECTOR_SHUFFLE for fixed-length vectors to benefit from existing |
--- |
| 11774 |
// legalisation and combines. |
--- |
11774 |
// legalisation and combines. |
--- |
| 11775 |
if (OutVT.isFixedLengthVector()) { |
0 |
11775 |
if (OutVT.isFixedLengthVector()) { |
0 |
| 11776 |
unsigned NumElts = InVT.getVectorMinNumElements(); |
0 |
11776 |
unsigned NumElts = InVT.getVectorMinNumElements(); |
0 |
| 11777 |
SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVec0, InVec1); |
0 |
11777 |
SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVec0, InVec1); |
0 |
| 11778 |
setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT), |
0 |
11778 |
setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT), |
0 |
| 11779 |
createInterleaveMask(NumElts, 2))); |
0 |
11779 |
createInterleaveMask(NumElts, 2))); |
0 |
| 11780 |
return; |
0 |
11780 |
return; |
0 |
| 11781 |
} |
--- |
11781 |
} |
--- |
| 11782 |
|
--- |
11782 |
|
--- |
| 11783 |
SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, |
0 |
11783 |
SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, |
0 |
| 11784 |
DAG.getVTList(InVT, InVT), InVec0, InVec1); |
0 |
11784 |
DAG.getVTList(InVT, InVT), InVec0, InVec1); |
0 |
| 11785 |
Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Res.getValue(0), |
0 |
11785 |
Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Res.getValue(0), |
0 |
| 11786 |
Res.getValue(1)); |
--- |
11786 |
Res.getValue(1)); |
--- |
| 11787 |
setValue(&I, Res); |
0 |
11787 |
setValue(&I, Res); |
0 |
| 11788 |
} |
0 |
11788 |
} |
0 |
| 11789 |
|
--- |
11789 |
|
--- |
| 11790 |
void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) { |
0 |
11790 |
void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) { |
0 |
| 11791 |
SmallVector ValueVTs; |
0 |
11791 |
SmallVector ValueVTs; |
0 |
| 11792 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), |
0 |
11792 |
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), |
0 |
| 11793 |
ValueVTs); |
--- |
11793 |
ValueVTs); |
--- |
| 11794 |
unsigned NumValues = ValueVTs.size(); |
0 |
11794 |
unsigned NumValues = ValueVTs.size(); |
0 |
| 11795 |
if (NumValues == 0) return; |
0 |
11795 |
if (NumValues == 0) return; |
0 |
| 11796 |
|
--- |
11796 |
|
--- |
| 11797 |
SmallVector Values(NumValues); |
0 |
11797 |
SmallVector Values(NumValues); |
0 |
| 11798 |
SDValue Op = getValue(I.getOperand(0)); |
0 |
11798 |
SDValue Op = getValue(I.getOperand(0)); |
0 |
| 11799 |
|
--- |
11799 |
|
--- |
| 11800 |
for (unsigned i = 0; i != NumValues; ++i) |
0 |
11800 |
for (unsigned i = 0; i != NumValues; ++i) |
0 |
| 11801 |
Values[i] = DAG.getNode(ISD::FREEZE, getCurSDLoc(), ValueVTs[i], |
0 |
11801 |
Values[i] = DAG.getNode(ISD::FREEZE, getCurSDLoc(), ValueVTs[i], |
0 |
| 11802 |
SDValue(Op.getNode(), Op.getResNo() + i)); |
0 |
11802 |
SDValue(Op.getNode(), Op.getResNo() + i)); |
0 |
| 11803 |
|
--- |
11803 |
|
--- |
| 11804 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
11804 |
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
| 11805 |
DAG.getVTList(ValueVTs), Values)); |
0 |
11805 |
DAG.getVTList(ValueVTs), Values)); |
0 |
| 11806 |
} |
0 |
11806 |
} |
0 |
| 11807 |
|
--- |
11807 |
|
--- |
| 11808 |
void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) { |
0 |
11808 |
void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) { |
0 |
| 11809 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11809 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11810 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
11810 |
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); |
0 |
| 11811 |
|
--- |
11811 |
|
--- |
| 11812 |
SDLoc DL = getCurSDLoc(); |
0 |
11812 |
SDLoc DL = getCurSDLoc(); |
0 |
| 11813 |
SDValue V1 = getValue(I.getOperand(0)); |
0 |
11813 |
SDValue V1 = getValue(I.getOperand(0)); |
0 |
| 11814 |
SDValue V2 = getValue(I.getOperand(1)); |
0 |
11814 |
SDValue V2 = getValue(I.getOperand(1)); |
0 |
| 11815 |
int64_t Imm = cast(I.getOperand(2))->getSExtValue(); |
0 |
11815 |
int64_t Imm = cast(I.getOperand(2))->getSExtValue(); |
0 |
| 11816 |
|
--- |
11816 |
|
--- |
| 11817 |
// VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node. |
--- |
11817 |
// VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node. |
--- |
| 11818 |
if (VT.isScalableVector()) { |
0 |
11818 |
if (VT.isScalableVector()) { |
0 |
| 11819 |
MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); |
0 |
11819 |
MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); |
0 |
| 11820 |
setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, |
0 |
11820 |
setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, |
0 |
| 11821 |
DAG.getConstant(Imm, DL, IdxVT))); |
0 |
11821 |
DAG.getConstant(Imm, DL, IdxVT))); |
0 |
| 11822 |
return; |
0 |
11822 |
return; |
0 |
| 11823 |
} |
--- |
11823 |
} |
--- |
| 11824 |
|
--- |
11824 |
|
--- |
| 11825 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
11825 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 11826 |
|
--- |
11826 |
|
--- |
| 11827 |
uint64_t Idx = (NumElts + Imm) % NumElts; |
0 |
11827 |
uint64_t Idx = (NumElts + Imm) % NumElts; |
0 |
| 11828 |
|
--- |
11828 |
|
--- |
| 11829 |
// Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors. |
--- |
11829 |
// Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors. |
--- |
| 11830 |
SmallVector Mask; |
0 |
11830 |
SmallVector Mask; |
0 |
| 11831 |
for (unsigned i = 0; i < NumElts; ++i) |
0 |
11831 |
for (unsigned i = 0; i < NumElts; ++i) |
0 |
| 11832 |
Mask.push_back(Idx + i); |
0 |
11832 |
Mask.push_back(Idx + i); |
0 |
| 11833 |
setValue(&I, DAG.getVectorShuffle(VT, DL, V1, V2, Mask)); |
0 |
11833 |
setValue(&I, DAG.getVectorShuffle(VT, DL, V1, V2, Mask)); |
0 |
| 11834 |
} |
0 |
11834 |
} |
0 |
| 11835 |
|
--- |
11835 |
|
--- |
| 11836 |
// Consider the following MIR after SelectionDAG, which produces output in |
--- |
11836 |
// Consider the following MIR after SelectionDAG, which produces output in |
--- |
| 11837 |
// phyregs in the first case or virtregs in the second case. |
--- |
11837 |
// phyregs in the first case or virtregs in the second case. |
--- |
| 11838 |
// |
--- |
11838 |
// |
--- |
| 11839 |
// INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx |
--- |
11839 |
// INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx |
--- |
| 11840 |
// %5:gr32 = COPY $ebx |
--- |
11840 |
// %5:gr32 = COPY $ebx |
--- |
| 11841 |
// %6:gr32 = COPY $edx |
--- |
11841 |
// %6:gr32 = COPY $edx |
--- |
| 11842 |
// %1:gr32 = COPY %6:gr32 |
--- |
11842 |
// %1:gr32 = COPY %6:gr32 |
--- |
| 11843 |
// %0:gr32 = COPY %5:gr32 |
--- |
11843 |
// %0:gr32 = COPY %5:gr32 |
--- |
| 11844 |
// |
--- |
11844 |
// |
--- |
| 11845 |
// INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32 |
--- |
11845 |
// INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32 |
--- |
| 11846 |
// %1:gr32 = COPY %6:gr32 |
--- |
11846 |
// %1:gr32 = COPY %6:gr32 |
--- |
| 11847 |
// %0:gr32 = COPY %5:gr32 |
--- |
11847 |
// %0:gr32 = COPY %5:gr32 |
--- |
| 11848 |
// |
--- |
11848 |
// |
--- |
| 11849 |
// Given %0, we'd like to return $ebx in the first case and %5 in the second. |
--- |
11849 |
// Given %0, we'd like to return $ebx in the first case and %5 in the second. |
--- |
| 11850 |
// Given %1, we'd like to return $edx in the first case and %6 in the second. |
--- |
11850 |
// Given %1, we'd like to return $edx in the first case and %6 in the second. |
--- |
| 11851 |
// |
--- |
11851 |
// |
--- |
| 11852 |
// If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap |
--- |
11852 |
// If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap |
--- |
| 11853 |
// to a single virtreg (such as %0). The remaining outputs monotonically |
--- |
11853 |
// to a single virtreg (such as %0). The remaining outputs monotonically |
--- |
| 11854 |
// increase in virtreg number from there. If a callbr has no outputs, then it |
--- |
11854 |
// increase in virtreg number from there. If a callbr has no outputs, then it |
--- |
| 11855 |
// should not have a corresponding callbr landingpad; in fact, the callbr |
--- |
11855 |
// should not have a corresponding callbr landingpad; in fact, the callbr |
--- |
| 11856 |
// landingpad would not even be able to refer to such a callbr. |
--- |
11856 |
// landingpad would not even be able to refer to such a callbr. |
--- |
| 11857 |
static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) { |
0 |
11857 |
static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) { |
0 |
| 11858 |
MachineInstr *MI = MRI.def_begin(Reg)->getParent(); |
0 |
11858 |
MachineInstr *MI = MRI.def_begin(Reg)->getParent(); |
0 |
| 11859 |
// There is definitely at least one copy. |
--- |
11859 |
// There is definitely at least one copy. |
--- |
| 11860 |
assert(MI->getOpcode() == TargetOpcode::COPY && |
0 |
11860 |
assert(MI->getOpcode() == TargetOpcode::COPY && |
0 |
| 11861 |
"start of copy chain MUST be COPY"); |
--- |
11861 |
"start of copy chain MUST be COPY"); |
--- |
| 11862 |
Reg = MI->getOperand(1).getReg(); |
0 |
11862 |
Reg = MI->getOperand(1).getReg(); |
0 |
| 11863 |
MI = MRI.def_begin(Reg)->getParent(); |
0 |
11863 |
MI = MRI.def_begin(Reg)->getParent(); |
0 |
| 11864 |
// There may be an optional second copy. |
--- |
11864 |
// There may be an optional second copy. |
--- |
| 11865 |
if (MI->getOpcode() == TargetOpcode::COPY) { |
0 |
11865 |
if (MI->getOpcode() == TargetOpcode::COPY) { |
0 |
| 11866 |
assert(Reg.isVirtual() && "expected COPY of virtual register"); |
0 |
11866 |
assert(Reg.isVirtual() && "expected COPY of virtual register"); |
0 |
| 11867 |
Reg = MI->getOperand(1).getReg(); |
0 |
11867 |
Reg = MI->getOperand(1).getReg(); |
0 |
| 11868 |
assert(Reg.isPhysical() && "expected COPY of physical register"); |
0 |
11868 |
assert(Reg.isPhysical() && "expected COPY of physical register"); |
0 |
| 11869 |
MI = MRI.def_begin(Reg)->getParent(); |
0 |
11869 |
MI = MRI.def_begin(Reg)->getParent(); |
0 |
| 11870 |
} |
--- |
11870 |
} |
--- |
| 11871 |
// The start of the chain must be an INLINEASM_BR. |
--- |
11871 |
// The start of the chain must be an INLINEASM_BR. |
--- |
| 11872 |
assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR && |
0 |
11872 |
assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR && |
0 |
| 11873 |
"end of copy chain MUST be INLINEASM_BR"); |
--- |
11873 |
"end of copy chain MUST be INLINEASM_BR"); |
--- |
| 11874 |
return Reg; |
0 |
11874 |
return Reg; |
0 |
| 11875 |
} |
--- |
11875 |
} |
--- |
| 11876 |
|
--- |
11876 |
|
--- |
| 11877 |
// We must do this walk rather than the simpler |
--- |
11877 |
// We must do this walk rather than the simpler |
--- |
| 11878 |
// setValue(&I, getCopyFromRegs(CBR, CBR->getType())); |
--- |
11878 |
// setValue(&I, getCopyFromRegs(CBR, CBR->getType())); |
--- |
| 11879 |
// otherwise we will end up with copies of virtregs only valid along direct |
--- |
11879 |
// otherwise we will end up with copies of virtregs only valid along direct |
--- |
| 11880 |
// edges. |
--- |
11880 |
// edges. |
--- |
| 11881 |
void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) { |
0 |
11881 |
void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) { |
0 |
| 11882 |
SmallVector ResultVTs; |
0 |
11882 |
SmallVector ResultVTs; |
0 |
| 11883 |
SmallVector ResultValues; |
0 |
11883 |
SmallVector ResultValues; |
0 |
| 11884 |
const auto *CBR = |
--- |
11884 |
const auto *CBR = |
--- |
| 11885 |
cast(I.getParent()->getUniquePredecessor()->getTerminator()); |
0 |
11885 |
cast(I.getParent()->getUniquePredecessor()->getTerminator()); |
0 |
| 11886 |
|
--- |
11886 |
|
--- |
| 11887 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11887 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11888 |
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); |
0 |
11888 |
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); |
0 |
| 11889 |
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); |
0 |
11889 |
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); |
0 |
| 11890 |
|
--- |
11890 |
|
--- |
| 11891 |
unsigned InitialDef = FuncInfo.ValueMap[CBR]; |
0 |
11891 |
unsigned InitialDef = FuncInfo.ValueMap[CBR]; |
0 |
| 11892 |
SDValue Chain = DAG.getRoot(); |
0 |
11892 |
SDValue Chain = DAG.getRoot(); |
0 |
| 11893 |
|
--- |
11893 |
|
--- |
| 11894 |
// Re-parse the asm constraints string. |
--- |
11894 |
// Re-parse the asm constraints string. |
--- |
| 11895 |
TargetLowering::AsmOperandInfoVector TargetConstraints = |
--- |
11895 |
TargetLowering::AsmOperandInfoVector TargetConstraints = |
--- |
| 11896 |
TLI.ParseConstraints(DAG.getDataLayout(), TRI, *CBR); |
0 |
11896 |
TLI.ParseConstraints(DAG.getDataLayout(), TRI, *CBR); |
0 |
| 11897 |
for (auto &T : TargetConstraints) { |
0 |
11897 |
for (auto &T : TargetConstraints) { |
0 |
| 11898 |
SDISelAsmOperandInfo OpInfo(T); |
0 |
11898 |
SDISelAsmOperandInfo OpInfo(T); |
0 |
| 11899 |
if (OpInfo.Type != InlineAsm::isOutput) |
0 |
11899 |
if (OpInfo.Type != InlineAsm::isOutput) |
0 |
| 11900 |
continue; |
0 |
11900 |
continue; |
0 |
| 11901 |
|
--- |
11901 |
|
--- |
| 11902 |
// Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the |
--- |
11902 |
// Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the |
--- |
| 11903 |
// individual constraint. |
--- |
11903 |
// individual constraint. |
--- |
| 11904 |
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); |
0 |
11904 |
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); |
0 |
| 11905 |
|
--- |
11905 |
|
--- |
| 11906 |
switch (OpInfo.ConstraintType) { |
0 |
11906 |
switch (OpInfo.ConstraintType) { |
0 |
| 11907 |
case TargetLowering::C_Register: |
0 |
11907 |
case TargetLowering::C_Register: |
0 |
| 11908 |
case TargetLowering::C_RegisterClass: { |
--- |
11908 |
case TargetLowering::C_RegisterClass: { |
--- |
| 11909 |
// Fill in OpInfo.AssignedRegs.Regs. |
--- |
11909 |
// Fill in OpInfo.AssignedRegs.Regs. |
--- |
| 11910 |
getRegistersForValue(DAG, getCurSDLoc(), OpInfo, OpInfo); |
0 |
11910 |
getRegistersForValue(DAG, getCurSDLoc(), OpInfo, OpInfo); |
0 |
| 11911 |
|
--- |
11911 |
|
--- |
| 11912 |
// getRegistersForValue may produce 1 to many registers based on whether |
--- |
11912 |
// getRegistersForValue may produce 1 to many registers based on whether |
--- |
| 11913 |
// the OpInfo.ConstraintVT is legal on the target or not. |
--- |
11913 |
// the OpInfo.ConstraintVT is legal on the target or not. |
--- |
| 11914 |
for (size_t i = 0, e = OpInfo.AssignedRegs.Regs.size(); i != e; ++i) { |
0 |
11914 |
for (size_t i = 0, e = OpInfo.AssignedRegs.Regs.size(); i != e; ++i) { |
0 |
| 11915 |
Register OriginalDef = FollowCopyChain(MRI, InitialDef++); |
0 |
11915 |
Register OriginalDef = FollowCopyChain(MRI, InitialDef++); |
0 |
| 11916 |
if (Register::isPhysicalRegister(OriginalDef)) |
0 |
11916 |
if (Register::isPhysicalRegister(OriginalDef)) |
0 |
| 11917 |
FuncInfo.MBB->addLiveIn(OriginalDef); |
0 |
11917 |
FuncInfo.MBB->addLiveIn(OriginalDef); |
0 |
| 11918 |
// Update the assigned registers to use the original defs. |
--- |
11918 |
// Update the assigned registers to use the original defs. |
--- |
| 11919 |
OpInfo.AssignedRegs.Regs[i] = OriginalDef; |
0 |
11919 |
OpInfo.AssignedRegs.Regs[i] = OriginalDef; |
0 |
| 11920 |
} |
--- |
11920 |
} |
--- |
| 11921 |
|
--- |
11921 |
|
--- |
| 11922 |
SDValue V = OpInfo.AssignedRegs.getCopyFromRegs( |
0 |
11922 |
SDValue V = OpInfo.AssignedRegs.getCopyFromRegs( |
0 |
| 11923 |
DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, CBR); |
0 |
11923 |
DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, CBR); |
0 |
| 11924 |
ResultValues.push_back(V); |
0 |
11924 |
ResultValues.push_back(V); |
0 |
| 11925 |
ResultVTs.push_back(OpInfo.ConstraintVT); |
0 |
11925 |
ResultVTs.push_back(OpInfo.ConstraintVT); |
0 |
| 11926 |
break; |
0 |
11926 |
break; |
0 |
| 11927 |
} |
--- |
11927 |
} |
--- |
| 11928 |
case TargetLowering::C_Other: { |
0 |
11928 |
case TargetLowering::C_Other: { |
0 |
| 11929 |
SDValue Flag; |
0 |
11929 |
SDValue Flag; |
0 |
| 11930 |
SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(), |
0 |
11930 |
SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(), |
0 |
| 11931 |
OpInfo, DAG); |
--- |
11931 |
OpInfo, DAG); |
--- |
| 11932 |
++InitialDef; |
0 |
11932 |
++InitialDef; |
0 |
| 11933 |
ResultValues.push_back(V); |
0 |
11933 |
ResultValues.push_back(V); |
0 |
| 11934 |
ResultVTs.push_back(OpInfo.ConstraintVT); |
0 |
11934 |
ResultVTs.push_back(OpInfo.ConstraintVT); |
0 |
| 11935 |
break; |
0 |
11935 |
break; |
0 |
| 11936 |
} |
--- |
11936 |
} |
--- |
| 11937 |
default: |
0 |
11937 |
default: |
0 |
| 11938 |
break; |
0 |
11938 |
break; |
0 |
| 11939 |
} |
--- |
11939 |
} |
--- |
| 11940 |
} |
0 |
11940 |
} |
0 |
| 11941 |
SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
11941 |
SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), |
0 |
| 11942 |
DAG.getVTList(ResultVTs), ResultValues); |
0 |
11942 |
DAG.getVTList(ResultVTs), ResultValues); |
0 |
| 11943 |
setValue(&I, V); |
0 |
11943 |
setValue(&I, V); |
0 |
| 11944 |
} |
0 |
11944 |
} |
0 |
| 11945 |
|
--- |
11945 |
|
--- |